From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Thu, 27 Sep 2012 18:45:26 +0200
Subject: [U-Boot] [PATCH 1/6] am33xx: Enable UART{1,2,4,5} clocks
In-Reply-To: <20120927162543.GJ14678@bill-the-cat>
References: <1348689859-21803-1-git-send-email-andrew@bradfordembedded.com>
	<201209271813.36568.marex@denx.de>
	<20120927162543.GJ14678@bill-the-cat>
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Dear Tom Rini,

> On Thu, Sep 27, 2012 at 06:13:36PM +0200, Marek Vasut wrote:
> > Dear Andrew Bradford,
> > 
> > > If configured to use UART{1,2,4,5}, such as on the Beaglebone RS232
> > > cape, enable the required clocks for the UART in use.
> > > 
> > > Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
> > > ---
> > > 
> > >  arch/arm/cpu/armv7/am33xx/clock.c |   28 ++++++++++++++++++++++++++++
> > >  1 file changed, 28 insertions(+)
> > > 
> > > diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
> > > b/arch/arm/cpu/armv7/am33xx/clock.c index 2b19506..4eb9226 100644
> > > --- a/arch/arm/cpu/armv7/am33xx/clock.c
> > > +++ b/arch/arm/cpu/armv7/am33xx/clock.c
> > > @@ -114,6 +114,34 @@ static void enable_per_clocks(void)
> > > 
> > >  	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
> > >  	
> > >  		;
> > > 
> > > +	/* UART1 */
> > > +#ifdef CONFIG_SERIAL2
> > > +	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
> > > +	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
> > > +		;
> > 
> > Call WATCHDOG_RESET() here, fix glboally
> 
> We don't have WATCHDOG_RESET...

You do, and it opts-out to udelay(1) is most cases.

Best regards,
Marek Vasut