From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Sat, 13 Oct 2012 13:21:36 +0200 Subject: [U-Boot] [PATCH v5 09/16] arm: Add control over cachability of memory regions In-Reply-To: <1349732556-30700-10-git-send-email-sjg@chromium.org> References: <1349732556-30700-1-git-send-email-sjg@chromium.org> <1349732556-30700-10-git-send-email-sjg@chromium.org> Message-ID: <20121013132136.28228eb9@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Simon, No comment on the patch itself except for one general question: On Mon, 8 Oct 2012 14:42:29 -0700, Simon Glass wrote: > Add support for adjusting the cachability of an L1 section by updating > the MMU. The mmu_set_region_dcache() function allows drivers to make > these changes after the MMU is set up. Can you just reformulate this a bit? "L1" is not necessary about cache (there can be for instance TCM, frequently (if not correctly) called L1 RAM where I work, for the obvious reason that they are accessed at the same level/layer as the L1 cache. Also, off, writethrough and copyback are "cache behaviors" in ARM parlance, not "cachability". Therefore I would prefer something like "Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behavior() function allows drivers to make these changes after the MMU is set up." (note the suggestion includes slightly renaming the function) Thanks in advance for considering this suggestion. Amicalement, -- Albert.