[U-Boot] [PATCH V2 13/21] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset

Troy Kisky
2012-09-22T02:39:10Z

Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 3a1f1bc..904276a 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -75,7 +75,7 @@ IOMUX_ENTRY1(IOM_DRAM_RAS, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
IOMUX_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)

-IOMUX_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+IOMUX_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
IOMUX_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
IOMUX_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)
--
1.7.9.5