* [U-Boot] [PATCH v2] USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY
@ 2012-09-13 19:38 Tom Rini
2012-10-17 15:39 ` Tom Rini
0 siblings, 1 reply; 2+ messages in thread
From: Tom Rini @ 2012-09-13 19:38 UTC (permalink / raw)
To: u-boot
From: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
The endpoint rx count register value will be zero if it is read before
receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.
Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before
reading endpoint rx count register. Proceed with rx count read and
FIFO read only if RXPKTRDY bit is set.
Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
---
drivers/usb/musb/musb_udc.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index 09cdec3..e0b4217 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -640,8 +640,17 @@ static void musb_peri_ep0(void)
static void musb_peri_rx_ep(unsigned int ep)
{
- u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
+ u16 peri_rxcount;
+ u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
+ if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s %d without MUSB_RXCSR_RXPKTRDY set\n",
+ __PRETTY_FUNCTION__, ep);
+ return;
+ }
+
+ peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
if (peri_rxcount) {
struct usb_endpoint_instance *endpoint;
u32 length;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH v2] USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY
2012-09-13 19:38 [U-Boot] [PATCH v2] USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY Tom Rini
@ 2012-10-17 15:39 ` Tom Rini
0 siblings, 0 replies; 2+ messages in thread
From: Tom Rini @ 2012-10-17 15:39 UTC (permalink / raw)
To: u-boot
On Thu, Sep 13, 2012 at 12:38:16PM -0700, Tom Rini wrote:
> From: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
>
> The endpoint rx count register value will be zero if it is read before
> receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.
>
> Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before
> reading endpoint rx count register. Proceed with rx count read and
> FIFO read only if RXPKTRDY bit is set.
>
> Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
> Signed-off-by: Tom Rini <trini@ti.com>
Applied to u-boot-ti/master, thanks!
--
Tom
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2012-10-17 15:39 ` Tom Rini
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