From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Thu, 18 Oct 2012 20:48:58 +0200 Subject: [U-Boot] [u-boot] Adding missing CONFIG_SYS_CACHELINE_SIZE to boards definitions In-Reply-To: <506D48C0.4040407@bus-elektronik.de> References: <1345795995-24656-5-git-send-email-l.majewski@samsung.com> <20121003230030.GC7623@bill-the-cat> <20121004091805.51060cac@amdc308.digital.local> <506D48C0.4040407@bus-elektronik.de> Message-ID: <20121018204858.2ca96189@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi esw, (resending as it was erroneously posted on gmane; sorry for any dupes) On Thu, 4 Oct 2012 10:28:48 +0200, esw wrote: > Dear Lukasz, > > > Hi Jens and Helmut, > > > >> On Thu, Aug 23, 2012 at 10:13:13PM -0000, Lukasz Majewski wrote: > >> > >>> The restoration of GPT table (both primary and secondary) is now > >>> possible. Simple GUID generation is supported. > >>> > >>> Signed-off-by: Lukasz Majewski > >>> Signed-off-by: Kyungmin Park > >> > >> While the changes are fine, tt01 and eb_cpux9k2 use CONFIG_PART_EFI > >> and do not set CONFIG_SYS_CACHELINE_SIZE and so fail to build after > >> this patch. tt01 is easily fixable (it relies on a non-exported > >> define elsewhere to 32) but the eb_cpu9k2 please contact the listed > >> board maintainer to get the define added. > >> > > > > Would it be possible to add the CONFIG_SYS_CACHELINE_SIZE > > definition to ./include/configs/{tty01|eb_cpux9k2} boards definition? > > > The eb_cpux9k2 board based on at91rm9200 soc. This soc has currently no cache implementation. So I think your run in this error. > > The attached patch sets the define to the soc default. > > We can also set #define CONFIG_SYS_DCACHE_OFF > > regards Jens If this is to be considered an actual patch submission, then please submit via git format-patch/git send-email or patman, and copy the at91 custodian. This patch has been marked as "changes requested" in PW. Amicalement, -- Albert.