From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anatolij Gustschin <agust@denx.de>
Date: Fri, 19 Oct 2012 22:13:55 +0200
Subject: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when missing
 USB PHY clock
In-Reply-To: <201210180621.57010.marex@denx.de>
References: <1350528023-17907-1-git-send-email-Shengzhou.Liu@freescale.com>
	<201210180621.57010.marex@denx.de>
Message-ID: <20121019221355.31d41e84@wker>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hi,

On Thu, 18 Oct 2012 06:21:56 +0200
Marek Vasut <marex@denx.de> wrote:

> Dear Shengzhou Liu,
> 
> > when missing USB PHY clock, u-boot will hang during USB
> > initialization when issuing "usb start". We should check
> > USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case.
> > 
> > Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> 
> CCing PPC experts.
...
> > @@ -82,18 +94,16 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr,
> > struct ehci_hcor **hcor) udelay(1000); /* delay required for PHY Clk to
> > appear */
> >  #endif
> >  		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
> > +		setbits_be32(&ehci->control, USB_EN);
> >  	} else {
> > -#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
> > -		clrbits_be32(&ehci->control, UTMI_PHY_EN);
> >  		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
> > +		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
> >  		udelay(1000); /* delay required for PHY Clk to appear */
> > -#endif
> > +		if (!usb_phy_clk_valid(ehci))
> > +			return -EINVAL;
> >  		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
> >  	}
> > 
> > -	/* Enable interface. */
> > -	setbits_be32(&ehci->control, USB_EN);

you moved the USB interface enabling before the PHY CLK check but the
commit description doesn't mention why it is needed. It would be good
to mention the reason in the commit log.

Thanks,
Anatolij