From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anatolij Gustschin <agust@denx.de>
Date: Sat, 20 Oct 2012 01:58:12 +0200
Subject: [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
In-Reply-To: <1349532964-8480-1-git-send-email-Ying.liu@freescale.com>
References: <1349532964-8480-1-git-send-email-Ying.liu@freescale.com>
Message-ID: <20121020015812.0f16e0ee@wker>
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To: u-boot@lists.denx.de

Hi,
On Sat, 6 Oct 2012 22:16:04 +0800
Liu Ying <Ying.liu@freescale.com> wrote:

> From: Liu Ying <Ying.Liu@freescale.com>
> 
> This patch checks self-clear sw_ipu_rst bit in
> SCR register of SRC controller to be cleared
> after setting it to high to reset IPUv3. This
> makes sure that IPUv3 finishes sofware reset.
> A timeout mechanism is added to stop polling
> on the bit status in case the bit could not be
> cleared by the hardware automatically within
> 10 millisecond.
> 
> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
> ---
>  drivers/video/ipu_common.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)

applied, thanks!

Anatolij