* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
@ 2012-10-06 14:16 Liu Ying
2012-10-06 18:00 ` Eric Nelson
2012-10-19 23:58 ` Anatolij Gustschin
0 siblings, 2 replies; 6+ messages in thread
From: Liu Ying @ 2012-10-06 14:16 UTC (permalink / raw)
To: u-boot
From: Liu Ying <Ying.Liu@freescale.com>
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
---
drivers/video/ipu_common.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 2020da9..fcc1745 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -94,6 +94,7 @@ struct ipu_ch_param {
temp1; \
})
+#define IPU_SW_RST_TOUT_USEC (10000)
void clk_enable(struct clk *clk)
{
@@ -392,11 +393,20 @@ void ipu_reset(void)
{
u32 *reg;
u32 value;
+ int timeout = IPU_SW_RST_TOUT_USEC;
reg = (u32 *)SRC_BASE_ADDR;
value = __raw_readl(reg);
value = value | SW_IPU_RST;
__raw_writel(value, reg);
+
+ while (__raw_readl(reg) & SW_IPU_RST) {
+ udelay(1);
+ if (!(timeout--)) {
+ printf("ipu software reset timeout\n");
+ break;
+ }
+ };
}
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
2012-10-06 14:16 [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly Liu Ying
@ 2012-10-06 18:00 ` Eric Nelson
2012-10-19 23:58 ` Anatolij Gustschin
1 sibling, 0 replies; 6+ messages in thread
From: Eric Nelson @ 2012-10-06 18:00 UTC (permalink / raw)
To: u-boot
Hi Liu Ying,
On 10/06/2012 07:16 AM, Liu Ying wrote:
> From: Liu Ying<Ying.Liu@freescale.com>
>
> This patch checks self-clear sw_ipu_rst bit in
> SCR register of SRC controller to be cleared
> after setting it to high to reset IPUv3. This
> makes sure that IPUv3 finishes sofware reset.
> A timeout mechanism is added to stop polling
> on the bit status in case the bit could not be
> cleared by the hardware automatically within
> 10 millisecond.
>
> Signed-off-by: Liu Ying<Ying.Liu@freescale.com>
> ---
> drivers/video/ipu_common.c | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
> index 2020da9..fcc1745 100644
> --- a/drivers/video/ipu_common.c
> +++ b/drivers/video/ipu_common.c
> @@ -94,6 +94,7 @@ struct ipu_ch_param {
> temp1; \
> })
>
> +#define IPU_SW_RST_TOUT_USEC (10000)
>
> void clk_enable(struct clk *clk)
> {
> @@ -392,11 +393,20 @@ void ipu_reset(void)
> {
> u32 *reg;
> u32 value;
> + int timeout = IPU_SW_RST_TOUT_USEC;
>
> reg = (u32 *)SRC_BASE_ADDR;
> value = __raw_readl(reg);
> value = value | SW_IPU_RST;
> __raw_writel(value, reg);
> +
> + while (__raw_readl(reg)& SW_IPU_RST) {
> + udelay(1);
> + if (!(timeout--)) {
> + printf("ipu software reset timeout\n");
> + break;
> + }
> + };
> }
>
> /*
Tested in the normal (successful) case on SABRE Lite.
Is there a situation under which this is known to fail or
is that a hypothetical?
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
2012-10-06 14:16 [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly Liu Ying
2012-10-06 18:00 ` Eric Nelson
@ 2012-10-19 23:58 ` Anatolij Gustschin
1 sibling, 0 replies; 6+ messages in thread
From: Anatolij Gustschin @ 2012-10-19 23:58 UTC (permalink / raw)
To: u-boot
Hi,
On Sat, 6 Oct 2012 22:16:04 +0800
Liu Ying <Ying.liu@freescale.com> wrote:
> From: Liu Ying <Ying.Liu@freescale.com>
>
> This patch checks self-clear sw_ipu_rst bit in
> SCR register of SRC controller to be cleared
> after setting it to high to reset IPUv3. This
> makes sure that IPUv3 finishes sofware reset.
> A timeout mechanism is added to stop polling
> on the bit status in case the bit could not be
> cleared by the hardware automatically within
> 10 millisecond.
>
> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
> ---
> drivers/video/ipu_common.c | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
applied, thanks!
Anatolij
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
@ 2012-10-06 10:32 Liu Ying
2012-10-06 12:59 ` Fabio Estevam
0 siblings, 1 reply; 6+ messages in thread
From: Liu Ying @ 2012-10-06 10:32 UTC (permalink / raw)
To: u-boot
From: Liu Ying <Ying.Liu@freescale.com>
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
---
drivers/video/ipu_common.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 2020da9..03b7382 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -397,6 +397,9 @@ void ipu_reset(void)
value = __raw_readl(reg);
value = value | SW_IPU_RST;
__raw_writel(value, reg);
+
+ while (__raw_readl(reg) & SW_IPU_RST)
+ ;
}
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
2012-10-06 10:32 Liu Ying
@ 2012-10-06 12:59 ` Fabio Estevam
2012-10-06 12:59 ` Fabio Estevam
0 siblings, 1 reply; 6+ messages in thread
From: Fabio Estevam @ 2012-10-06 12:59 UTC (permalink / raw)
To: u-boot
Hi Liu Ying,
On Sat, Oct 6, 2012 at 7:32 AM, Liu Ying <Ying.liu@freescale.com> wrote:
> @@ -397,6 +397,9 @@ void ipu_reset(void)
> value = __raw_readl(reg);
> value = value | SW_IPU_RST;
> __raw_writel(value, reg);
> +
> + while (__raw_readl(reg) & SW_IPU_RST)
> + ;
Ok, but if the reset fails we would hand the whole system.
Wouldn't it be better to add a timeout here?
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly
2012-10-06 12:59 ` Fabio Estevam
@ 2012-10-06 12:59 ` Fabio Estevam
0 siblings, 0 replies; 6+ messages in thread
From: Fabio Estevam @ 2012-10-06 12:59 UTC (permalink / raw)
To: u-boot
On Sat, Oct 6, 2012 at 9:59 AM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Liu Ying,
>
> On Sat, Oct 6, 2012 at 7:32 AM, Liu Ying <Ying.liu@freescale.com> wrote:
>
>> @@ -397,6 +397,9 @@ void ipu_reset(void)
>> value = __raw_readl(reg);
>> value = value | SW_IPU_RST;
>> __raw_writel(value, reg);
>> +
>> + while (__raw_readl(reg) & SW_IPU_RST)
>> + ;
>
> Ok, but if the reset fails we would hand the whole system.
I mean "hang"
>
> Wouldn't it be better to add a timeout here?
>
> Regards,
>
> Fabio Estevam
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-10-19 23:58 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2012-10-06 14:16 [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly Liu Ying
2012-10-06 18:00 ` Eric Nelson
2012-10-19 23:58 ` Anatolij Gustschin
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2012-10-06 10:32 Liu Ying
2012-10-06 12:59 ` Fabio Estevam
2012-10-06 12:59 ` Fabio Estevam
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