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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines
Date: Fri, 2 Nov 2012 23:10:08 +0100	[thread overview]
Message-ID: <201211022310.08939.marex@denx.de> (raw)
In-Reply-To: <50943BB3.5050800@wwwdotorg.org>

Dear Stephen Warren,

> On 11/02/2012 03:28 PM, Marek Vasut wrote:
> > Dear Stephen Warren,
> > 
> >> On 11/02/2012 02:38 PM, Marek Vasut wrote:
> ...
> 
> >>> Dumb question -- might be unrelated. Does the tegra mmc driver do DMA?
> >>> And if so, what happens if you do raw read to unaligned address (aka.
> >>> how come you don't need the bounce buffer)?
> >> 
> >> Yes, it does DMA, I believe. (At least if it doesn't, I have no idea why
> >> the driver is flushing caches!)
> >> 
> >> I guess we only support the use of aligned addresses, so e.g. the
> >> following would work:
> >> 
> >> ext2load mmc 0:1 0x00100000 /file
> >> 
> >> but the following wouldn't:
> >> 
> >> ext2load mmc 0:1 0x00100004 /file
> >> 
> >> which while I suppose it is an artificial restriction, hasn't been an
> >> issue in practice.
> > 
> > Then just enable the bounce buffer and it will work ;-)
> 
> You suggested that last time, and it made no difference then... In fact,
> the config option you mentioned isn't used anywhere in the srouce tree
> except adding bouncebuf.o

Bouncebuf.o ?

> into the build right now; which config option
> do you think I should use?

CONFIG_BOUNCE_BUFFER

It's used on mx28-based boards.

Best regards,
Marek Vasut

  reply	other threads:[~2012-11-02 22:10 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-04-24  7:53 [U-Boot] [PATCH 1/2] part_dos: allocate cacheline aligned buffers Thierry Reding
2012-04-24  7:53 ` [U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines Thierry Reding
2012-04-25 22:54   ` Mike Frysinger
2012-04-26  6:18     ` Thierry Reding
2012-04-26 10:16       ` Simon Glass
2012-04-26 10:34         ` Thierry Reding
2012-04-27  5:29           ` Mike Frysinger
2012-04-27  5:50             ` Simon Glass
2012-11-02 20:22             ` Stephen Warren
2012-11-02 20:25               ` Simon Glass
2012-11-02 20:38                 ` Marek Vasut
2012-11-02 20:58                   ` Stephen Warren
2012-11-02 21:28                     ` Marek Vasut
2012-11-02 21:31                       ` Stephen Warren
2012-11-02 22:10                         ` Marek Vasut [this message]
2012-11-05 19:50                           ` Stephen Warren
2012-11-05 22:59                             ` Marek Vasut
2012-11-05 23:07                             ` Simon Glass
2012-11-02 20:55                 ` Stephen Warren
2012-04-24 18:31 ` [U-Boot] [PATCH 1/2] part_dos: allocate cacheline aligned buffers Simon Glass
2012-04-24 18:45   ` Thierry Reding

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