* [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write
[not found] <cover.1351876757.git.vipin.kumar@st.com>
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 02/19] mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar
` (16 more replies)
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
` (4 subsequent siblings)
5 siblings, 17 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
SMI controller reports an error when the code tries to write on the flash area
with Write Enable command not issued or the bank has come out of the write mode.
This error is reported even with a fresh write once the ERF1 or ERF2 is set.
Clear these flags while initiating a fresh write
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/mtd/st_smi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 7507e5d..fad4420 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -392,6 +392,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
return -1;
}
+ writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
+
if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
return -EBUSY;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC
[not found] <cover.1351876757.git.vipin.kumar@st.com>
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 2/7] spear1310: Add support for spear1310 SoC Vipin Kumar
` (5 more replies)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (3 subsequent siblings)
5 siblings, 6 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
spear1340 is a CortexA9 dual core SoC which supports multiple peripherals like
GMII, USBH etc. More information can be found at
http://www.st.com/internet/mcu/product/251211.jsp
This patch adds support for spear1340 SoC. It also adds support for pinum for
spear1340. The APIs implemented for this purpose are
* _void spear1340_configure_pin(u32 plgpio, u32 mode)_
* _int spear1340_plgpio_get(u32 plgpio)_
* _void spear1340_plgpio_set(u32 plgpio, u32 val)_
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/armv7/spear13xx/Makefile | 50 +++
arch/arm/cpu/armv7/spear13xx/reset.c | 47 +++
arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c | 439 +++++++++++++++++++++
arch/arm/cpu/armv7/spear13xx/spear1340.c | 270 +++++++++++++
arch/arm/cpu/armv7/spear13xx/spear13xx.c | 32 ++
arch/arm/include/asm/arch-spear13xx/generic.h | 33 ++
arch/arm/include/asm/arch-spear13xx/gpio.h | 42 ++
arch/arm/include/asm/arch-spear13xx/hardware.h | 31 ++
arch/arm/include/asm/arch-spear13xx/misc.h | 31 ++
arch/arm/include/asm/arch-spear13xx/mmc.h | 29 ++
arch/arm/include/asm/arch-spear13xx/pinmux.h | 104 +++++
arch/arm/include/asm/arch-spear13xx/spear1340.h | 159 ++++++++
.../include/asm/arch-spear13xx/spear1340_misc.h | 331 ++++++++++++++++
arch/arm/include/asm/arch-spear13xx/spear13xx.h | 46 +++
drivers/usb/host/ehci-spear.c | 2 +
include/linux/bitops.h | 12 +
16 files changed, 1658 insertions(+)
create mode 100644 arch/arm/cpu/armv7/spear13xx/Makefile
create mode 100644 arch/arm/cpu/armv7/spear13xx/reset.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spear13xx.c
create mode 100644 arch/arm/include/asm/arch-spear13xx/generic.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/misc.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/mmc.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/pinmux.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/spear13xx.h
diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
new file mode 100644
index 0000000..214b89b
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
+COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o
+COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/spear13xx/reset.c b/arch/arm/cpu/armv7/spear13xx/reset.c
new file mode 100644
index 0000000..09fbfa9
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/reset.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/misc.h>
+
+void reset_cpu(ulong ignored)
+{
+ struct misc_regs *misc_regs_p =
+ (struct misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ printf("System is going to reboot ...\n");
+
+ /*
+ * This 1 second delay will allow the above message
+ * to be printed before reset
+ */
+ udelay((1000 * 1000));
+
+ writel(0x01, &misc_regs_p->sys_sw_res);
+
+ /* system will restart */
+ while (1)
+ ;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c b/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c
new file mode 100644
index 0000000..1c92beb
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/* Pin multiplexing for fsmc nand 16 bit device */
+static void enable_nand16bit_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ KBD_ROW_COL_MASK,
+ 0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1,
+ FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
+ FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK);
+}
+
+/* Pin multiplexing for fsmc nand 8 bit device */
+static void enable_nand8bit_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8,
+ FSMC_8BIT_REG7_MASK,
+ FSMC_8BIT_REG7_MASK);
+}
+
+/* Pin multiplexing for fsmc nand device */
+static void enable_nand_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_NAND_8BIT:
+ enable_nand8bit_pins();
+ break;
+ case PMX_NAND_16BIT:
+ enable_nand16bit_pins();
+ }
+}
+
+/* Pin multiplexing for smi device */
+static void enable_smi_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ SMI_REG2_MASK,
+ SMI_REG2_MASK);
+}
+
+/* Pin multiplexing for ssp0 device */
+static void enable_ssp0cs0_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ SSP0_REG2_MASK,
+ SSP0_REG2_MASK);
+}
+
+/* Pin multiplexing for ssp0 chip select 1 */
+static void enable_ssp0cs1_pins(void)
+{
+ enable_ssp0cs0_pins();
+
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ SSP0_CS1_MASK,
+ SSP0_CS1_MASK);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1,
+ PWM0_AND_SSP0_CS1_REG0_MASK,
+ PWM0_AND_SSP0_CS1_REG0_MASK);
+}
+
+/* Pin multiplexing for ssp0 chip select 2 */
+static void enable_ssp0cs2_pins(void)
+{
+ enable_ssp0cs0_pins();
+
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ SSP0_CS2_MASK,
+ SSP0_CS2_MASK);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ TS_AND_SSP0_CS2_REG2_MASK,
+ TS_AND_SSP0_CS2_REG2_MASK);
+}
+
+/* Pin multiplexing for ssp0 chip select 3 */
+static void enable_ssp0cs3_pins(void)
+{
+ enable_ssp0cs0_pins();
+
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5,
+ SSP0_CS3_REG4_MASK,
+ SSP0_CS3_REG4_MASK);
+}
+
+static void enable_ssp0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SSP_CS0:
+ enable_ssp0cs0_pins();
+ break;
+ case PMX_SSP_CS1:
+ enable_ssp0cs1_pins();
+ break;
+ case PMX_SSP_CS2:
+ enable_ssp0cs2_pins();
+ break;
+ case PMX_SSP_CS3:
+ enable_ssp0cs3_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for uart0 device */
+static void enable_uart0simple_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ UART0_REG2_MASK,
+ UART0_REG2_MASK);
+}
+
+/* Pin multiplexing for uart0 enhanced (modem) device */
+static void enable_uart0_enh_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ GPT_MASK,
+ 0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1,
+ UART0_ENH_AND_GPT_REG0_MASK,
+ UART0_ENH_AND_GPT_REG0_MASK);
+}
+
+static void enable_uart0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_UART_SIMPLE:
+ enable_uart0simple_pins();
+ break;
+ case PMX_UART_MODEM:
+ enable_uart0_enh_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for uart1 device */
+static void enable_uart1_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ UART1_REG2_MASK,
+ UART1_REG2_MASK);
+}
+
+/* Pin multiplexing for fsmc-prallel nor device */
+static void enable_fsmcpnor_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ MCIF_MASK,
+ 0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7,
+ FSMC_PNOR_AND_MCIF_REG6_MASK,
+ FSMC_PNOR_AND_MCIF_REG6_MASK);
+}
+
+/*
+ * Pin multiplexing for ethernet device
+ * Ethernet on spear1340 can be configured as either of the below
+ * - GMII
+ * - RGMII
+ * - RMII
+ * - SGMII
+ */
+static void enable_miicommon_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_4,
+ GMAC_REG3_MASK,
+ GMAC_REG3_MASK);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5,
+ GMAC_REG4_MASK,
+ GMAC_REG4_MASK);
+}
+
+static void enable_gmii_pins(void)
+{
+ enable_miicommon_pins();
+
+ pinmux_maskval(SPEAR1340_GMAC_CLK_CFG,
+ GMAC_PHY_IF_SEL_MASK,
+ GMAC_PHY_IF_GMII_VAL);
+}
+
+static void enable_rgmii_pins(void)
+{
+ enable_miicommon_pins();
+
+ pinmux_maskval(SPEAR1340_GMAC_CLK_CFG,
+ GMAC_PHY_IF_SEL_MASK,
+ GMAC_PHY_IF_RGMII_VAL);
+}
+
+static void enable_rmii_pins(void)
+{
+ enable_miicommon_pins();
+
+ pinmux_maskval(SPEAR1340_GMAC_CLK_CFG,
+ GMAC_PHY_IF_SEL_MASK,
+ GMAC_PHY_IF_RMII_VAL);
+}
+
+static void enable_sgmii_pins(void)
+{
+ enable_miicommon_pins();
+
+ pinmux_maskval(SPEAR1340_GMAC_CLK_CFG,
+ GMAC_PHY_IF_SEL_MASK,
+ GMAC_PHY_IF_SGMII_VAL);
+}
+
+static void enable_eth0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_ETH_GMII:
+ enable_gmii_pins();
+ break;
+ case PMX_ETH_RGMII:
+ enable_rgmii_pins();
+ break;
+ case PMX_ETH_RMII:
+ enable_rmii_pins();
+ break;
+ case PMX_ETH_SGMII:
+ enable_sgmii_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for i2c0 device */
+static void enable_i2c0_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5,
+ I2C0_REG4_MASK,
+ I2C0_REG4_MASK);
+}
+
+/* Pin multiplexing for i2c1 device */
+static void enable_i2c1_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1,
+ I2C1_REG0_MASK,
+ I2C1_REG0_MASK);
+}
+
+/* Pin multiplexing for sdmmc device */
+static void enable_sdmmc_pins(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1,
+ MCIF_MASK,
+ MCIF_MASK);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7,
+ FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK,
+ FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8,
+ MCIF_REG7_MASK,
+ MCIF_REG7_MASK);
+ pinmux_maskval(SPEAR1340_PERIP_CFG,
+ MCIF_SEL_MASK,
+ MCIF_SEL_SD);
+}
+
+/**
+ * spear1340_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear1340_pins_default(void)
+{
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1,
+ PADS_AS_GPIO_REG0_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_2,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_4,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_6,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7,
+ PADS_AS_GPIO_REGS_MASK,
+ 0x0);
+ pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8,
+ PADS_AS_GPIO_REG7_MASK,
+ 0x0);
+}
+
+/**
+ * spear1340_enable_pins - enable pins for peripherals on spear1340 devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear1340_enable_pins(u32 ip, u32 mode)
+{
+ if (PMX_SDMMC == ip)
+ enable_sdmmc_pins();
+ else if (PMX_SMI == ip)
+ enable_smi_pins();
+ else if (PMX_I2C0 == ip)
+ enable_i2c0_pins();
+ else if (PMX_I2C1 == ip)
+ enable_i2c1_pins();
+ else if (PMX_UART1 == ip)
+ enable_uart1_pins();
+ else if (PMX_FSMCPNOR == ip)
+ enable_fsmcpnor_pins();
+ else if (PMX_FSMCNAND == ip)
+ enable_nand_pins(mode);
+ else if (PMX_UART0 == ip)
+ enable_uart0_pins(mode);
+ else if (PMX_ETH0 == ip)
+ enable_eth0_pins(mode);
+ else if (PMX_SSP0 == ip)
+ enable_ssp0_pins(mode);
+}
+
+static void configure_gpio(u32 plgpio)
+{
+ if (plgpio > SPEAR1340_MAX_PLGPIOS)
+ return;
+
+ /* Set the pin to GPIO IN mode */
+ pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_EN0);
+
+ /* Put the pin in gpio state */
+ if (plgpio < 127)
+ pinmux_clear_bit(plgpio + 1, SPEAR1340_PAD_FUNCTION_EN_1);
+ else
+ pinmux_clear_bit(plgpio + 1, SPEAR1340_PAD_FUNCTION_EN_5);
+}
+
+static void configure_pullup(u32 plgpio)
+{
+ if (plgpio > SPEAR1340_MAX_PLGPIOS)
+ return;
+
+ /* Deactivate pull down */
+ pinmux_set_bit(plgpio, SPEAR1340_PAD_PD_CFG_1);
+
+ /* Activate pull up */
+ pinmux_clear_bit(plgpio, SPEAR1340_PAD_PU_CFG_1);
+}
+
+static void configure_pulldown(u32 plgpio)
+{
+ if (plgpio > SPEAR1340_MAX_PLGPIOS)
+ return;
+
+ /* Deactivate pull up */
+ pinmux_set_bit(plgpio, SPEAR1340_PAD_PU_CFG_1);
+
+ /* Activate pull down */
+ pinmux_clear_bit(plgpio, SPEAR1340_PAD_PD_CFG_1);
+}
+
+/**
+ * spear1340_configure_pin - Configure pin on spear1340 devices
+ * @plgpio: Pin Number (plgpio number)
+ * @mode: Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc
+ */
+void spear1340_configure_pin(u32 plgpio, u32 mode)
+{
+ if (PMX_GPIO == mode)
+ configure_gpio(plgpio);
+ else if (PMX_PULLUP == mode)
+ configure_pullup(plgpio);
+ else if (PMX_PULLDOWN == mode)
+ configure_pulldown(plgpio);
+}
+
+/**
+ * spear1340_plgpio_get - Get the gpio input
+ * @plgpio: Pin Number (plgpio number)
+ */
+int spear1340_plgpio_get(u32 plgpio)
+{
+ if (plgpio > SPEAR1340_MAX_PLGPIOS)
+ return -1;
+
+ /* Set the pin to GPIO IN mode */
+ pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_EN0);
+
+ return pinmux_test_bit(plgpio, SPEAR1340_PLGPIO_IN0);
+}
+
+/**
+ * spear1340_plgpio_set - Set the gpio value
+ * @plgpio: Pin Number (plgpio number)
+ */
+void spear1340_plgpio_set(u32 plgpio, u32 val)
+{
+ if (plgpio > SPEAR1340_MAX_PLGPIOS)
+ return;
+
+ if (val & 0x1)
+ pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_OUT0);
+ else
+ pinmux_clear_bit(plgpio, SPEAR1340_PLGPIO_OUT0);
+
+ /* Set the pin to GPIO OUT mode */
+ pinmux_clear_bit(plgpio, SPEAR1340_PLGPIO_EN0);
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spear1340.c b/arch/arm/cpu/armv7/spear13xx/spear1340.c
new file mode 100644
index 0000000..ca4626e
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spear1340.c
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/misc.h>
+
+int arch_cpu_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip1_clk_enb, perip2_clk_enb;
+ u32 perip_clk_cfg;
+#if defined(CONFIG_SDHCI)
+ u32 perip_cfg;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+ u32 fsmc_cfg;
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 gmac_clk_cfg;
+#endif
+
+ perip1_clk_enb = readl(&misc_p->perip1_clk_enb);
+ perip2_clk_enb = readl(&misc_p->perip2_clk_enb);
+
+#if defined(CONFIG_PL011_SERIAL)
+ /* select USB PLL 48 MHz as the src clock */
+ perip_clk_cfg = readl(&misc_p->perip_clk_cfg);
+ perip_clk_cfg &= ~SPEAR1340_UARTCLKMSK;
+ perip_clk_cfg |= SPEAR1340_UART48M;
+ writel(perip_clk_cfg, &misc_p->perip_clk_cfg);
+
+ perip1_clk_enb |= SPEAR1340_UART_CLKEN;
+#endif
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ gmac_clk_cfg = readl(&misc_p->gmac_clk_cfg);
+ gmac_clk_cfg &= ~SPEAR1340_CLKSEL_MSK;
+ gmac_clk_cfg |= SPEAR1340_CLKSEL_PLL2;
+ writel(gmac_clk_cfg, &misc_p->gmac_clk_cfg);
+
+ perip1_clk_enb |= SPEAR1340_GETH_CLKEN;
+#endif
+
+#if defined(CONFIG_DW_UDC)
+ perip1_clk_enb |= SPEAR1340_UDC_UPD_CLKEN;
+#endif
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+ perip1_clk_enb |= SPEAR1340_UHC1_CLKEN;
+#endif
+
+#if defined(CONFIG_DW_I2C)
+ perip1_clk_enb |= SPEAR1340_I2C_CLKEN;
+#endif
+
+#if defined(CONFIG_ST_SMI)
+ perip1_clk_enb |= SPEAR1340_SMI_CLKEN;
+#endif
+
+#if defined(CONFIG_PL022_SPI)
+ perip1_clk_enb |= SPEAR1340_SSP_CLKEN;
+#endif
+
+#if defined(CONFIG_SDHCI)
+ perip_cfg = readl(&misc_p->perip_cfg);
+ perip_cfg &= ~SPEAR1340_MCIF_MSK;
+ perip_cfg |= SPEAR1340_MCIF_SD;
+ writel(perip_cfg, &misc_p->perip_cfg);
+
+ writel(SPEAR1340_SYNT_X_2 | SPEAR1340_SYNT_Y_21 | SPEAR1340_SYNT_CLKENB,
+ &misc_p->mcif_sd_clk_synt);
+
+ perip1_clk_enb |= SPEAR1340_SD_CLKEN;
+#endif
+
+#if defined(CONFIG_NAND_FSMC)
+ fsmc_cfg = readl(&misc_p->fsmc_cfg);
+ fsmc_cfg &= ~SPEAR1340_DEV_SEL_MSK;
+ fsmc_cfg |= SPEAR1340_DEV_SEL_NAND;
+#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
+ fsmc_cfg |= SPEAR1340_DEV_WIDTH_16;
+#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
+ fsmc_cfg |= SPEAR1340_DEV_WIDTH_8;
+#endif
+ writel(fsmc_cfg, &misc_p->fsmc_cfg);
+
+ perip1_clk_enb |= SPEAR1340_FSMC_CLKEN;
+#endif
+
+ writel(perip1_clk_enb, &misc_p->perip1_clk_enb);
+ writel(perip2_clk_enb, &misc_p->perip2_clk_enb);
+
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("CPU: SPEAr1340\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PL022_SPI)
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ struct spear1340_misc_regs *misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip_cfg;
+
+ perip_cfg = readl(&misc_regs_p->perip_cfg);
+ perip_cfg &= ~SPEAR1340_SSP_CS_EN_MSK;
+ perip_cfg |= cs << SPEAR1340_SSP_CS_EN_SHFT;
+
+ perip_cfg |= SPEAR1340_HS_SSP_SW_CS;
+ perip_cfg |= SPEAR1340_HS_SSP_EN;
+ writel(perip_cfg, &misc_regs_p->perip_cfg);
+
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct spear1340_misc_regs *misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip_cfg;
+
+ perip_cfg = readl(&misc_regs_p->perip_cfg);
+ perip_cfg &= ~SPEAR1340_HS_SSP_SW_CS;
+ writel(perip_cfg, &misc_regs_p->perip_cfg);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct spear1340_misc_regs *misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip_cfg;
+
+ perip_cfg = readl(&misc_regs_p->perip_cfg);
+ perip_cfg |= SPEAR1340_HS_SSP_SW_CS;
+ writel(perip_cfg, &misc_regs_p->perip_cfg);
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+void spear1340_usbh_stop(void)
+{
+ struct spear1340_misc_regs *const misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip1_sw_rst = readl(&misc_regs_p->perip1_sw_rst);
+
+ perip1_sw_rst |= SPEAR1340_UHC1_SWRST;
+ writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst);
+
+ udelay(1000);
+ perip1_sw_rst &= ~SPEAR1340_UHC1_SWRST;
+ writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst);
+}
+#endif
+
+#ifdef CONFIG_DW_OTG_PHYINIT
+void udc_phy_init(void)
+{
+ struct spear1340_misc_regs *const misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 temp;
+ ulong start;
+
+ /* phy por assert */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp |= SPEAR1340_USBPHY_POR;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+ udelay(1);
+
+ /* phy clock disable */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp &= ~SPEAR1340_USBPHY_RST;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+
+ udelay(150);
+
+ /* phy por deassert */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp &= ~SPEAR1340_USBPHY_POR;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+ udelay(1);
+
+ /* phy clock enable */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp |= SPEAR1340_USBPHY_RST;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+
+ start = get_timer(0);
+
+ while (get_timer(start) < CONFIG_SYS_HZ) {
+ if (readl(&misc_regs_p->usbphy_gen_cfg) &
+ SPEAR1340_USB_PLL_LOCK)
+ break;
+
+ /* Try after 10 ms */
+ udelay(10);
+ };
+
+ /* wait for pll to stabilize */
+ udelay(1);
+
+ /* OTG HCLK Disable */
+ temp = readl(&misc_regs_p->perip1_clk_enb);
+ temp &= ~SPEAR1340_UDC_UPD_CLKEN;
+ writel(temp, &misc_regs_p->perip1_clk_enb);
+
+ /* OTG HRESET deassert */
+ temp = readl(&misc_regs_p->perip1_sw_rst);
+ temp &= ~SPEAR1340_UDC_UPD_SWRST;
+ writel(temp, &misc_regs_p->perip1_sw_rst);
+
+ /* OTG HCLK Enable */
+ temp = readl(&misc_regs_p->perip1_clk_enb);
+ temp |= SPEAR1340_UDC_UPD_CLKEN;
+ writel(temp, &misc_regs_p->perip1_clk_enb);
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+ struct spear1340_misc_regs *misc_regs_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ printf("System is going to reboot ...\n");
+
+ /*
+ * This 1 second delay will allow the above message
+ * to be printed before reset
+ */
+ udelay((1000 * 1000));
+
+ writel(0x01, &misc_regs_p->sys_sw_res);
+
+ /* system will restart */
+ while (1)
+ ;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
new file mode 100644
index 0000000..351e8cd
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+#endif
+}
diff --git a/arch/arm/include/asm/arch-spear13xx/generic.h b/arch/arm/include/asm/arch-spear13xx/generic.h
new file mode 100644
index 0000000..7beb1c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/generic.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_GENERIC_H__
+#define __ARCH_ARM_GENERIC_H__
+
+#if defined(CONFIG_SOC_SPEAR1310)
+extern void spear1310_usbh_stop(void);
+#elif defined(CONFIG_SOC_SPEAR1340)
+extern void spear1340_usbh_stop(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/gpio.h b/arch/arm/include/asm/arch-spear13xx/gpio.h
new file mode 100644
index 0000000..59cc88f
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * Copied from arch/arm/include/asm/arch-spear/gpio.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_SPEAR_GPIO_H
+#define __ASM_ARCH_SPEAR_GPIO_H
+
+enum gpio_direction {
+ GPIO_DIRECTION_IN,
+ GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+ u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */
+ u32 gpiodir; /* 0x400 */
+};
+
+#define SPEAR_GPIO_COUNT 8
+#define DATA_REG_ADDR(gpio) (1 << (gpio + 2))
+
+#endif /* __ASM_ARCH_SPEAR_GPIO_H */
diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h
new file mode 100644
index 0000000..b49ef67
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#if defined(CONFIG_SOC_SPEAR1340)
+#include <asm/arch/spear1340.h>
+#endif
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear13xx/misc.h b/arch/arm/include/asm/arch-spear13xx/misc.h
new file mode 100644
index 0000000..5134938
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/misc.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_MISC_H
+#define _ASM_ARCH_MISC_H
+
+#ifdef CONFIG_SOC_SPEAR1340
+#include <asm/arch/spear1340_misc.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/mmc.h b/arch/arm/include/asm/arch-spear13xx/mmc.h
new file mode 100644
index 0000000..5c01a7e
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/mmc.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_MMC_H
+#define _ASM_ARCH_MMC_H
+
+extern int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/pinmux.h b/arch/arm/include/asm/arch-spear13xx/pinmux.h
new file mode 100644
index 0000000..9354f21
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/pinmux.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_PINMUX_H
+#define _ASM_ARCH_PINMUX_H
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+static inline void pinmux_maskval(ulong reg, u32 mask, u32 val)
+{
+ u32 temp = readl((u32 *)reg);
+ temp &= ~mask;
+ temp |= val & mask;
+ writel(temp, (u32 *)reg);
+}
+
+static inline void pinmux_set_bit(int nr, unsigned long addr)
+{
+ __set_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline void pinmux_clear_bit(int nr, unsigned long addr)
+{
+ __clear_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline int pinmux_test_bit(int nr, unsigned long addr)
+{
+ return __test_bit(nr, (volatile unsigned long *)addr);
+}
+
+enum pinmux_ip {
+ PMX_UART0,
+ PMX_UART1,
+ PMX_UART2,
+ PMX_UART3,
+ PMX_UART4,
+ PMX_UART5,
+ PMX_I2C0,
+ PMX_I2C1,
+ PMX_I2C2,
+ PMX_SSP0,
+ PMX_SSP1,
+ PMX_SSP2,
+ PMX_ETH0,
+ PMX_ETH1,
+ PMX_ETH2,
+ PMX_FSMCNAND,
+ PMX_FSMCPNOR,
+ PMX_SDMMC,
+ PMX_EMI,
+ PMX_SMI,
+};
+
+/* UART0 modem modes */
+#define PMX_UART_SIMPLE 1
+#define PMX_UART_MODEM 2
+
+/* SSP modes */
+#define PMX_SSP_CS0 1
+#define PMX_SSP_CS1 2
+#define PMX_SSP_CS2 3
+#define PMX_SSP_CS3 4
+
+/* ETH modes */
+#define PMX_ETH_GMII 1
+#define PMX_ETH_MII 2
+#define PMX_ETH_RGMII 3
+#define PMX_ETH_RMII 4
+#define PMX_ETH_SGMII 5
+#define PMX_ETH_SMII 6
+
+/* NAND modes */
+#define PMX_NAND_8BIT 1
+#define PMX_NAND_16BIT 2
+
+/* PLGPIO modes */
+#define PMX_GPIO 1
+#define PMX_PULLUP 2
+#define PMX_PULLDOWN 3
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340.h b/arch/arm/include/asm/arch-spear13xx/spear1340.h
new file mode 100644
index 0000000..c595607
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/spear1340.h
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR1340_PINMUX_H
+#define _ASM_ARCH_SPEAR1340_PINMUX_H
+
+#include <asm/arch/spear13xx.h>
+
+/* Macros to select an interface within a peripheral pins */
+#define SPEAR1340_PERIP_CFG (CONFIG_SYS_MISC_BASE + 0x42C)
+ /* PERIP_CFG register masks */
+ #define MCIF_SEL_SD 1
+ #define MCIF_SEL_CF 2
+ #define MCIF_SEL_XD 3
+ #define MCIF_SEL_MASK 3
+ #define MCIF_SEL_SHIFT 0
+
+#define SPEAR1340_GMAC_CLK_CFG (CONFIG_SYS_MISC_BASE + 0x248)
+ #define GMAC_PHY_IF_GMII_VAL (0 << 3)
+ #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
+ #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
+ #define GMAC_PHY_IF_RMII_VAL (4 << 3)
+ #define GMAC_PHY_IF_SEL_MASK (7 << 3)
+
+/*
+ * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
+ * registers with 32 bits each for handling gpio pads, register 8 has only 26
+ * relevant bits.
+ */
+#define SPEAR1340_PAD_FUNCTION_EN_1 (CONFIG_SYS_MISC_BASE + 0x668)
+#define SPEAR1340_PAD_FUNCTION_EN_2 (CONFIG_SYS_MISC_BASE + 0x66C)
+#define SPEAR1340_PAD_FUNCTION_EN_3 (CONFIG_SYS_MISC_BASE + 0x670)
+#define SPEAR1340_PAD_FUNCTION_EN_4 (CONFIG_SYS_MISC_BASE + 0x674)
+#define SPEAR1340_PAD_FUNCTION_EN_5 (CONFIG_SYS_MISC_BASE + 0x690)
+#define SPEAR1340_PAD_FUNCTION_EN_6 (CONFIG_SYS_MISC_BASE + 0x694)
+#define SPEAR1340_PAD_FUNCTION_EN_7 (CONFIG_SYS_MISC_BASE + 0x698)
+#define SPEAR1340_PAD_FUNCTION_EN_8 (CONFIG_SYS_MISC_BASE + 0x69C)
+ /* macro's for making pads as gpio's */
+ #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
+ #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
+ #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
+ /* macro's for making pads as peripherals */
+ #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
+ #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
+ #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
+ #define I2C1_REG0_MASK 0x01080000
+ #define SPDIF_IN_REG0_MASK 0x00100000
+ #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
+ #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
+ #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
+ #define VIP_AND_CAM3_REG0_MASK 0xFC200000
+ #define VIP_AND_CAM3_REG1_MASK 0x0000000F
+ #define VIP_REG1_MASK 0x00001EF0
+ #define VIP_AND_CAM2_REG1_MASK 0x007FE100
+ #define VIP_AND_CAM1_REG1_MASK 0xFF800000
+ #define VIP_AND_CAM1_REG2_MASK 0x00000003
+ #define VIP_AND_CAM0_REG2_MASK 0x00001FFC
+ #define SMI_REG2_MASK 0x0021E000
+ #define SSP0_REG2_MASK 0x001E0000
+ #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
+ #define UART0_REG2_MASK 0x01800000
+ #define UART1_REG2_MASK 0x06000000
+ #define I2S_IN_REG2_MASK 0xF8000000
+ #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
+ #define I2S_OUT_REG3_MASK 0x000001EF
+ #define I2S_IN_REG3_MASK 0x00000010
+ #define GMAC_REG3_MASK 0xFFFFFE00
+ #define GMAC_REG4_MASK 0x0000001F
+ #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
+ #define SSP0_CS3_REG4_MASK 0x00000020
+ #define I2C0_REG4_MASK 0x000000C0
+ #define CEC0_REG4_MASK 0x00000100
+ #define CEC1_REG4_MASK 0x00000200
+ #define SPDIF_OUT_REG4_MASK 0x00000400
+ #define CLCD_REG4_MASK 0x7FFFF800
+ #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
+ #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
+ #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
+ #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
+ #define MCIF_REG6_MASK 0xF8C00000
+ #define MCIF_REG7_MASK 0x000043FF
+ #define FSMC_8BIT_REG7_MASK 0x07FFBC00
+
+
+
+/* - If peripherals, then primary OR alternate peripheral */
+#define SPEAR1340_PAD_SHARED_IP_EN_1 (CONFIG_SYS_MISC_BASE + 0x6A0)
+#define SPEAR1340_PAD_SHARED_IP_EN_2 (CONFIG_SYS_MISC_BASE + 0x6A4)
+ /*
+ * Macro's for second level of pmx
+ * - pads as primary OR alternate peripheral
+ */
+ /* Write 0 to enable FSMC_16_BIT */
+ #define KBD_ROW_COL_MASK (1 << 0)
+ /* Write 0 to enable UART0_ENH */
+ #define GPT_MASK (1 << 1)
+ /* Write 0 to enable PWM1 */
+ #define KBD_COL5_MASK (1 << 2)
+ /* Write 0 to enable PWM2 */
+ #define GPT0_TMR0_CPT_MASK (1 << 3)
+ /* Write 0 to enable PWM3 */
+ #define GPT0_TMR1_CLK_MASK (1 << 4)
+ /* Write 0 to enable PWM0 */
+ #define SSP0_CS1_MASK (1 << 5)
+ /* Write 0 to enable VIP */
+ #define CAM3_MASK (1 << 6)
+ /* Write 0 to enable VIP */
+ #define CAM2_MASK (1 << 7)
+ /* Write 0 to enable VIP */
+ #define CAM1_MASK (1 << 8)
+ /* Write 0 to enable VIP */
+ #define CAM0_MASK (1 << 9)
+ /* Write 0 to enable TS */
+ #define SSP0_CS2_MASK (1 << 10)
+ /* Write 0 to enable FSMC PNOR */
+ #define MCIF_MASK (1 << 11)
+ /* Write 0 to enable CLCD */
+ #define ARM_TRACE_MASK (1 << 12)
+ /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
+ #define MIPHY_DBG_MASK (1 << 13)
+
+/* Pull DOWN and Pull UP */
+#define SPEAR1340_PAD_PU_CFG_1 (CONFIG_SYS_MISC_BASE + 0x600)
+#define SPEAR1340_PAD_PD_CFG_1 (CONFIG_SYS_MISC_BASE + 0x620)
+
+/* Macro's to configure plgpios as Pull UP, Pull Down */
+#define CONFIG_SYS_PLGPIO_BASE 0xE2800000
+ #define SPEAR1340_PLGPIO_EN0 (CONFIG_SYS_PLGPIO_BASE + 0x00)
+ #define SPEAR1340_PLGPIO_IN0 (CONFIG_SYS_PLGPIO_BASE + 0x20)
+ #define SPEAR1340_PLGPIO_OUT0 (CONFIG_SYS_PLGPIO_BASE + 0x40)
+ #define SPEAR1340_MAX_PLGPIOS 249
+
+extern void spear1340_pins_default(void);
+extern void spear1340_enable_pins(u32 ip, u32 mode);
+extern void spear1340_configure_pin(u32 plgpio, u32 mode);
+extern void spear1340_plgpio_set(u32 plgpio, u32 val);
+extern int spear1340_plgpio_get(u32 plgpio);
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
new file mode 100644
index 0000000..090de1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
@@ -0,0 +1,331 @@
+/*
+ * (C) Copyright 2012
+ * Vipul Kumar Samar, ST Microelectronics, vipulkumar.samar at st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPEAR1340_MISC_H
+#define __SPEAR1340_MISC_H
+
+struct spear1340_misc_regs {
+ u32 soc_cfg; /* 0x000 */
+ u32 bootstrap_cfg; /* 0x004 */
+ u8 reserved_1[0x100 - 0x8];
+ u32 pcm_cfg; /* 0x100 */
+ u32 pcm_wkup_cfg; /* 0x104 */
+ u32 switch_ctr; /* 0x108 */
+ u8 reserved_2[0x200 - 0x10c];
+ u32 sys_clk_ctrl; /* 0x200 */
+ u32 sys_sw_res; /* 0x204 */
+ u32 sys_clk_plltimer; /* 0x208 */
+ u32 sys_clk_oscitimer; /* 0x20c */
+ u32 pll_cfg; /* 0x210 */
+ u32 pll1_ctr; /* 0x214 */
+ u32 pll1_frq; /* 0x218 */
+ u32 pll1_mod; /* 0x21c */
+ u32 pll2_ctr; /* 0x220 */
+ u32 pll2_frq; /* 0x224 */
+ u32 pll2_mod; /* 0x228 */
+ u32 pll3_ctr; /* 0x22c */
+ u32 pll3_frq; /* 0x230 */
+ u32 pll3_mod; /* 0x234 */
+ u32 pll4_ctr; /* 0x238 */
+ u32 pll4_frq; /* 0x23C */
+ u32 pll4_mod; /* 0x240 */
+ u32 perip_clk_cfg; /* 0x244 */
+ u32 gmac_clk_cfg; /* 0x248 */
+ u32 i2s_clk_cfg; /* 0x24c */
+ u32 c3_clk_synt; /* 0x250 */
+ u32 uart1_clk_synt; /* 0x254 */
+ u32 uart2_clk_synt; /* 0x258 */
+ u32 gmac_clk_synt; /* 0x25c */
+ u32 mcif_sd_clk_synt; /* 0x260 */
+ u32 mcif_cfxd_clk_synt; /* 0x264 */
+ u32 cec1_clk_synt; /* 0x268 */
+ u32 cec2_clk_synt; /* 0x26c */
+ u32 adc_clk_synt; /* 0x270 */
+ u32 amba_clk_sscg; /* 0x274 */
+ u32 amba_clk_sscg_mod; /* 0x278 */
+ u32 clcd_clk_sscg; /* 0x27c */
+ u32 clcd_clk_sscg_mod; /* 0x280 */
+ u32 cpu_clk_sscg; /* 0x284 */
+ u32 cpu_clk_sscg_mod; /* 0x288 */
+ u32 gen_clk_sscg0; /* 0x28C */
+ u32 gen_clk_sscg0_mod; /* 0x290 */
+ u32 gen_clk_sscg1; /* 0x294 */
+ u32 gen_clk_sscg1_mod; /* 0x298 */
+ u32 gen_clk_sscg2; /* 0x29c */
+ u8 reserved_3[0x300 - 0x2A0];
+ u32 gen_clk_sscg2_mod; /* 0x300 */
+ u32 gen_clk_sscg3; /* 0x304 */
+ u32 gen_clk_sscg3_mod; /* 0x308 */
+ u32 perip1_clk_enb; /* 0x30c */
+ u32 perip2_clk_enb; /* 0x310 */
+ u32 perip3_clk_enb; /* 0x314 */
+ u32 perip1_sw_rst; /* 0x318 */
+ u32 perip2_sw_rst; /* 0x31c */
+ u32 perip3_sw_rst; /* 0x320 */
+ u8 reserved_4[0x400 - 0x324];
+ u32 dmac_hs_sel; /* 0x400 */
+ u32 dmac_sel; /* 0x404 */
+ u32 dmac_flow_sel; /* 0x408 */
+ u32 dmac_dir_sel; /* 0x40c */
+ u32 endianess_cfg; /* 0x410 */
+ u32 usbphy_gen_cfg; /* 0x414 */
+ u32 usbphy_p1_cfg; /* 0x418 */
+ u32 usbphy_p2_cfg; /* 0x41c */
+ u32 usbphy_p3_cfg; /* 0x420 */
+ u32 pcie_sata_cfg; /* 0x424 */
+ u32 pcie_miphy_cfg; /* 0x428 */
+ u32 perip_cfg; /* 0x42c */
+ u32 fsmc_cfg; /* 0x430 */
+ u32 mpmc_cfg; /* 0x434 */
+ u32 mpmc_ctr_sts; /* 0x438 */
+ u32 sata_core_id; /* 0x43c */
+ u32 mali_gen_purpose_1; /* 0x440 */
+ u32 mali_gen_purpose_2; /* 0x444 */
+ u8 reserved_5[0x500 - 0x448];
+ u32 prc1_lock_ctr; /* 0x500 */
+ u32 prc2_lock_ctr; /* 0x504 */
+ u32 prc1_irq_ctr; /* 0x508 */
+ u8 reserved_6[0x51c - 0x50c];
+ u32 prc2_irq_ctr; /* 0x51c */
+ u8 reserved_7[0x600 - 0x520];
+ u32 pad_pu_cfg_1; /* 0x600 */
+ u32 pad_pu_cfg_2; /* 0x604 */
+ u32 pad_pu_cfg_3; /* 0x608 */
+ u32 pad_pu_cfg_4; /* 0x60c */
+ u32 pad_pu_cfg_5; /* 0x610 */
+ u32 pad_pu_cfg_6; /* 0x614 */
+ u32 pad_pu_cfg_7; /* 0x618 */
+ u32 pad_pu_cfg_8; /* 0x61c */
+ u32 pad_pd_cfg_1; /* 0x620 */
+ u32 pad_pd_cfg_2; /* 0x624 */
+ u32 pad_pd_cfg_3; /* 0x628 */
+ u32 pad_pd_cfg_4; /* 0x62c */
+ u32 pad_pd_cfg_5; /* 0x630 */
+ u32 pad_pd_cfg_6; /* 0x634 */
+ u32 pad_pd_cfg_7; /* 0x638 */
+ u32 pad_pd_cfg_8; /* 0x63c */
+ u8 reserved_8[0x648 - 0x640];
+ u32 pad_drv_cfg_1; /* 0x648 */
+ u32 pad_drv_cfg_2; /* 0x64c */
+ u32 pad_drv_cfg_3; /* 0x650 */
+ u32 pad_drv_cfg_4; /* 0x654 */
+ u32 pad_drv_cfg_5; /* 0x658 */
+ u32 pad_slew_cfg_1; /* 0x65c */
+ u32 pad_slew_cfg_2; /* 0x660 */
+ u32 pad_slew_cfg_3; /* 0x664 */
+ u32 pad_function_en_1; /* 0x668 */
+ u32 pad_function_en_2; /* 0x66c */
+ u32 pad_function_en_3; /* 0x670 */
+ u32 pad_function_en_4; /* 0x674 */
+ u8 reserved_9[0x690 - 0x678];
+ u32 pad_function_en_5; /* 0x690 */
+ u32 pad_function_en_6; /* 0x694 */
+ u32 pad_function_en_7; /* 0x698 */
+ u32 pad_function_en_8; /* 0x69c */
+ u32 pad_shared_ip_en_1; /* 0x6A0 */
+ u32 pad_shared_ip_en_2; /* 0x6A4 */
+ u32 ddr_pad_cfg; /* 0x6A8 */
+ u8 reserved_10[0x700 - 0x6Ac];
+ u32 compensation_1v8_3v3_1_cfg; /* 0x700 */
+ u32 compensation_1v8_3v3_2_cfg; /* 0x704 */
+ u32 compensation_3v3_1_cfg; /* 0x708 */
+ u32 compensation_3v3_2_cfg; /* 0x70c */
+ u32 compensation_ddr_cfg; /* 0x710 */
+ u32 compensation_2v5_3v3_1_cfg; /* 0x714 */
+ u8 reserved_11[0x800 - 0x718];
+ u32 otp_prog_ctr; /* 0x800 */
+ u32 otp_wdata1_1; /* 0x804 */
+ u32 otp_wdata1_2; /* 0x808 */
+ u32 otp_wdata1_3; /* 0x80c */
+ u32 otp_wdata1_4; /* 0x810 */
+ u32 otp_wdata1_5; /* 0x814 */
+ u32 otp_wdata1_6; /* 0x818 */
+ u32 otp_wdata1_7; /* 0x81c */
+ u32 otp_wdata1_8; /* 0x820 */
+ u32 otp_wdata2_1; /* 0x824 */
+ u32 otp_wdata2_2; /* 0x828 */
+ u32 otp_wdata2_3; /* 0x82c */
+ u32 otp_wdata2_4; /* 0x830 */
+ u32 otp_wdata2_5; /* 0x834 */
+ u32 otp_wdata2_6; /* 0x838 */
+ u32 otp_wdata2_7; /* 0x83c */
+ u32 otp_wdata2_8; /* 0x840 */
+ u32 otp_mask_1; /* 0x844 */
+ u32 otp_mask_2; /* 0x848 */
+ u32 otp_mask_3; /* 0x84c */
+ u32 otp_mask_4; /* 0x850 */
+ u32 otp_mask_5; /* 0x854 */
+ u32 otp_mask_6; /* 0x858 */
+ u32 otp_mask_7; /* 0x85c */
+ u32 otp_mask_8; /* 0x860 */
+ u32 otp_rdata1_1; /* 0x864 */
+ u32 otp_rdata1_2; /* 0x868 */
+ u32 otp_rdata1_3; /* 0x86c */
+ u32 otp_rdata1_4; /* 0x870 */
+ u32 otp_rdata1_5; /* 0x874 */
+ u32 otp_rdata1_6; /* 0x878 */
+ u32 otp_rdata1_7; /* 0x87c */
+ u32 otp_rdata1_8; /* 0x880 */
+ u32 otp_rdata2_1; /* 0x884 */
+ u32 otp_rdata2_2; /* 0x888 */
+ u32 otp_rdata2_3; /* 0x88c */
+ u32 otp_rdata2_4; /* 0x890 */
+ u32 otp_rdata2_5; /* 0x894 */
+ u32 otp_rdata2_6; /* 0x898 */
+ u32 otp_rdata2_7; /* 0x89c */
+ u32 otp_rdata2_8; /* 0x8a0 */
+ u32 otp_rdatam_1; /* 0x8a4 */
+ u32 otp_rdatam_2; /* 0x8a8 */
+ u32 otp_rdatam_3; /* 0x8ac */
+ u32 otp_rdatam_4; /* 0x8b0 */
+ u32 otp_rdatam_5; /* 0x8b4 */
+ u32 otp_rdatam_6; /* 0x8b8 */
+ u32 otp_rdatam_7; /* 0x8bc */
+ u32 otp_rdatam_8; /* 0x8c0 */
+ u32 thsens_cfg; /* 0x8c4 */
+ u8 reserved_12[0x900 - 0x8c8];
+ u32 a9sm_clusterid; /* 0x900 */
+ u32 a9sm_status; /* 0x904 */
+ u32 a9sm_debug; /* 0x908 */
+ u32 a9sm_filter; /* 0x90c */
+ u32 a9sm_parity_cfg; /* 0x910 */
+ u32 a9sm_parity_err; /* 0x914 */
+ u8 reserved_13[0xa00 - 0x918];
+ u32 die_id_1; /* 0xa00 */
+ u32 die_id_2; /* 0xa04 */
+ u32 die_id_3; /* 0xa08 */
+ u32 die_id_4; /* 0xa0c */
+ u8 reserved_14[0xc00 - 0xa10];
+ u32 axi_cache_user_ctrl_0; /* 0xc00 */
+ u32 axi_cache_user_ctrl_1; /* 0xc04 */
+ u32 axi_cache_user_ctrl_2; /* 0xc08 */
+ u32 axi_cache_user_ctrl_3; /* 0xc0c */
+ u32 ahb_cache_user_ctrl_0; /* 0xc10 */
+ u32 ahb_cache_user_ctrl_1; /* 0xc14 */
+ u32 ahb_cache_user_ctrl_2; /* 0xc18 */
+ u32 ahb_cache_user_ctrl_3; /* 0xc1c */
+ u32 ahb_cache_user_ctrl_4; /* 0xc20 */
+ u32 ahb_cache_user_ctrl_5; /* 0xc24 */
+ u32 ahb_cache_user_ctrl_6; /* 0xc28 */
+ u32 ahb_cache_user_ctrl_7; /* 0xc2c */
+ u8 reserved_15[0x1000 - 0xc30];
+ u32 miphy_test; /* 0x1000 */
+ u32 usb_test; /* 0x1004 */
+ u32 misc_cfg; /* 0x1008 */
+};
+
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1340_C3_CLKEN 0x20000000
+#define SPEAR1340_GPT1_CLKEN 0x00200000
+#define SPEAR1340_I2C_CLKEN 0x00040000
+#define SPEAR1340_SSP_CLKEN 0x00020000
+#define SPEAR1340_UART_CLKEN 0x00008000
+#define SPEAR1340_UDC_UPD_CLKEN 0x00000800
+#define SPEAR1340_UHC1_CLKEN 0x00000200
+#define SPEAR1340_GETH_CLKEN 0x00000100
+#define SPEAR1340_SD_CLKEN 0x00000040
+#define SPEAR1340_SMI_CLKEN 0x00000020
+#define SPEAR1340_FSMC_CLKEN 0x00000010
+
+/* perip1_sw_rst */
+#define SPEAR1340_C3_SWRST 0x20000000
+#define SPEAR1340_UDC_UPD_SWRST 0x00000800
+#define SPEAR1340_UHC1_SWRST 0x00000200
+
+#define SPEAR1340_SYS_MODE_MASK 0x00000007
+#define SPEAR1340_SYS_MODE_DOZE 0x00000001
+#define SPEAR1340_SYS_MODE_SLOW 0x00000002
+#define SPEAR1340_SYS_MODE_NORMAL 0x00000004
+#define SPEAR1340_PLL_TIMEOUT_ENB 0x00000008
+#define SPEAR1340_XTAL_TIMEOUT_ENB 0x00000010
+#define SPEAR1340_SYS_STATE_MASK 0x000F0000
+#define SPEAR1340_SYS_STATE_NORMAL 0x000F0000
+
+/* sys_clk_*timer definitions */
+#define SPEAR1340_PLL_TIM 0x000007f8
+#define SPEAR1340_OSCI_TIM 0x000007f8
+
+/* pll_freq definitions in MHz */
+#define SPEAR1340_FREQ_1000 0x7D000006
+#define SPEAR1340_FREQ_996 0x53000004
+#define SPEAR1340_FREQ_332 0x53000203
+
+/* pll_ctr definitions */
+#define SPEAR1340_PLLLOCK 0x00000001
+#define SPEAR1340_PLLENABLE 0x00000004
+
+/* perip_clk_cfg definitions */
+#define SPEAR1340_GPTCLKSRC 0x00000100
+#define SPEAR1340_UARTCLKMSK 0x00000030
+#define SPEAR1340_UART48M 0x00000000
+
+/* gmac_clk_cfg definitions */
+#define SPEAR1340_PHYIF_MSK 0x00000038
+#define SPEAR1340_PHYIF_RMII 0x00000020
+#define SPEAR1340_PHYIF_SGMII 0x00000010
+#define SPEAR1340_PHYIF_RGMII 0x00000008
+#define SPEAR1340_PHYIF_GMII 0x00000000
+#define SPEAR1340_GMII_SYNT_ENB 0x00000004
+#define SPEAR1340_CLKSEL_MSK 0x00000003
+#define SPEAR1340_CLKSEL_OSCI3 0x00000002
+#define SPEAR1340_CLKSEL_PLL2 0x00000001
+#define SPEAR1340_CLKSEL_PAD 0x00000000
+
+/* usbphy_gen_cfg definitions */
+#define SPEAR1340_USB_PLL_LOCK 0x01000000
+#define SPEAR1340_USBPHY_RST 0x00008000
+#define SPEAR1340_USBPHY_PRSNT 0x00002000
+#define SPEAR1340_USBPHY_POR 0x00001000
+#define SPEAR1340_COMMON_PWDN 0x00000000
+
+/* perip_cfg definitions */
+#define SPEAR1340_HS_SSP_EN 0x00200000
+#define SPEAR1340_HS_SSP_SW_CS 0x00100000
+#define SPEAR1340_SSP_CS_EN_MSK 0x000C0000
+#define SPEAR1340_SSP_CS_EN_SHFT 18
+#define SPEAR1340_MCIF_MSK 0x00000003
+#define SPEAR1340_MCIF_SD 0x00000001
+
+/* fsmc_cfg definitions */
+#define SPEAR1340_DEV_SEL_NOR 0x00000000
+#define SPEAR1340_DEV_SEL_NAND 0x00000001
+#define SPEAR1340_DEV_SEL_SRAM 0x00000002
+#define SPEAR1340_DEV_SEL_MSK 0x00000003
+#define SPEAR1340_NAND_BANK_0 0x00000000
+#define SPEAR1340_NAND_BANK_1 0x00000004
+#define SPEAR1340_NAND_BANK_2 0x00000008
+#define SPEAR1340_NAND_BANK_3 0x0000000C
+#define SPEAR1340_DEV_WIDTH_8 0x00000000
+#define SPEAR1340_DEV_WIDTH_16 0x00000010
+
+/* synth registers definitions */
+#define SPEAR1340_SYNT_CLKENB 0x80000000
+#define SPEAR1340_SYNT_FINFULL 0x04000000
+#define SPEAR1340_SYNT_X_1 0x00010000
+#define SPEAR1340_SYNT_X_2 0x00020000
+#define SPEAR1340_SYNT_Y_2 0x00000002
+#define SPEAR1340_SYNT_Y_5 0x00000005
+#define SPEAR1340_SYNT_Y_21 0x00000015
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear13xx.h b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
new file mode 100644
index 0000000..a4fca51
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR13XX_H
+#define _ASM_ARCH_SPEAR13XX_H
+
+#define CONFIG_SPEAR_CORTEXBASE 0xEC800000
+#define CONFIG_ARMV7_LTIMER_BASE (CONFIG_SPEAR_CORTEXBASE + 0x600)
+
+#define CONFIG_SYS_C3_BASE 0xE1800000
+#define CONFIG_SYS_USBD_BASE 0xE3800000
+#define CONFIG_SYS_UHC0_EHCI_BASE 0xE4800000
+#define CONFIG_SYS_UHC1_EHCI_BASE 0xE5800000
+#define CONFIG_SYS_SMI_BASE 0xEA000000
+#define CONFIG_SYS_MISC_BASE 0xE0700000
+#define CONFIG_SYS_I2C_BASE 0xE0280000
+#define CONFIG_SYS_ETH_BASE 0xE2000000
+#define CONFIG_SYS_FSMC_BASE 0xB0000000
+#define CONFIG_SYS_MMC_BASE 0xB3000000
+#define CONFIG_SYS_SPI_BASE 0xE0100000
+#define CONFIG_GPIO_BASE 0xE0600000
+
+#define CONFIG_SYS_NAND_CLE (1 << 16)
+#define CONFIG_SYS_NAND_ALE (1 << 17)
+
+#endif /* _ASM_ARCH_SPEAR13XX_H */
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index 71c4ea2..7a57379 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -59,6 +59,8 @@ int ehci_hcd_stop(int index)
spear3xx_usbh_stop();
#elif defined(CONFIG_ARCH_SPEAR6XX)
spear6xx_usbh_stop();
+#elif defined(CONFIG_SOC_SPEAR1340)
+ spear1340_usbh_stop();
#else
#error No spear platforms defined
#endif
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index e724310..984022c 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -115,6 +115,10 @@ static inline unsigned int generic_hweight8(unsigned int w)
# define __set_bit generic_set_bit
#endif
+#ifndef PLATFORM__TEST_BIT
+# define __test_bit generic_test_bit
+#endif
+
#ifndef PLATFORM__CLEAR_BIT
# define __clear_bit generic_clear_bit
#endif
@@ -144,6 +148,14 @@ static inline void generic_set_bit(int nr, volatile unsigned long *addr)
*p |= mask;
}
+static inline int generic_test_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ return !!(*p & mask);
+}
+
static inline void generic_clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = BIT_MASK(nr);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support
[not found] <cover.1351876757.git.vipin.kumar@st.com>
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 2/9] spear3xx: Add pinmux support Vipin Kumar
` (7 more replies)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (2 subsequent siblings)
5 siblings, 8 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 7 ++++---
arch/arm/cpu/arm926ejs/spear/cache.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/cache.c
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 7d11035..cf29ede 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS-y := cpu.o \
- reset.o \
- timer.o
+COBJS-y += cache.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
COBJS-$(CONFIG_ST_EMI) += emi.o
COBJS-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cache.c b/arch/arm/cpu/arm926ejs/spear/cache.c
new file mode 100644
index 0000000..351e8cd
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/cache.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+#endif
+}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations
[not found] <cover.1351876757.git.vipin.kumar@st.com>
` (2 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board Vipin Kumar
` (9 more replies)
2012-11-07 14:10 ` [U-Boot] [PATCH 00/46] Enhance spear support Stefan Roese
2012-11-20 9:46 ` Vipin Kumar
5 siblings, 10 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
boards.cfg | 8 --------
1 file changed, 8 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index b14a08f..fe357e7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -201,23 +201,15 @@ dkb arm arm926ejs - Marvell pantheon
spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300
spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand
spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty
-spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand
spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310
spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR
spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand
spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty
-spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR
-spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand
spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320
-spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR
-spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand
spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty
-spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR
-spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand
spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600
spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
-spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
x600 arm arm926ejs - spear spear x600
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 02/19] mtd/st_smi: Add support for Micron N25Q128 Flash
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 03/19] mtd/st_smi: Avoid issuing multiple WE commands Vipin Kumar
` (15 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
From: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
---
drivers/mtd/st_smi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index fad4420..e2d1cf9 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -75,6 +75,7 @@ static struct flash_device flash_devices[] = {
FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
+ FLASH_ID("mcr n25q128" , 0xd8, 0x0018BA20, 0x100, 0x10000, 0x1000000),
FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 2/7] spear1310: Add support for spear1310 SoC
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 3/7] spear1340evb: Add support for evb machine Vipin Kumar
` (4 subsequent siblings)
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
spear1310 is a CortexA9 dual core SoC which supports multiple peripherals like
GMII, USBH, PCIe etc. More information can be found at
http://www.st.com/internet/mcu/product/250658.jsp
This patch adds support for spear1310 SoC. This patch also adds support for
pinmux for spear1310 SoC. The APIs implemented are
* spear1310_configure_pin: Configures a particular pin to GPIO, PULLDOWN,
PULLUP. The prototype is as follows
_void spear1310_configure_pin(u32 plgpio, u32 mode)_
* spear1310_plgpio_get: Configures a particular pin to GPIO IN and gets the
value on that particular GPIO. The prototype is as follows
_int spear1310_plgpio_get(u32 plgpio)_
* spear1310_plgpio_set: Configures a particular pin to GPIO OUT and sets a
value on that particular GPIO. The prototype is as follows
_void spear1310_plgpio_set(u32 plgpio, u32 val)_
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/armv7/spear13xx/Makefile | 2 +
arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c | 860 +++++++++++++++++++++
arch/arm/cpu/armv7/spear13xx/spear1310.c | 205 +++++
arch/arm/include/asm/arch-spear13xx/hardware.h | 2 +
arch/arm/include/asm/arch-spear13xx/misc.h | 3 +
arch/arm/include/asm/arch-spear13xx/pinmux.h | 10 +
arch/arm/include/asm/arch-spear13xx/spear1310.h | 244 ++++++
.../include/asm/arch-spear13xx/spear1310_misc.h | 300 +++++++
drivers/usb/host/ehci-spear.c | 2 +
9 files changed, 1628 insertions(+)
create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310.c
create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
index 214b89b..cacf268 100644
--- a/arch/arm/cpu/armv7/spear13xx/Makefile
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -29,6 +29,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
+COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310.o
+COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310-pinmux.o
COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o
COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o
diff --git a/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c b/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c
new file mode 100644
index 0000000..f204fda
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c
@@ -0,0 +1,860 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/* Pin multiplexing for i2c0 device */
+static void enable_i2c0_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_I2C0_MASK,
+ PMX_I2C0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_I2C0_MASK,
+ PMX_I2C0_MASK);
+}
+
+/* Pin multiplexing for ssp cs0 device */
+static void enable_ssp0cs0_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_SSP0_MASK,
+ PMX_SSP0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_SSP0_CS0_MASK,
+ PMX_SSP0_CS0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_SSP0_MASK,
+ PMX_SSP0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_SSP0_CS0_MASK,
+ PMX_SSP0_CS0_MASK);
+}
+
+/* Pin multiplexing for ssp0 cs1 and cs2 */
+static void enable_ssp0cs1cs2_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_SSP0_CS1_2_MASK,
+ PMX_SSP0_CS1_2_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_SSP0_CS1_2_MASK,
+ PMX_SSP0_CS1_2_MASK);
+}
+
+static void enable_ssp0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SSP_CS0:
+ enable_ssp0cs0_pins();
+ case PMX_SSP_CS1_CS2:
+ enable_ssp0cs1cs2_pins();
+ break;
+ }
+}
+/* Pin multiplexing for arm gpio device */
+static void enable_leggpio_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_EGPIO_0_GRP_MASK,
+ PMX_EGPIO_0_GRP_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_EGPIO_1_GRP_MASK,
+ PMX_EGPIO_1_GRP_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_EGPIO_0_GRP_MASK,
+ PMX_EGPIO_0_GRP_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_EGPIO_1_GRP_MASK,
+ PMX_EGPIO_1_GRP_MASK);
+}
+
+/* Pin multiplexing for smi two chips device */
+static void enable_smi2chips_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_SMI_MASK,
+ PMX_SMI_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_SMI_MASK,
+ PMX_SMI_MASK);
+}
+
+/* Pin multiplexing for smi four chips device */
+static void enable_smi4chips_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_SMI_MASK,
+ PMX_SMI_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ PMX_SMINCS2_MASK | PMX_SMINCS3_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_SMI_MASK,
+ PMX_SMI_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
+ PMX_SMINCS2_MASK | PMX_SMINCS3_MASK);
+}
+
+static void enable_smi_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SMI_2CHIPS:
+ enable_smi2chips_pins();
+ break;
+ case PMX_SMI_4CHIPS:
+ enable_smi4chips_pins();
+ break;
+ }
+}
+
+/*
+ * Pin multiplexing for ethernet device
+ * Ethernet on spear1310 can be configured as either of the below
+ * - GMII
+ * - RGMII
+ * - RMII
+ * - SGMII
+ */
+/* Pin multiplexing for gmii device */
+static void enable_gmii_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_GMII_MASK,
+ PMX_GMII_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_GMII_MASK,
+ PMX_GMII_MASK);
+}
+
+/* Pin multiplexing for rgmii device */
+static void enable_rgmii_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_RGMII_REG1_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_RGMII_REG2_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_RGMII_REG3_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_RGMII_REG1_MASK,
+ PMX_RGMII_REG1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_RGMII_REG2_MASK,
+ PMX_RGMII_REG2_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_RGMII_REG3_MASK,
+ PMX_RGMII_REG3_MASK);
+}
+
+static void enable_eth0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_ETH_GMII:
+ enable_gmii_pins();
+ break;
+ case PMX_ETH_RGMII:
+ enable_rgmii_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for nand 8bit device */
+static void enable_nand8bit_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_NAND8BIT_0_MASK,
+ PMX_NAND8BIT_0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_NAND8BIT_1_MASK,
+ PMX_NAND8BIT_1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_NAND8BIT_0_MASK,
+ PMX_NAND8BIT_0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_NAND8BIT_1_MASK,
+ PMX_NAND8BIT_1_MASK);
+}
+
+/* Pin multiplexing for nand 16bit device */
+static void enable_nand16bit_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_NAND8BIT_0_MASK,
+ PMX_NAND8BIT_0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_NAND8BIT_1_MASK,
+ PMX_NAND8BIT_1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_NAND16BIT_1_MASK,
+ PMX_NAND16BIT_1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_NAND8BIT_0_MASK,
+ PMX_NAND8BIT_0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_NAND8BIT_1_MASK,
+ PMX_NAND8BIT_1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_NAND16BIT_1_MASK,
+ PMX_NAND16BIT_1_MASK);
+}
+
+/* Pin multiplexing for nand 4chips device */
+static void enable_nand4chips_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_NAND_4CHIPS_MASK,
+ PMX_NAND_4CHIPS_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_NAND_4CHIPS_MASK,
+ PMX_NAND_4CHIPS_MASK);
+}
+
+/* Pin multiplexing for fsmc nand device */
+static void enable_nand_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_NAND_8BIT:
+ enable_nand8bit_pins();
+ break;
+ case PMX_NAND_16BIT:
+ enable_nand16bit_pins();
+ break;
+ case PMX_NAND_4CHIPS:
+ enable_nand4chips_pins();
+ }
+}
+
+/* Pin multiplexing for uart0 device */
+static void enable_uart0simple_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_UART0_MASK,
+ PMX_UART0_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_UART0_MASK,
+ PMX_UART0_MASK);
+}
+
+/* Pin multiplexing for uart0 modem device */
+static void enable_uart0modem_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_UART0_MODEM_MASK,
+ PMX_UART0_MODEM_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_UART0_MODEM_MASK,
+ PMX_UART0_MODEM_MASK);
+}
+
+
+static void enable_uart0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_UART_SIMPLE:
+ enable_uart0simple_pins();
+ break;
+ case PMX_UART_MODEM:
+ enable_uart0modem_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for sdmmc device */
+static void enable_sdmmc_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_MCI_DATA8_15_MASK,
+ PMX_MCI_DATA8_15_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |
+ PMX_NFWPRT2_MASK,
+ PMX_MCIFALL_1_MASK);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIFALL_2_MASK,
+ PMX_MCIFALL_2_MASK);
+ pinmux_maskval(SPEAR1310_PERIP_CFG,
+ MCIF_SEL_MASK,
+ MCIF_SEL_SD);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_MCI_DATA8_15_MASK,
+ PMX_MCI_DATA8_15_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |
+ PMX_NFWPRT2_MASK,
+ PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK |
+ PMX_NFWPRT2_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIFALL_2_MASK,
+ PMX_MCIFALL_2_MASK);
+}
+
+/* Pin multiplexing for uart1disi2c0 device */
+static void enable_uart1disi2c0_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_I2C0_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_I2C0_MASK,
+ PMX_I2C0_MASK);
+}
+
+/* Pin multiplexing for uart1 (disables SD) device */
+static void enable_uart1dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_MCIDATA1_MASK |
+ PMX_MCIDATA2_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_MCIDATA1_MASK | PMX_MCIDATA2_MASK,
+ PMX_MCIDATA1_MASK | PMX_MCIDATA2_MASK);
+}
+
+static void enable_uart1_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_UART_DISSD:
+ enable_uart1dissd_pins();
+ break;
+ case PMX_UART_DISI2C0:
+ enable_uart1disi2c0_pins();
+ break;
+ }
+}
+
+/* Pin multiplexing for uart 2 and 3 device */
+static void enable_uart23_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_I2S0_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_I2S0_MASK,
+ PMX_I2S0_MASK);
+}
+
+/* Pin multiplexing for uart 4 device */
+static void enable_uart4_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_I2S0_MASK | PMX_CLCD1_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_I2S0_MASK | PMX_CLCD1_MASK,
+ PMX_I2S0_MASK | PMX_CLCD1_MASK);
+}
+
+/* Pin multiplexing for uart 5 device */
+static void enable_uart5_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_CLCD1_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_CLCD1_MASK,
+ PMX_CLCD1_MASK);
+}
+
+/* Pin multiplexing for i2c 1 and 2 device */
+static void enable_i2c12_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_CLCD1_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_CLCD1_MASK,
+ PMX_CLCD1_MASK);
+}
+
+#if 0
+/* Pin multiplexing for i2c3 (Disables smi and clcd) device */
+static void enable_i2c3dissmiclcd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_CLCD1_MASK | PMX_SMI_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_CLCD1_MASK | PMX_SMI_MASK,
+ PMX_CLCD1_MASK | PMX_SMI_MASK);
+}
+
+/* Pin multiplexing for i2c3 (Disables sd and i2s0) device */
+static void enable_i2c3dissdi2s0_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
+ PMX_I2S1_MASK | PMX_MCIDATA3_MASK);
+}
+
+/* Pin multiplexing for i2c4 and 5 (Disables smi and clcd) device */
+static void enable_i2c3dissmiclcd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1,
+ PMX_SMI_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1,
+ PMX_SMI_MASK,
+ PMX_SMI_MASK);
+}
+
+/* Pin multiplexing for i2c4 (Disables sd) device */
+static void enable_i2c4dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_MCIDATA4_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIDATA5_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_MCIDATA4_MASK,
+ PMX_MCIDATA4_MASK);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIDATA5_MASK,
+ PMX_MCIDATA5_MASK);
+}
+
+/* Pin multiplexing for i2c5 (Disables sd) device */
+static void enable_i2c5dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK,
+ PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK);
+}
+
+/* Pin multiplexing for i2c6 and 7 (Disables kbd) device */
+static void enable_i2c67diskbd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_KBD_ROWCOL25_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_KBD_ROWCOL25_MASK,
+ PMX_KBD_ROWCOL25_MASK);
+}
+
+/* Pin multiplexing for i2c6 (Disables sd) device */
+static void enable_i2c6dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK,
+ PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK);
+}
+
+/* Pin multiplexing for i2c7 (Disables sd) device */
+static void enable_i2c7dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK,
+ PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK);
+}
+
+/* Pin multiplexing for ssp1 (Disables kbd) device */
+static void enable_ssp1diskbd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2,
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+ PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+ PMX_NFCE2_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2,
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+ PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+ PMX_NFCE2_MASK,
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
+ PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
+ PMX_NFCE2_MASK);
+}
+
+/* Pin multiplexing for ssp1 (Disables sd) device */
+static void enable_ssp1dissd_pins(void)
+{
+ pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3,
+ PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+ PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
+ 0);
+ pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3,
+ PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+ PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
+ PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
+ PMX_MCICECF_MASK | PMX_MCICEXD_MASK);
+}
+#endif
+
+/**
+ * spear1310_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear1310_pins_default(void)
+{
+}
+
+/**
+ * spear1310_enable_pins - enable pins for peripherals on spear1310 devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear1310_enable_pins(u32 ip, u32 mode)
+{
+ if (PMX_SDMMC == ip)
+ enable_sdmmc_pins();
+ else if (PMX_SMI == ip)
+ enable_smi_pins(mode);
+ else if (PMX_I2C0 == ip)
+ enable_i2c0_pins();
+ else if ((PMX_I2C1 == ip) || (PMX_I2C1 == ip))
+ enable_i2c12_pins();
+ else if (PMX_FSMCNAND == ip)
+ enable_nand_pins(mode);
+ else if (PMX_UART0 == ip)
+ enable_uart0_pins(mode);
+ else if (PMX_UART1 == ip)
+ enable_uart1_pins(mode);
+ else if ((PMX_UART2 == ip) || (PMX_UART3 == ip))
+ enable_uart23_pins();
+ else if (PMX_UART4 == ip)
+ enable_uart4_pins();
+ else if (PMX_UART5 == ip)
+ enable_uart5_pins();
+ else if (PMX_ETH0 == ip)
+ enable_eth0_pins(mode);
+ else if (PMX_SSP0 == ip)
+ enable_ssp0_pins(mode);
+ else if (PMX_LEGGPIO0 == ip)
+ enable_leggpio_pins();
+}
+
+static void configure_gpio(u32 plgpio)
+{
+ if (plgpio > SPEAR1310_MAX_PLGPIOS)
+ return;
+
+ /* Set the GPIO direction to input */
+ pinmux_set_bit(plgpio, SPEAR1310_GPIO_EN0);
+
+ /* Enable PLGPIO from RAS */
+ pinmux_set_bit(plgpio, SPEAR1310_GPIO_FUN_EN0);
+
+ if (plgpio <= 3) {
+ pinmux_clear_bit(16, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(16, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 4) && (plgpio <= 5)) {
+ pinmux_clear_bit(15, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(15, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 6) && (plgpio <= 7)) {
+ pinmux_clear_bit(14, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(14, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 8) && (plgpio <= 9)) {
+ pinmux_clear_bit(13, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(13, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 10) && (plgpio <= 11)) {
+ pinmux_clear_bit(12, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(12, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 12) && (plgpio <= 17)) {
+ pinmux_clear_bit(11, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(11, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 18) {
+ pinmux_clear_bit(10, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(10, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 19) {
+ pinmux_clear_bit(9, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(9, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 20) {
+ pinmux_clear_bit(8, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(8, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 21) {
+ pinmux_clear_bit(7, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(7, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 22) {
+ pinmux_clear_bit(6, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(6, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 23) {
+ pinmux_clear_bit(5, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(5, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 24) && (plgpio <= 29)) {
+ pinmux_clear_bit(4, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(4, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 30) && (plgpio <= 53)) {
+ pinmux_clear_bit(3, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(3, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 54) {
+ pinmux_clear_bit(2, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(2, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 55) {
+ pinmux_clear_bit(1, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(1, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 56) {
+ pinmux_clear_bit(0, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(0, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if (plgpio == 57) {
+ pinmux_clear_bit(31, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(31, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 58) {
+ pinmux_clear_bit(30, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(30, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 59) {
+ pinmux_clear_bit(29, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(29, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 60) {
+ pinmux_clear_bit(28, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(28, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 61) {
+ pinmux_clear_bit(27, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(27, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 62) {
+ pinmux_clear_bit(26, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(26, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 63) {
+ pinmux_clear_bit(25, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(25, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 64) && (plgpio <= 85)) {
+ pinmux_clear_bit(24, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(24, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 86) && (plgpio <= 93)) {
+ pinmux_clear_bit(23, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(23, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 94) && (plgpio <= 95)) {
+ pinmux_clear_bit(30, SPEAR1310_PAD_FUNCTION_EN_3);
+ pinmux_set_bit(30, SPEAR1310_PAD_DIR_SEL_3);
+
+ } else if (plgpio >= 96) {
+ pinmux_clear_bit(29, SPEAR1310_PAD_FUNCTION_EN_3);
+ pinmux_set_bit(29, SPEAR1310_PAD_DIR_SEL_3);
+
+ } else if (plgpio >= 97) {
+ pinmux_clear_bit(28, SPEAR1310_PAD_FUNCTION_EN_3);
+ pinmux_set_bit(28, SPEAR1310_PAD_DIR_SEL_3);
+
+ } else if ((plgpio >= 98) && (plgpio <= 99)) {
+ pinmux_clear_bit(22, SPEAR1310_PAD_FUNCTION_EN_2);
+ pinmux_set_bit(22, SPEAR1310_PAD_DIR_SEL_2);
+
+ } else if ((plgpio >= 100) && (plgpio <= 101)) {
+ pinmux_clear_bit(1, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(1, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 102) && (plgpio <= 103)) {
+ pinmux_clear_bit(2, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(2, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 104) && (plgpio <= 108)) {
+ pinmux_clear_bit(3, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(3, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 109) && (plgpio <= 112)) {
+ pinmux_clear_bit(4, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(4, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 113) && (plgpio <= 142)) {
+ pinmux_clear_bit(5, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(5, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 143) && (plgpio <= 152)) {
+ pinmux_clear_bit(plgpio - 137, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(plgpio - 137, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 153) && (plgpio <= 157)) {
+ pinmux_clear_bit(16, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(16, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 158) && (plgpio <= 172)) {
+ pinmux_clear_bit(17, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(17, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 173) && (plgpio <= 174)) {
+ pinmux_clear_bit(18, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(18, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 175) {
+ pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 176) && (plgpio <= 179)) {
+ pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 180) && (plgpio <= 183)) {
+ pinmux_clear_bit(21, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(21, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 184) {
+ pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 185) {
+ pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 186) && (plgpio <= 187)) {
+ pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if (plgpio == 188) {
+ pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 189) && (plgpio <= 192)) {
+ pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 193) && (plgpio <= 196)) {
+ pinmux_clear_bit(21, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(21, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 197) && (plgpio <= 198)) {
+ pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1);
+
+ } else if ((plgpio >= 199) && (plgpio <= 200)) {
+ pinmux_clear_bit(22, SPEAR1310_PAD_FUNCTION_EN_1);
+ pinmux_set_bit(22, SPEAR1310_PAD_DIR_SEL_1);
+
+ }
+}
+
+static void configure_pullup(u32 plgpio)
+{
+ if (plgpio > SPEAR1310_MAX_PLGPIOS)
+ return;
+
+ /* Deactivate pull down */
+ pinmux_set_bit(plgpio, SPEAR1310_PAD_PD_CFG_1);
+
+ /* Activate pull up */
+ pinmux_clear_bit(plgpio, SPEAR1310_PAD_PU_CFG_1);
+}
+
+static void configure_pulldown(u32 plgpio)
+{
+ if (plgpio > SPEAR1310_MAX_PLGPIOS)
+ return;
+
+ /* Deactivate pull up */
+ pinmux_set_bit(plgpio, SPEAR1310_PAD_PU_CFG_1);
+
+ /* Activate pull down */
+ pinmux_clear_bit(plgpio, SPEAR1310_PAD_PD_CFG_1);
+}
+
+/**
+ * spear1310_configure_pin - Configure pin on spear1310 devices
+ * @plgpio: Pin Number (plgpio number)
+ * @mode: Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc
+ */
+void spear1310_configure_pin(u32 plgpio, u32 mode)
+{
+ if (PMX_GPIO == mode)
+ configure_gpio(plgpio);
+ else if (PMX_PULLUP == mode)
+ configure_pullup(plgpio);
+ else if (PMX_PULLDOWN == mode)
+ configure_pulldown(plgpio);
+}
+
+/**
+ * spear1310_plgpio_get - Get the gpio input
+ * @plgpio: Pin Number (plgpio number)
+ */
+int spear1310_plgpio_get(u32 plgpio)
+{
+ if (plgpio > SPEAR1310_MAX_PLGPIOS)
+ return -1;
+
+ /* Set the pin to GPIO IN mode */
+ pinmux_set_bit(plgpio, SPEAR1310_GPIO_EN0);
+
+ return pinmux_test_bit(plgpio, SPEAR1310_GPIO_IN0);
+}
+
+/**
+ * spear1310_plgpio_set - Set the gpio value
+ * @plgpio: Pin Number (plgpio number)
+ */
+void spear1310_plgpio_set(u32 plgpio, u32 val)
+{
+ if (plgpio > SPEAR1310_MAX_PLGPIOS)
+ return;
+
+ if (val & 0x1)
+ pinmux_set_bit(plgpio, SPEAR1310_GPIO_OUT0);
+ else
+ pinmux_clear_bit(plgpio, SPEAR1310_GPIO_OUT0);
+
+ /* Set the pin to GPIO OUT mode */
+ pinmux_clear_bit(plgpio, SPEAR1310_GPIO_EN0);
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spear1310.c b/arch/arm/cpu/armv7/spear13xx/spear1310.c
new file mode 100644
index 0000000..9936d25
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spear1310.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/misc.h>
+
+int arch_cpu_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip1_clk_enb, perip2_clk_enb;
+ u32 perip_clk_cfg;
+#if defined(CONFIG_SDHCI)
+ u32 perip_cfg;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+ u32 fsmc_cfg;
+#endif
+ perip1_clk_enb = readl(&misc_p->perip1_clk_enb);
+ perip2_clk_enb = readl(&misc_p->perip2_clk_enb);
+
+#if defined(CONFIG_PL011_SERIAL)
+ /* select USB PLL 48 MHz as the src clock */
+ perip_clk_cfg = readl(&misc_p->perip_clk_cfg);
+ perip_clk_cfg &= ~SPEAR1310_UARTCLKMSK;
+ perip_clk_cfg |= SPEAR1310_UART48M;
+ writel(perip_clk_cfg, &misc_p->perip_clk_cfg);
+
+ perip1_clk_enb |= SPEAR1310_UART_CLKEN;
+#endif
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ perip1_clk_enb |= SPEAR1310_GETH_CLKEN;
+#endif
+
+#if defined(CONFIG_DW_UDC)
+ perip1_clk_enb |= SPEAR1310_UDC_UPD_CLKEN;
+#endif
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+ perip1_clk_enb |= SPEAR1310_UHC1_CLKEN;
+#endif
+
+#if defined(CONFIG_DW_I2C)
+ perip1_clk_enb |= SPEAR1310_I2C_CLKEN;
+#endif
+
+#if defined(CONFIG_ST_SMI)
+ perip1_clk_enb |= SPEAR1310_SMI_CLKEN;
+#endif
+
+#if defined(CONFIG_PL022_SPI)
+ perip1_clk_enb |= SPEAR1310_SSP_CLKEN;
+#endif
+
+#if defined(CONFIG_SDHCI)
+ perip_cfg = readl(&misc_p->perip_cfg);
+ perip_cfg &= ~SPEAR1310_MCIF_MSK;
+ perip_cfg |= SPEAR1310_MCIF_SD;
+ writel(perip_cfg, &misc_p->perip_cfg);
+
+ writel(SPEAR1310_SYNT_X_2 | SPEAR1310_SYNT_Y_21 |
+ SPEAR1310_SYNT_CLKENB, &misc_p->mcif_sd_clk_synt);
+
+ perip1_clk_enb |= SPEAR1310_SD_CLKEN;
+#endif
+
+#if defined(CONFIG_NAND_FSMC)
+ fsmc_cfg = readl(&misc_p->fsmc_cfg);
+ fsmc_cfg &= ~SPEAR1310_NANDCS0_NORCS4;
+ writel(fsmc_cfg, &misc_p->fsmc_cfg);
+
+ perip1_clk_enb |= SPEAR1310_FSMC_CLKEN;
+#endif
+
+ writel(perip1_clk_enb, &misc_p->perip1_clk_enb);
+ writel(perip2_clk_enb, &misc_p->perip2_clk_enb);
+
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ printf("CPU: SPEAr1310\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+void spear1310_usbh_stop(void)
+{
+ struct spear1310_misc_regs *const misc_regs_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip1_sw_rst = readl(&misc_regs_p->perip1_sw_rst);
+
+ perip1_sw_rst |= SPEAR1310_UHC1_SWRST;
+ writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst);
+
+ udelay(1000);
+ perip1_sw_rst &= ~SPEAR1310_UHC1_SWRST;
+ writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst);
+}
+#endif
+
+#ifdef CONFIG_DW_OTG_PHYINIT
+void udc_phy_init(void)
+{
+ struct spear1310_misc_regs *const misc_regs_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ u32 temp;
+
+ /* phy por assert */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp |= SPEAR1310_USBPHY_POR;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+ udelay(1);
+
+ /* phy clock disable */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp &= ~SPEAR1310_USBPHY_RST;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+
+ udelay(150);
+
+ /* phy por deassert */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp &= ~SPEAR1310_USBPHY_POR;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+ udelay(1);
+
+ /* phy clock enable */
+ temp = readl(&misc_regs_p->usbphy_gen_cfg);
+ temp |= SPEAR1310_USBPHY_RST;
+ writel(temp, &misc_regs_p->usbphy_gen_cfg);
+
+ /* wait for pll lock */
+ while (!(readl(&misc_regs_p->usbphy_gen_cfg) & USB_PLL_LOCK))
+ ;
+
+ udelay(1);
+
+ /* OTG HCLK Disable */
+ temp = readl(&misc_regs_p->perip1_clk_enb);
+ temp &= ~SPEAR1310_UDC_UPD_CLKEN;
+ writel(temp, &misc_regs_p->perip1_clk_enb);
+
+ /* OTG HRESET deassert */
+ temp = readl(&misc_regs_p->perip1_sw_rst);
+ temp &= ~SPEAR1310_UDC_UPD_SWRST;
+ writel(temp, &misc_regs_p->perip1_sw_rst);
+
+ /* OTG HCLK Enable */
+ temp = readl(&misc_regs_p->perip1_clk_enb);
+ temp |= SPEAR1310_UDC_UPD_CLKEN;
+ writel(temp, &misc_regs_p->perip1_clk_enb);
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+ struct spear1310_misc_regs *misc_regs_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ printf("System is going to reboot ...\n");
+
+ /*
+ * This 1 second delay will allow the above message
+ * to be printed before reset
+ */
+ udelay((1000 * 1000));
+
+ writel(0x01, &misc_regs_p->sys_sw_res);
+
+ /* system will restart */
+ while (1)
+ ;
+}
diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h
index b49ef67..616b57d 100644
--- a/arch/arm/include/asm/arch-spear13xx/hardware.h
+++ b/arch/arm/include/asm/arch-spear13xx/hardware.h
@@ -26,6 +26,8 @@
#if defined(CONFIG_SOC_SPEAR1340)
#include <asm/arch/spear1340.h>
+#elif defined(CONFIG_SOC_SPEAR1310)
+#include <asm/arch/spear1310.h>
#endif
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear13xx/misc.h b/arch/arm/include/asm/arch-spear13xx/misc.h
index 5134938..531862a 100644
--- a/arch/arm/include/asm/arch-spear13xx/misc.h
+++ b/arch/arm/include/asm/arch-spear13xx/misc.h
@@ -26,6 +26,9 @@
#ifdef CONFIG_SOC_SPEAR1340
#include <asm/arch/spear1340_misc.h>
+
+#elif defined(CONFIG_SOC_SPEAR1310)
+#include <asm/arch/spear1310_misc.h>
#endif
#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/pinmux.h b/arch/arm/include/asm/arch-spear13xx/pinmux.h
index 9354f21..01531f1 100644
--- a/arch/arm/include/asm/arch-spear13xx/pinmux.h
+++ b/arch/arm/include/asm/arch-spear13xx/pinmux.h
@@ -72,17 +72,22 @@ enum pinmux_ip {
PMX_SDMMC,
PMX_EMI,
PMX_SMI,
+ PMX_LEGGPIO0,
+ PMX_LEGGPIO1,
};
/* UART0 modem modes */
#define PMX_UART_SIMPLE 1
#define PMX_UART_MODEM 2
+#define PMX_UART_DISSD 3
+#define PMX_UART_DISI2C0 4
/* SSP modes */
#define PMX_SSP_CS0 1
#define PMX_SSP_CS1 2
#define PMX_SSP_CS2 3
#define PMX_SSP_CS3 4
+#define PMX_SSP_CS1_CS2 5
/* ETH modes */
#define PMX_ETH_GMII 1
@@ -95,6 +100,11 @@ enum pinmux_ip {
/* NAND modes */
#define PMX_NAND_8BIT 1
#define PMX_NAND_16BIT 2
+#define PMX_NAND_4CHIPS 3
+
+/* SMI modes */
+#define PMX_SMI_2CHIPS 1
+#define PMX_SMI_4CHIPS 2
/* PLGPIO modes */
#define PMX_GPIO 1
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310.h b/arch/arm/include/asm/arch-spear13xx/spear1310.h
new file mode 100644
index 0000000..95d38aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/spear1310.h
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR1310_PINMUX_H
+#define _ASM_ARCH_SPEAR1310_PINMUX_H
+
+#include <asm/arch/spear13xx.h>
+
+#define SPEAR1310_PERIP_CFG (CONFIG_SYS_MISC_BASE + 0x32C)
+ #define MCIF_SEL_SHIFT 3
+ #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
+ #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
+
+#define SPEAR1310_PCIE_SATA_CFG (CONFIG_SYS_MISC_BASE + 0x3A4)
+ #define PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define PCIE_SATA2_SEL_SATA (1 << 31)
+ #define PCIE_SATA1_SEL_SATA (1 << 30)
+ #define PCIE_SATA0_SEL_SATA (1 << 29)
+ #define SATA2_CFG_TX_CLK_EN (1 << 27)
+ #define SATA2_CFG_RX_CLK_EN (1 << 26)
+ #define SATA2_CFG_POWERUP_RESET (1 << 25)
+ #define SATA2_CFG_PM_CLK_EN (1 << 24)
+ #define SATA1_CFG_TX_CLK_EN (1 << 23)
+ #define SATA1_CFG_RX_CLK_EN (1 << 22)
+ #define SATA1_CFG_POWERUP_RESET (1 << 21)
+ #define SATA1_CFG_PM_CLK_EN (1 << 20)
+ #define SATA0_CFG_TX_CLK_EN (1 << 19)
+ #define SATA0_CFG_RX_CLK_EN (1 << 18)
+ #define SATA0_CFG_POWERUP_RESET (1 << 17)
+ #define SATA0_CFG_PM_CLK_EN (1 << 16)
+ #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
+ #define PCIE2_CFG_POWERUP_RESET (1 << 10)
+ #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
+ #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
+ #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
+ #define PCIE1_CFG_POWERUP_RESET (1 << 6)
+ #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
+ #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
+ #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
+ #define PCIE0_CFG_POWERUP_RESET (1 << 2)
+ #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
+ #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
+
+#define SPEAR1310_PAD_DIR_SEL_1 (CONFIG_SYS_MISC_BASE + 0x65C)
+#define SPEAR1310_PAD_FUNCTION_EN_1 (CONFIG_SYS_MISC_BASE + 0x650)
+ #define PMX_UART0_MASK (1 << 1)
+ #define PMX_I2C0_MASK (1 << 2)
+ #define PMX_I2S0_MASK (1 << 3)
+ #define PMX_SSP0_MASK (1 << 4)
+ #define PMX_CLCD1_MASK (1 << 5)
+ #define PMX_EGPIO00_MASK (1 << 6)
+ #define PMX_EGPIO01_MASK (1 << 7)
+ #define PMX_EGPIO02_MASK (1 << 8)
+ #define PMX_EGPIO03_MASK (1 << 9)
+ #define PMX_EGPIO04_MASK (1 << 10)
+ #define PMX_EGPIO05_MASK (1 << 11)
+ #define PMX_EGPIO06_MASK (1 << 12)
+ #define PMX_EGPIO07_MASK (1 << 13)
+ #define PMX_EGPIO08_MASK (1 << 14)
+ #define PMX_EGPIO09_MASK (1 << 15)
+ #define PMX_SMI_MASK (1 << 16)
+ #define PMX_NAND8_MASK (1 << 17)
+ #define PMX_GMIICLK_MASK (1 << 18)
+ #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
+ #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
+ #define PMX_GMIID47_MASK (1 << 21)
+ #define PMX_MDC_MDIO_MASK (1 << 22)
+ #define PMX_MCI_DATA8_15_MASK (1 << 23)
+ #define PMX_NFAD23_MASK (1 << 24)
+ #define PMX_NFAD24_MASK (1 << 25)
+ #define PMX_NFAD25_MASK (1 << 26)
+ #define PMX_NFCE3_MASK (1 << 27)
+ #define PMX_NFWPRT3_MASK (1 << 28)
+ #define PMX_NFRSTPWDWN0_MASK (1 << 29)
+ #define PMX_NFRSTPWDWN1_MASK (1 << 30)
+ #define PMX_NFRSTPWDWN2_MASK (1 << 31)
+
+#define SPEAR1310_PAD_DIR_SEL_2 (CONFIG_SYS_MISC_BASE + 0x660)
+#define SPEAR1310_PAD_FUNCTION_EN_2 (CONFIG_SYS_MISC_BASE + 0x654)
+ #define PMX_NFRSTPWDWN3_MASK (1 << 0)
+ #define PMX_SMINCS2_MASK (1 << 1)
+ #define PMX_SMINCS3_MASK (1 << 2)
+ #define PMX_CLCD2_MASK (1 << 3)
+ #define PMX_KBD_ROWCOL68_MASK (1 << 4)
+ #define PMX_EGPIO10_MASK (1 << 5)
+ #define PMX_EGPIO11_MASK (1 << 6)
+ #define PMX_EGPIO12_MASK (1 << 7)
+ #define PMX_EGPIO13_MASK (1 << 8)
+ #define PMX_EGPIO14_MASK (1 << 9)
+ #define PMX_EGPIO15_MASK (1 << 10)
+ #define PMX_UART0_MODEM_MASK (1 << 11)
+ #define PMX_GPT0_TMR0_MASK (1 << 12)
+ #define PMX_GPT0_TMR1_MASK (1 << 13)
+ #define PMX_GPT1_TMR0_MASK (1 << 14)
+ #define PMX_GPT1_TMR1_MASK (1 << 15)
+ #define PMX_I2S1_MASK (1 << 16)
+ #define PMX_KBD_ROWCOL25_MASK (1 << 17)
+ #define PMX_NFIO8_15_MASK (1 << 18)
+ #define PMX_KBD_COL1_MASK (1 << 19)
+ #define PMX_NFCE1_MASK (1 << 20)
+ #define PMX_KBD_COL0_MASK (1 << 21)
+ #define PMX_NFCE2_MASK (1 << 22)
+ #define PMX_KBD_ROW1_MASK (1 << 23)
+ #define PMX_NFWPRT1_MASK (1 << 24)
+ #define PMX_KBD_ROW0_MASK (1 << 25)
+ #define PMX_NFWPRT2_MASK (1 << 26)
+ #define PMX_MCIDATA0_MASK (1 << 27)
+ #define PMX_MCIDATA1_MASK (1 << 28)
+ #define PMX_MCIDATA2_MASK (1 << 29)
+ #define PMX_MCIDATA3_MASK (1 << 30)
+ #define PMX_MCIDATA4_MASK (1 << 31)
+
+#define SPEAR1310_PAD_DIR_SEL_3 (CONFIG_SYS_MISC_BASE + 0x664)
+#define SPEAR1310_PAD_FUNCTION_EN_3 (CONFIG_SYS_MISC_BASE + 0x658)
+ #define PMX_MCIDATA5_MASK (1 << 0)
+ #define PMX_MCIDATA6_MASK (1 << 1)
+ #define PMX_MCIDATA7_MASK (1 << 2)
+ #define PMX_MCIDATA1SD_MASK (1 << 3)
+ #define PMX_MCIDATA2SD_MASK (1 << 4)
+ #define PMX_MCIDATA3SD_MASK (1 << 5)
+ #define PMX_MCIADDR0ALE_MASK (1 << 6)
+ #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
+ #define PMX_MCIADDR2_MASK (1 << 8)
+ #define PMX_MCICECF_MASK (1 << 9)
+ #define PMX_MCICEXD_MASK (1 << 10)
+ #define PMX_MCICESDMMC_MASK (1 << 11)
+ #define PMX_MCICDCF1_MASK (1 << 12)
+ #define PMX_MCICDCF2_MASK (1 << 13)
+ #define PMX_MCICDXD_MASK (1 << 14)
+ #define PMX_MCICDSDMMC_MASK (1 << 15)
+ #define PMX_MCIDATADIR_MASK (1 << 16)
+ #define PMX_MCIDMARQWP_MASK (1 << 17)
+ #define PMX_MCIIORDRE_MASK (1 << 18)
+ #define PMX_MCIIOWRWE_MASK (1 << 19)
+ #define PMX_MCIRESETCF_MASK (1 << 20)
+ #define PMX_MCICS0CE_MASK (1 << 21)
+ #define PMX_MCICFINTR_MASK (1 << 22)
+ #define PMX_MCIIORDY_MASK (1 << 23)
+ #define PMX_MCICS1_MASK (1 << 24)
+ #define PMX_MCIDMAACK_MASK (1 << 25)
+ #define PMX_MCISDCMD_MASK (1 << 26)
+ #define PMX_MCILEDS_MASK (1 << 27)
+ #define PMX_TOUCH_XY_MASK (1 << 28)
+ #define PMX_SSP0_CS0_MASK (1 << 29)
+ #define PMX_SSP0_CS1_2_MASK (1 << 30)
+
+/* combined macros */
+#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
+ PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
+ PMX_RXCLK_RDV_TXEN_D03_MASK | \
+ PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
+
+#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
+ PMX_EGPIO02_MASK | \
+ PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
+ PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
+ PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
+ PMX_EGPIO09_MASK)
+#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
+ PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
+ PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
+
+#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+ PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
+ PMX_KBD_COL1_MASK)
+
+#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
+ PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
+ PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
+ PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
+ PMX_NFCE3_MASK)
+#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
+
+#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
+#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
+ PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
+ PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
+ PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
+
+#define PMX_MCIFALL_1_MASK 0xF8000000
+#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
+
+#define PMX_PCI_REG2_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
+ PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
+ PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
+ PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
+ PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
+ PMX_NFCE2_MASK)
+#define PMX_PCI_REG3_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
+ PMX_SSP0_CS1_2_MASK)
+
+#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
+#define PMX_RGMII_REG1_MASK (PMX_MCI_DATA8_15_MASK | \
+ PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
+ PMX_GMIID47_MASK)
+#define PMX_RGMII_REG2_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
+ PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
+ PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
+#define PMX_RGMII_REG3_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
+ PMX_SSP0_CS1_2_MASK)
+
+/* Pull DOWN and Pull UP */
+#define SPEAR1310_PAD_PU_CFG_1 (CONFIG_SYS_MISC_BASE + 0x600)
+#define SPEAR1310_PAD_PD_CFG_1 (CONFIG_SYS_MISC_BASE + 0x620)
+
+/* Macro's to configure plgpios as Pull UP, Pull Down */
+#define CONFIG_SYS_RASCFG_BASE 0xD8400000
+ #define SPEAR1310_GPIO_IN0 (CONFIG_SYS_RASCFG_BASE + 0x70)
+ #define SPEAR1310_GPIO_OUT0 (CONFIG_SYS_RASCFG_BASE + 0x90)
+ #define SPEAR1310_GPIO_EN0 (CONFIG_SYS_RASCFG_BASE + 0xB0)
+ #define SPEAR1310_GPIO_FUN_EN0 (CONFIG_SYS_RASCFG_BASE + 0xD0)
+ #define SPEAR1310_MAX_PLGPIOS 200
+
+extern void spear1310_pins_default(void);
+extern void spear1310_enable_pins(u32 ip, u32 mode);
+extern void spear1310_configure_pin(u32 plgpio, u32 mode);
+extern void spear1310_plgpio_set(u32 plgpio, u32 val);
+extern int spear1310_plgpio_get(u32 plgpio);
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
new file mode 100644
index 0000000..8d8278e
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2012
+ * Amit Virdi, ST Microelectronics, amit.virdi at st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPEAR1310_REVC_MISC_H
+#define __SPEAR1310_REVC_MISC_H
+
+struct spear1310_misc_regs {
+ u32 soc_cfg; /* 0x000 */
+ u32 bootstrap_cfg; /* 0x004 */
+ u8 reserved_1[0x100 - 0x8];
+ u32 pcm_cfg; /* 0x100 */
+ u32 pcm_wkup_cfg; /* 0x104 */
+ u32 switch_ctr; /* 0x108 */
+ u8 reserved_2[0x200 - 0x10c];
+ u32 sys_clk_ctrl; /* 0x200 */
+ u32 sys_sw_res; /* 0x204 */
+ u32 sys_clk_plltimer; /* 0x208 */
+ u32 sys_clk_oscitimer; /* 0x20c */
+ u32 pll_cfg; /* 0x210 */
+ u32 pll1_ctr; /* 0x214 */
+ u32 pll1_frq; /* 0x218 */
+ u32 pll1_mod; /* 0x21c */
+ u32 pll2_ctr; /* 0x220 */
+ u32 pll2_frq; /* 0x224 */
+ u32 pll2_mod; /* 0x228 */
+ u32 pll3_ctr; /* 0x22c */
+ u32 pll3_frq; /* 0x230 */
+ u32 pll3_mod; /* 0x234 */
+ u32 pll4_ctr; /* 0x238 */
+ u32 pll4_frq; /* 0x23C */
+ u32 pll4_mod; /* 0x240 */
+ u32 perip_clk_cfg; /* 0x244 */
+ u32 gmac_clk_cfg; /* 0x248 */
+ u32 i2s_clk_cfg; /* 0x24c */
+ u32 c3_clk_synt; /* 0x250 */
+ u32 uart_clk_synt; /* 0x254 */
+ u32 gmac_clk_synt; /* 0x258 */
+ u32 mcif_sd_clk_synt; /* 0x25c */
+ u32 mcif_cfxd_clk_synt; /* 0x260 */
+ u32 adc_clk_synt; /* 0x264 */
+ u32 amba_clk_sscg; /* 0x268 */
+ u32 amba_clk_sscg_mod; /* 0x26c */
+ u32 clcd_clk_sscg; /* 0x270 */
+ u32 expi_cpu_sscg_mod; /* 0x274 */
+ u32 gen_clk_sscg0; /* 0x278 */
+ u32 gen_clk_sscg0_mod; /* 0x27c */
+ u32 gen_clk_sscg1; /* 0x280 */
+ u32 gen_clk_sscg1_mod; /* 0x284 */
+ u32 gen_clk_sscg2; /* 0x288 */
+ u32 gen_clk_sscg2_mod; /* 0x28C */
+ u32 gen_clk_sscg3; /* 0x290 */
+ u32 clcd_clk_sscg_mod; /* 0x294 */
+ u32 expi_cpu_sscg; /* 0x298 */
+ u32 gen_clk_sscg3_mod; /* 0x29c */
+ u8 reserved_3[0x300 - 0x2a0];
+ u32 perip1_clk_enb; /* 0x300 */
+ u32 perip2_clk_enb; /* 0x304 */
+ u32 perip1_sw_rst; /* 0x308 */
+ u32 perip2_sw_rst; /* 0x30c */
+ u32 ras_clk_enb; /* 0x310 */
+ u32 ras_sw_rst; /* 0x314 */
+ u8 reserved_4[0x380 - 0x318];
+ u32 dmac_hs_sel; /* 0x380 */
+ u32 dmac_sel; /* 0x384 */
+ u32 dmac_flow_sel; /* 0x388 */
+ u32 dmac_dir_sel; /* 0x38c */
+ u32 endianess_cfg; /* 0x390 */
+ u32 usbphy_gen_cfg; /* 0x394 */
+ u32 usbphy_p1_cfg; /* 0x398 */
+ u32 usbphy_p2_cfg; /* 0x39c */
+ u32 usbphy_p3_cfg; /* 0x3a0 */
+ u32 pcie_sata_cfg; /* 0x3a4 */
+ u32 pcie_miphy_cfg_1; /* 0x3a8 */
+ u32 pcie_miphy_cfg_2; /* 0x3ac */
+ u32 perip_cfg; /* 0x3b0 */
+ u32 fsmc_cfg; /* 0x3b4 */
+ u32 mpmc_cfg; /* 0x3b8 */
+ u32 mpmc_ctr_sts; /* 0x3bc */
+ u8 reserved_5[0x400 - 0x3c0];
+ u32 expif_clk_cfg; /* 0x400 */
+ u32 expif_cfg; /* 0x404 */
+ u32 expif_dmachs_flex; /* 0x408 */
+ u8 reserved_6[0x41c - 0x40c];
+ u32 expif_dmachs_simple; /* 0x41c */
+ u32 expif_addr_expansion_tab_0; /* 0x420 */
+ u32 expif_addr_expansion_tab_1; /* 0x424 */
+ u32 expif_addr_expansion_tab_2; /* 0x428 */
+ u32 expif_addr_expansion_tab_3; /* 0x42c */
+ u32 expif_addr_expansion_tab_4; /* 0x430 */
+ u32 expif_addr_expansion_tab_5; /* 0x434 */
+ u32 expif_addr_expansion_tab_6; /* 0x438 */
+ u32 expif_addr_expansion_tab_7; /* 0x43c */
+ u8 reserved_7[0x500 - 0x440];
+ u32 prc1_lock_ctr; /* 0x500 */
+ u32 prc2_lock_ctr; /* 0x504 */
+ u32 prc1_irq_ctr; /* 0x508 */
+ u8 reserved_8[0x51c - 0x50c];
+ u32 prc2_irq_ctr; /* 0x51c */
+ u8 reserved_9[0x600 - 0x520];
+ u32 pad_pu_cfg_1; /* 0x600 */
+ u32 pad_pu_cfg_2; /* 0x604 */
+ u32 pad_pu_cfg_3; /* 0x608 */
+ u32 pad_pu_cfg_4; /* 0x60c */
+ u32 pad_pu_cfg_5; /* 0x610 */
+ u32 pad_pu_cfg_6; /* 0x614 */
+ u32 pad_pu_cfg_7; /* 0x618 */
+ u32 pad_pu_cfg_8; /* 0x61c */
+ u32 pad_pd_cfg_1; /* 0x620 */
+ u32 pad_pd_cfg_2; /* 0x624 */
+ u32 pad_pd_cfg_3; /* 0x628 */
+ u32 pad_pd_cfg_4; /* 0x62c */
+ u32 pad_pd_cfg_5; /* 0x630 */
+ u32 pad_pd_cfg_6; /* 0x634 */
+ u32 pad_pd_cfg_7; /* 0x638 */
+ u32 pad_pd_cfg_8; /* 0x63c */
+ u32 pad_sleep_cfg; /* 0x640 */
+ u32 pad_hyst_cfg; /* 0x644 */
+ u32 pad_drv_cfg; /* 0x648 */
+ u32 pad_slew_cfg; /* 0x64c */
+ u32 pad_function_en_1; /* 0x650 */
+ u32 pad_function_en_2; /* 0x654 */
+ u32 pad_function_en_3; /* 0x658 */
+ u32 pad_dir_sel_1; /* 0x65c */
+ u32 pad_dir_sel_2; /* 0x660 */
+ u32 pad_dir_sel_3; /* 0x664 */
+ u32 ddr_pad_cfg; /* 0x668 */
+ u8 reserved_10[0x700 - 0x66c];
+ u32 compensation_1v8_2v5_3v3_1_cfg; /* 0x700 */
+ u32 compensation_1v8_2v5_3v3_2_cfg; /* 0x704 */
+ u32 compensation_3v3_1_cfg; /* 0x708 */
+ u32 compensation_3v3_2_cfg; /* 0x70c */
+ u32 compensation_3v3_3_cfg; /* 0x710 */
+ u32 compensation_ddr_cfg; /* 0x714 */
+ u8 reserved_11[0x800 - 0x718];
+ u32 otp_prog_ctr; /* 0x800 */
+ u32 otp_wdata1_1; /* 0x804 */
+ u32 otp_wdata1_2; /* 0x808 */
+ u32 otp_wdata1_3; /* 0x80c */
+ u32 otp_wdata1_4; /* 0x810 */
+ u32 otp_wdata1_5; /* 0x814 */
+ u32 otp_wdata1_6; /* 0x818 */
+ u32 otp_wdata1_7; /* 0x81c */
+ u32 otp_wdata1_8; /* 0x820 */
+ u32 otp_wdata2_1; /* 0x824 */
+ u32 otp_wdata2_2; /* 0x828 */
+ u32 otp_wdata2_3; /* 0x82c */
+ u32 otp_wdata2_4; /* 0x830 */
+ u32 otp_wdata2_5; /* 0x834 */
+ u32 otp_wdata2_6; /* 0x838 */
+ u32 otp_wdata2_7; /* 0x83c */
+ u32 otp_wdata2_8; /* 0x840 */
+ u32 otp_mask_1; /* 0x844 */
+ u32 otp_mask_2; /* 0x848 */
+ u32 otp_mask_3; /* 0x84c */
+ u32 otp_mask_4; /* 0x850 */
+ u32 otp_mask_5; /* 0x854 */
+ u32 otp_mask_6; /* 0x858 */
+ u32 otp_mask_7; /* 0x85c */
+ u32 otp_mask_8; /* 0x860 */
+ u32 otp_rdata1_1; /* 0x864 */
+ u32 otp_rdata1_2; /* 0x868 */
+ u32 otp_rdata1_3; /* 0x86c */
+ u32 otp_rdata1_4; /* 0x870 */
+ u32 otp_rdata1_5; /* 0x874 */
+ u32 otp_rdata1_6; /* 0x878 */
+ u32 otp_rdata1_7; /* 0x87c */
+ u32 otp_rdata1_8; /* 0x880 */
+ u32 otp_rdata2_1; /* 0x884 */
+ u32 otp_rdata2_2; /* 0x888 */
+ u32 otp_rdata2_3; /* 0x88c */
+ u32 otp_rdata2_4; /* 0x890 */
+ u32 otp_rdata2_5; /* 0x894 */
+ u32 otp_rdata2_6; /* 0x898 */
+ u32 otp_rdata2_7; /* 0x89c */
+ u32 otp_rdata2_8; /* 0x8a0 */
+ u32 otp_rdatam_1; /* 0x8a4 */
+ u32 otp_rdatam_2; /* 0x8a8 */
+ u32 otp_rdatam_3; /* 0x8ac */
+ u32 otp_rdatam_4; /* 0x8b0 */
+ u32 otp_rdatam_5; /* 0x8b4 */
+ u32 otp_rdatam_6; /* 0x8b8 */
+ u32 otp_rdatam_7; /* 0x8bc */
+ u32 otp_rdatam_8; /* 0x8c0 */
+ u32 thsens_cfg; /* 0x8c4 */
+ u8 reserved_12[0x900 - 0x8c8];
+ u32 a9sm_clusterid; /* 0x900 */
+ u32 a9sm_status; /* 0x904 */
+ u32 a9sm_debug; /* 0x908 */
+ u32 a9sm_filter; /* 0x90c */
+ u32 a9sm_parity_cfg; /* 0x910 */
+ u32 a9sm_parity_err; /* 0x914 */
+ u8 reserved_13[0xa00 - 0x918];
+ u32 die_id_1; /* 0xa00 */
+ u32 die_id_2; /* 0xa04 */
+ u32 die_id_3; /* 0xa08 */
+ u32 die_id_4; /* 0xa0c */
+ u8 reserved_14[0xb00 - 0xa10];
+ u32 ras1_gpp_inp; /* 0xb00 */
+ u32 ras2_gpp_inp; /* 0xb04 */
+ u32 ras1_gpp_out; /* 0xb08 */
+ u32 ras2_gpp_out; /* 0xb0c */
+ u8 reserved_15[0xc00 - 0xa10];
+ u32 axi_cache_user_ctrl_0; /* 0xc00 */
+ u32 axi_cache_user_ctrl_1; /* 0xc04 */
+ u32 axi_cache_user_ctrl_2; /* 0xc08 */
+ u32 axi_cache_user_ctrl_3; /* 0xc0c */
+ u32 ahb_cache_user_ctrl_0; /* 0xc10 */
+ u32 ahb_cache_user_ctrl_1; /* 0xc14 */
+ u32 ahb_cache_user_ctrl_2; /* 0xc18 */
+ u32 ahb_cache_user_ctrl_3; /* 0xc1c */
+ u32 ahb_cache_user_ctrl_4; /* 0xc20 */
+ u32 ahb_cache_user_ctrl_5; /* 0xc24 */
+ u32 ahb_cache_user_ctrl_6; /* 0xc28 */
+ u32 ahb_cache_user_ctrl_7; /* 0xc2c */
+ u8 reserved_16[0x1000 - 0xc30];
+ u32 usb_test; /* 0x1000 */
+ u32 misc_cfg; /* 0x1004 */
+};
+
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1310_C3_CLKEN 0x20000000
+#define SPEAR1310_GPT1_CLKEN 0x00200000
+#define SPEAR1310_I2C_CLKEN 0x00040000
+#define SPEAR1310_SSP_CLKEN 0x00020000
+#define SPEAR1310_UART_CLKEN 0x00008000
+#define SPEAR1310_UDC_UPD_CLKEN 0x00000800
+#define SPEAR1310_UHC1_CLKEN 0x00000200
+#define SPEAR1310_GETH_CLKEN 0x00000100
+#define SPEAR1310_SD_CLKEN 0x00000040
+#define SPEAR1310_SMI_CLKEN 0x00000020
+#define SPEAR1310_FSMC_CLKEN 0x00000010
+
+/* perip1_sw_rst */
+#define SPEAR1310_C3_SWRST 0x20000000
+#define SPEAR1310_UDC_UPD_SWRST 0x00000800
+#define SPEAR1310_UHC1_SWRST 0x00000200
+
+/* perip_clk_cfg definitions */
+#define SPEAR1310_UART48M 0x00000000
+#define SPEAR1310_UARTCLKMSK 0x00000030
+
+/* gmac_clk_cfg definitions */
+#define SPEAR1310_PHYIF_MSK 0x00000070
+#define SPEAR1310_PHYIF_RMII 0x00000040
+#define SPEAR1310_PHYIF_SGMII 0x00000020
+#define SPEAR1310_PHYIF_RGMII 0x00000010
+#define SPEAR1310_PHYIF_GMII 0x00000000
+#define SPEAR1310_GMII_SYNT_ENB 0x00000008
+#define SPEAR1310_CLKSEL_OSCI3 0x00000004
+#define SPEAR1310_CLKSEL_PLL2 0x00000002
+#define SPEAR1310_CLKSEL_PAD 0x00000000
+
+/* usbphy_gen_cfg definitions */
+#define SPEAR1310_USB_PLL_LOCK 0x01000000
+#define SPEAR1310_USBUTMI_RST 0x00008000
+#define SPEAR1310_USBPHY_RST 0x00002000
+#define SPEAR1310_USBPHY_POR 0x00001000
+#define SPEAR1310_COMMON_PWDN 0x00000000
+
+/* perip_cfg definitions */
+#define SPEAR1310_MCIF_MSK 0x00000060
+#define SPEAR1310_MCIF_SD 0x00000020
+
+/* fsmc_cfg definitions */
+#define SPEAR1310_NANDCS0_NORCS4 0x00000001
+#define SPEAR1310_NANDCS0_NORCS5 0x00000002
+#define SPEAR1310_NANDCS0_NORCS6 0x00000004
+#define SPEAR1310_NANDCS0_NORCS7 0x00000008
+
+/* synth registers definitions */
+#define SPEAR1310_SYNT_CLKENB 0x80000000
+#define SPEAR1310_SYNT_FIN_FULL 0x04000000
+#define SPEAR1310_SYNT_X_1 0x00010000
+#define SPEAR1310_SYNT_X_2 0x00020000
+#define SPEAR1310_SYNT_Y_2 0x00000002
+#define SPEAR1310_SYNT_Y_5 0x00000005
+#define SPEAR1310_SYNT_Y_21 0x00000015
+
+#endif
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index 7a57379..61d30f8 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -59,6 +59,8 @@ int ehci_hcd_stop(int index)
spear3xx_usbh_stop();
#elif defined(CONFIG_ARCH_SPEAR6XX)
spear6xx_usbh_stop();
+#elif defined(CONFIG_SOC_SPEAR1310)
+ spear1310_usbh_stop();
#elif defined(CONFIG_SOC_SPEAR1340)
spear1340_usbh_stop();
#else
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 2/9] spear3xx: Add pinmux support
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 3/9] spear320plc: Correct the MACB interface Vipin Kumar
` (6 subsequent siblings)
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The pinmux layer for spear family of devices exports three APIs for the board.
<soc>_pins_default:
This routine puts all the SoC pins in a default (safe) state. This API
can be used by the respective boards to place all pins in a safe mode
before going ahead with initializing with pinmux
<soc>_select_mode:
This routine selects a particular SoC mode. It is particularly for those
SoCs which have several modes one of which can be selected. spear300 and
spear320 are such SoCs.
<soc>_enable_pins:
This routine enables the desired pins. It accepts two arguments. First
is 'ip' which indicates which controller pins are to be enabled and the
second is 'mode' in which this ip has to run eg. ip can be PMX_ETH0 and
mode can be PMX_ETH_RGMII/PMX_ETH_MII etc
<soc> spear320_configure_pin:
Configures the selected pin in GPIO, PULLDOWN/PULLUP mode
<soc>_plgpio_get:
Gets the value at a particular GPIO
<soc>_plgpio_set(u32 plgpio, u32 val)
Sets the value at a particular GPIO
Additionally, this patch also defines mdio_get_control for spear3xx which also
falls in the purview of pinmux. This is defined because spear310 and spear320
devices need to control mdio lines dynamically because these are shared. Define
the mdio_get_control routine to achieve this.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 6 +-
arch/arm/cpu/arm926ejs/spear/spear300.c | 140 +++++
arch/arm/cpu/arm926ejs/spear/spear310.c | 162 ++++++
arch/arm/cpu/arm926ejs/spear/spear320.c | 860 +++++++++++++++++++++++++++++
arch/arm/cpu/arm926ejs/spear/spear3xx.c | 87 +++
arch/arm/include/asm/arch-spear/pinmux.h | 133 +++++
arch/arm/include/asm/arch-spear/spear300.h | 27 +
arch/arm/include/asm/arch-spear/spear310.h | 13 +
arch/arm/include/asm/arch-spear/spear320.h | 426 ++++++++++++++
arch/arm/include/asm/arch-spear/spear3xx.h | 22 +
board/st/spear/spear300evb.c | 19 +
board/st/spear/spear310evb.c | 16 +
board/st/spear/spear320plc.c | 38 +-
board/st/spear/spear600evb.c | 7 +
14 files changed, 1949 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/spear300.c
create mode 100644 arch/arm/cpu/arm926ejs/spear/spear310.c
create mode 100644 arch/arm/cpu/arm926ejs/spear/spear320.c
create mode 100644 arch/arm/include/asm/arch-spear/pinmux.h
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index cf29ede..2e026ee 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -32,6 +32,9 @@ COBJS-y += timer.o
COBJS-$(CONFIG_ST_EMI) += emi.o
COBJS-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
+COBJS-$(CONFIG_SOC_SPEAR300) += spear300.o
+COBJS-$(CONFIG_SOC_SPEAR310) += spear310.o
+COBJS-$(CONFIG_SOC_SPEAR320) += spear320.o
COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
ifdef CONFIG_SPL_BUILD
@@ -39,9 +42,8 @@ COBJS-y += spl.o spl_boot.o
COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o
endif
-SRCS := $(START:.o=.S) $(COBJS-y:.o=.c)
+SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
-START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/arm926ejs/spear/spear300.c b/arch/arm/cpu/arm926ejs/spear/spear300.c
new file mode 100644
index 0000000..11c6ae7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear300.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* NAND pinmux */
+static void enable_nand_2chips_pins(void)
+{
+ pinmux_maskval(SPEAR300_RAS_REG1,
+ PMX_FIRDA_MASK,
+ 0);
+}
+
+static void enable_nand_4chips_pins(void)
+{
+ pinmux_maskval(SPEAR300_RAS_REG1,
+ PMX_FIRDA_MASK | PMX_UART0_MASK,
+ 0);
+}
+
+static void enable_nand_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_NAND_2CHIP:
+ enable_nand_2chips_pins();
+ break;
+ case PMX_NAND_4CHIP:
+ enable_nand_4chips_pins();
+ break;
+ }
+}
+
+/* SDMMC pinmux */
+static void enable_sdmmc_4bit_pins(void)
+{
+ pinmux_maskval(SPEAR300_RAS_REG1,
+ PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ 0);
+}
+
+static void enable_sdmmc_8bit_pins(void)
+{
+ pinmux_maskval(SPEAR300_RAS_REG1,
+ PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+ 0);
+}
+
+static void enable_sdmmc_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SDMMC_4BIT:
+ enable_sdmmc_4bit_pins();
+ break;
+ case PMX_SDMMC_8BIT:
+ enable_sdmmc_8bit_pins();
+ break;
+ }
+}
+
+/**
+ * spear300_select_mode
+ * @mode: SoC mode to e selected
+ */
+void spear300_select_mode(u32 mode)
+{
+ pinmux_maskval(SPEAR300_RAS_REG2,
+ SPEAR300_MODE_MSK,
+ mode);
+}
+
+/**
+ * spear300_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear300_pins_default(void)
+{
+}
+
+/**
+ * spear300_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear300_enable_pins(u32 ip, u32 mode)
+{
+ if (PMX_FSMCNAND == ip)
+ enable_nand_pins(mode);
+ else if (PMX_SDMMC == ip)
+ enable_sdmmc_pins(mode);
+ else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+ (PMX_ETH0 == ip) || (PMX_UART0 == ip))
+ spear3xx_enable_pins(ip, mode);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear310.c b/arch/arm/cpu/arm926ejs/spear/spear310.c
new file mode 100644
index 0000000..d1ab43f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear310.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * Function to dnamically set control of shared mdio lines to concerned
+ * mac controller
+ */
+void arch_get_mdio_control(const char *devname)
+{
+ u32 val;
+
+ val = readl(SPEAR310_SMII_REG);
+ val &= ~SPEAR310_SMII_PHY_MASK;
+
+ if (!strcmp(devname, "macb0"))
+ val |= (0x0 << SPEAR310_SMII_PHY_SHIFT);
+ else if (!strcmp(devname, "macb1"))
+ val |= (0x1 << SPEAR310_SMII_PHY_SHIFT);
+ else if (!strcmp(devname, "macb2"))
+ val |= (0x2 << SPEAR310_SMII_PHY_SHIFT);
+ else if (!strcmp(devname, "macb3"))
+ val |= (0x3 << SPEAR310_SMII_PHY_SHIFT);
+ else
+ printf("no such device:%s\n", devname);
+
+ writel(val, SPEAR310_SMII_REG);
+}
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* Pinmux for EMI */
+static void enable_emi_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+ 0);
+}
+
+/* Pinmux for UART1 */
+static void enable_uart1_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_FIRDA_MASK,
+ 0);
+}
+
+/* Pinmux for UART2 */
+static void enable_uart2_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_TIMER_0_1_MASK,
+ 0);
+}
+
+/* Pinmux for UART3 */
+static void enable_uart3_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_UART0_MODEM_MASK,
+ 0);
+}
+
+/* Pinmux for UART4 */
+static void enable_uart4_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_UART0_MODEM_MASK,
+ 0);
+}
+
+/* Pinmux for UART5 */
+static void enable_uart5_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_UART0_MODEM_MASK,
+ 0);
+}
+
+/* Pinmux for NAND */
+static void enable_nand_pins(void)
+{
+ pinmux_maskval(SPEAR310_FUNCENB_REG,
+ PMX_SSP_CS_MASK,
+ 0);
+}
+
+/**
+ * spear310_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear310_pins_default(void)
+{
+}
+
+/**
+ * spear310_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear310_enable_pins(u32 ip, u32 mode)
+{
+ if (PMX_FSMCNAND == ip)
+ enable_nand_pins();
+ else if (PMX_EMI == ip)
+ enable_emi_pins();
+ else if (PMX_UART1 == ip)
+ enable_uart1_pins();
+ else if (PMX_UART2 == ip)
+ enable_uart2_pins();
+ else if (PMX_UART3 == ip)
+ enable_uart3_pins();
+ else if (PMX_UART4 == ip)
+ enable_uart4_pins();
+ else if (PMX_UART5 == ip)
+ enable_uart5_pins();
+ else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+ (PMX_ETH0 == ip) || (PMX_UART0 == ip))
+ spear3xx_enable_pins(ip, mode);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear320.c b/arch/arm/cpu/arm926ejs/spear/spear320.c
new file mode 100644
index 0000000..10c921c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear320.c
@@ -0,0 +1,860 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+void arch_get_mdio_control(const char *devname)
+{
+ u32 val;
+
+ val = readl(SPEAR320_CONTROL_REG);
+
+ if (!strcmp(devname, "macb0"))
+ val &= ~(0x1 << MII_ENB_SHFT);
+ else if (!strcmp(devname, "macb1"))
+ val |= (0x1 << MII_ENB_SHFT);
+ else
+ printf("no such device:%s\n", devname);
+
+ writel(val, SPEAR320_CONTROL_REG);
+}
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* Pinmux for EMI */
+static void enable_emi_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+ PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+ PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
+ PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
+ PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
+ PMX_FSMC_EMI_PL_54_55_56_VAL |
+ PMX_FSMC_EMI_PL_58_59_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+ PMX_PL_69_MASK,
+ PMX_EMI_PL_69_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+ PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+ PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+ PMX_PL_77_78_79_MASK,
+ PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+ PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
+ PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+ PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+ PMX_PL_88_89_MASK,
+ PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
+ PMX_EMI_PL_88_89_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+ PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+ PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
+ PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL);
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ EMI_FSMC_DYNAMIC_MUX_MASK,
+ EMI_FSMC_DYNAMIC_MUX_MASK);
+}
+
+/* Pinmux for 8bit NAND interface */
+static void enable_nand8bit_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+ PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
+ PMX_PL_57_MASK | PMX_PL_58_59_MASK,
+ PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
+ PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+ PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
+ PMX_PL_65_TO_68_MASK,
+ PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
+ PMX_FSMC_PL_65_TO_68_VAL);
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ EMI_FSMC_DYNAMIC_MUX_MASK,
+ EMI_FSMC_DYNAMIC_MUX_MASK);
+}
+
+/* Pinmux for 16bit NAND interface */
+static void enable_nand16bit_pins(void)
+{
+ enable_nand8bit_pins();
+
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+ PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+ PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
+ PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+ PMX_FSMC_EMI_PL_73_VAL);
+}
+
+static void enable_nand_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_NAND_8BIT:
+ enable_nand8bit_pins();
+ break;
+ case PMX_NAND_16BIT:
+ enable_nand16bit_pins();
+ }
+}
+
+/* Pinmux for sdmmc led */
+static void enable_sdmmc_led_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_SSP_CS_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+ PMX_PL_34_MASK,
+ PMX_PWM2_PL_34_VAL);
+}
+
+static void enable_sdmmc_common_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
+ PMX_PL_48_49_MASK,
+ PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
+ PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+ PMX_PL_50_MASK,
+ PMX_SDHCI_PL_50_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_99_MASK,
+ PMX_SDHCI_PL_99_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_PL_100_101_MASK,
+ PMX_SDHCI_PL_100_101_VAL);
+}
+
+static void enable_sdmmc_cd12_pins(void)
+{
+ enable_sdmmc_common_pins();
+
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_12_MASK,
+ PMX_SDHCI_CD_PL_12_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SDHCI_CD_PORT_SEL_MASK,
+ PMX_SDHCI_CD_PORT_12_VAL);
+}
+
+static void enable_sdmmc_cd51_pins(void)
+{
+ enable_sdmmc_common_pins();
+
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+ PMX_PL_51_MASK,
+ PMX_SDHCI_CD_PL_51_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SDHCI_CD_PORT_SEL_MASK,
+ PMX_SDHCI_CD_PORT_51_VAL);
+}
+
+static void enable_sdmmc_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SDMMC_LED:
+ enable_sdmmc_led_pins();
+ break;
+ case PMX_SDMMC_CD12:
+ enable_sdmmc_cd12_pins();
+ break;
+ case PMX_SDMMC_CD51:
+ enable_sdmmc_cd51_pins();
+ break;
+ }
+}
+
+/* Pinmux for UART1 */
+static void enable_uart1simple_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+ PMX_PL_28_29_MASK,
+ PMX_UART1_PL_28_29_VAL);
+}
+
+/* Pinmux for UART1 modem */
+static void enable_uart1_modem_2to7_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+ PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
+ PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
+ PMX_UART1_ENH_PL_6_7_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_UART1_ENH_PORT_SEL_MASK,
+ PMX_UART1_ENH_PORT_3_TO_5_7_VAL);
+}
+
+static void enable_uart1_modem_31to36_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+ PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+ PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
+ PMX_PL_35_MASK | PMX_PL_36_MASK,
+ PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
+ PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+ PMX_UART1_ENH_PL_36_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_UART1_ENH_PORT_SEL_MASK,
+ PMX_UART1_ENH_PORT_32_TO_34_36_VAL);
+}
+
+static void enable_uart1_modem_34to45_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
+ PMX_SSP_CS_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+ PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
+ PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+ PMX_UART1_ENH_PL_36_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+ PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_UART1_ENH_PORT_SEL_MASK,
+ PMX_UART1_ENH_PORT_44_45_34_36_VAL);
+}
+
+static void enable_uart1_modem_80to85_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+ PMX_PL_80_TO_85_MASK,
+ PMX_UART1_ENH_PL_80_TO_85_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+ PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_UART1_ENH_PORT_SEL_MASK,
+ PMX_UART1_ENH_PORT_81_TO_85_VAL);
+}
+
+static void enable_uart1_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_UART_SIMPLE:
+ enable_uart1simple_pins();
+ break;
+ case PMX_UART_MDM_2_7:
+ enable_uart1_modem_2to7_pins();
+ break;
+ case PMX_UART_MDM_31_36:
+ enable_uart1_modem_31to36_pins();
+ break;
+ case PMX_UART_MDM_34_45:
+ enable_uart1_modem_34to45_pins();
+ break;
+ case PMX_UART_MDM_80_85:
+ enable_uart1_modem_80to85_pins();
+ break;
+ }
+}
+
+/* Pinmux for UART2 */
+static void enable_uart2_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_FIRDA_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+ PMX_PL_0_1_MASK,
+ PMX_UART2_PL_0_1_VAL);
+};
+
+/* Pinmux for SSP1 */
+static void enable_ssp1_17to20_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+ PMX_SSP1_PL_17_18_19_20_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+ PMX_PL_20_MASK,
+ PMX_SSP1_PL_17_18_19_20_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP1_PORT_SEL_MASK,
+ PMX_SSP1_PORT_17_TO_20_VAL);
+}
+
+static void enable_ssp1_36to39_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+ PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
+ PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
+ PMX_SSP1_PL_39_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP1_PORT_SEL_MASK,
+ PMX_SSP1_PORT_36_TO_39_VAL);
+}
+
+static void enable_ssp1_48to51_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_48_49_MASK,
+ PMX_SSP1_PL_48_49_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+ PMX_PL_50_51_MASK,
+ PMX_SSP1_PL_50_51_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP1_PORT_SEL_MASK,
+ PMX_SSP1_PORT_48_TO_51_VAL);
+}
+
+static void enable_ssp1_65to68_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+ PMX_PL_65_TO_68_MASK,
+ PMX_SSP1_PL_65_TO_68_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP1_PORT_SEL_MASK,
+ PMX_SSP1_PORT_65_TO_68_VAL);
+}
+
+static void enable_ssp1_94to97_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+ PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP1_PORT_SEL_MASK,
+ PMX_SSP1_PORT_94_TO_97_VAL);
+}
+
+static void enable_ssp1_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SSP_17_20:
+ enable_ssp1_17to20_pins();
+ break;
+ case PMX_SSP_36_39:
+ enable_ssp1_36to39_pins();
+ break;
+ case PMX_SSP_48_51:
+ enable_ssp1_48to51_pins();
+ break;
+ case PMX_SSP_65_68:
+ enable_ssp1_65to68_pins();
+ break;
+ case PMX_SSP_94_97:
+ enable_ssp1_94to97_pins();
+ break;
+ }
+}
+
+/* Pinmux for SSP2 */
+static void enable_ssp2_13to16_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
+ PMX_SSP2_PL_13_14_15_16_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP2_PORT_SEL_MASK,
+ PMX_SSP2_PORT_13_TO_16_VAL);
+}
+
+static void enable_ssp2_32to35_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
+ PMX_GPIO_PIN5_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+ PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
+ PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
+ PMX_SSP2_PL_35_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP2_PORT_SEL_MASK,
+ PMX_SSP2_PORT_32_TO_35_VAL);
+}
+
+static void enable_ssp2_44to47_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+ PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
+ PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP2_PORT_SEL_MASK,
+ PMX_SSP2_PORT_44_TO_47_VAL);
+}
+
+static void enable_ssp2_61to64_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+ PMX_PL_61_TO_64_MASK,
+ PMX_SSP2_PL_61_TO_64_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP2_PORT_SEL_MASK,
+ PMX_SSP2_PORT_61_TO_64_VAL);
+}
+
+static void enable_ssp2_90to93_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
+ PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_SSP2_PORT_SEL_MASK,
+ PMX_SSP2_PORT_90_TO_93_VAL);
+}
+
+static void enable_ssp2_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_SSP_13_16:
+ enable_ssp2_13to16_pins();
+ break;
+ case PMX_SSP_32_35:
+ enable_ssp2_32to35_pins();
+ break;
+ case PMX_SSP_44_47:
+ enable_ssp2_44to47_pins();
+ break;
+ case PMX_SSP_61_64:
+ enable_ssp2_61to64_pins();
+ break;
+ case PMX_SSP_90_93:
+ enable_ssp2_90to93_pins();
+ break;
+ }
+}
+
+/* Pinmux for ETH2 */
+static void enable_mii2_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+ PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+ PMX_PL_88_89_MASK,
+ PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
+ PMX_MII2_PL_88_89_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+ PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+ PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
+ PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL);
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+ (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+ MII_MDIO_MASK,
+ (MAC_MODE_MII << MAC2_MODE_SHIFT) |
+ (MAC_MODE_MII << MAC1_MODE_SHIFT) |
+ MII_MDIO_81_VAL);
+}
+
+static void enable_smii2_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_10_11_MASK,
+ PMX_SMII_PL_10_11_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+ PMX_PL_21_TO_27_MASK,
+ PMX_SMII_PL_21_TO_27_VAL);
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+ (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+ MII_MDIO_MASK,
+ (MAC_MODE_SMII << MAC2_MODE_SHIFT)
+ | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
+ | MII_MDIO_10_11_VAL);
+}
+
+static void enable_rmii2_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
+ PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+ PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
+ PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
+ PMX_RMII_PL_19_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+ PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
+ PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL);
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+ (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+ MII_MDIO_MASK,
+ (MAC_MODE_RMII << MAC2_MODE_SHIFT)
+ | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
+ | MII_MDIO_10_11_VAL);
+}
+
+static void enable_eth2_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_ETH_MII:
+ enable_mii2_pins();
+ break;
+ }
+}
+
+static void enable_eth1_eth2_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_ETH_SMII:
+ enable_smii2_pins();
+ break;
+ case PMX_ETH_RMII:
+ enable_rmii2_pins();
+ break;
+ }
+}
+
+/* Pinmux for I2C1 */
+static void enable_i2c1_8to9_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_SSP_CS_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+ PMX_PL_8_9_MASK,
+ PMX_I2C1_PL_8_9_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C1_PORT_SEL_MASK,
+ PMX_I2C1_PORT_8_9_VAL);
+}
+
+static void enable_i2c1_98to99_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_98_MASK | PMX_PL_99_MASK,
+ PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C1_PORT_SEL_MASK,
+ PMX_I2C1_PORT_98_99_VAL);
+}
+
+static void enable_i2c1_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_I2C_8_9:
+ enable_i2c1_8to9_pins();
+ break;
+ case PMX_I2C_98_99:
+ enable_i2c1_98to99_pins();
+ break;
+ }
+}
+
+/* Pinmux for I2C2 */
+static void enable_i2c2_0to1_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_FIRDA_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+ PMX_PL_0_1_MASK,
+ PMX_I2C2_PL_0_1_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C2_PORT_SEL_MASK,
+ PMX_I2C2_PORT_0_1_VAL);
+}
+
+static void enable_i2c2_2to3_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_UART0_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+ PMX_PL_2_3_MASK,
+ PMX_I2C2_PL_2_3_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C2_PORT_SEL_MASK,
+ PMX_I2C2_PORT_2_3_VAL);
+}
+
+static void enable_i2c2_19to20_pins(void)
+{
+ pinmux_maskval(SPEAR320_RASSELECT_REG,
+ PMX_MII_MASK,
+ 0);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+ PMX_PL_19_MASK,
+ PMX_I2C2_PL_19_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+ PMX_PL_20_MASK,
+ PMX_I2C2_PL_20_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C2_PORT_SEL_MASK,
+ PMX_I2C2_PORT_19_20_VAL);
+}
+
+static void enable_i2c2_75to76_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+ PMX_PL_75_76_MASK,
+ PMX_I2C2_PL_75_76_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C2_PORT_SEL_MASK,
+ PMX_I2C2_PORT_75_76_VAL);
+}
+
+static void enable_i2c2_96to97_pins(void)
+{
+ pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+ PMX_PL_96_97_MASK,
+ PMX_I2C2_PL_96_97_VAL);
+ pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+ PMX_I2C2_PORT_SEL_MASK,
+ PMX_I2C2_PORT_96_97_VAL);
+}
+
+static void enable_i2c2_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_I2C_0_1:
+ enable_i2c2_0to1_pins();
+ break;
+ case PMX_I2C_2_3:
+ enable_i2c2_2to3_pins();
+ break;
+ case PMX_I2C_19_20:
+ enable_i2c2_19to20_pins();
+ break;
+ case PMX_I2C_75_76:
+ enable_i2c2_75to76_pins();
+ break;
+ case PMX_I2C_96_97:
+ enable_i2c2_96to97_pins();
+ break;
+ }
+}
+
+/**
+ * spear320_select_mode
+ * @mode: SoC mode to e selected
+ */
+void spear320_select_mode(u32 mode)
+{
+ if (mode == SPEAR320_EXTENDED_MODE) {
+ pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+ EXT_MODE_MASK,
+ EXT_MODE_MASK);
+ } else
+ printf("deprecated: Please run device only in ext mode\n");
+}
+
+/**
+ * spear320_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode@initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear320_pins_default(void)
+{
+}
+
+/**
+ * spear320_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear320_enable_pins(u32 ip, u32 mode)
+{
+ if (PMX_UART2 == ip)
+ enable_uart2_pins();
+ else if (PMX_EMI == ip)
+ enable_emi_pins();
+ else if (PMX_FSMCNAND == ip)
+ enable_nand_pins(mode);
+ else if (PMX_SDMMC == ip)
+ enable_sdmmc_pins(mode);
+ else if (PMX_UART1 == ip)
+ enable_uart1_pins(mode);
+ else if (PMX_I2C1 == ip)
+ enable_i2c1_pins(mode);
+ else if (PMX_I2C2 == ip)
+ enable_i2c2_pins(mode);
+ else if (PMX_SSP1 == ip)
+ enable_ssp1_pins(mode);
+ else if (PMX_SSP2 == ip)
+ enable_ssp2_pins(mode);
+ else if (PMX_ETH2 == ip)
+ enable_eth2_pins(mode);
+ else if (PMX_ETH1_ETH2 == ip)
+ enable_eth1_eth2_pins(mode);
+ else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+ (PMX_ETH0 == ip) || (PMX_UART0 == ip))
+ spear3xx_enable_pins(ip, mode);
+}
+
+static void configure_gpio(u32 plgpio)
+{
+ if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+ return;
+
+ /* Set the pin to GPIO IN mode */
+ pinmux_set_bit(plgpio, SPEAR320_GPIO_EN0);
+
+ /* Select GPIO mode */
+ pinmux_set_bit(plgpio, SPEAR320_GPIO_SELECT0);
+
+ /* Select RAS from Fixed Part / RAS */
+ if (plgpio < 2) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_FIRDA_MASK, 0);
+ } else if (plgpio < 4) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_UART0_MASK, 0);
+ } else if (plgpio < 6) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_I2C_MASK, 0);
+ } else if (plgpio < 10) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_SSP_MASK, 0);
+ } else if (plgpio < 28) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_MII_MASK, 0);
+ } else if (plgpio < 29) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN0_MASK, 0);
+ } else if (plgpio < 30) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN1_MASK, 0);
+ } else if (plgpio < 31) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN2_MASK, 0);
+ } else if (plgpio < 32) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN3_MASK, 0);
+ } else if (plgpio < 33) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN4_MASK, 0);
+ } else if (plgpio < 34) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_GPIO_PIN5_MASK, 0);
+ } else if (plgpio < 37) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_SSP_CS_MASK, 0);
+ } else if (plgpio < 43) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_UART0_MODEM_MASK, 0);
+ } else if (plgpio < 51) {
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 0);
+ }
+}
+
+/**
+ * spear320_configure_pin - Configure pin on spear320 devices
+ * @plgpio: Pin Number (plgpio number)
+ * @mode: Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc
+ */
+void spear320_configure_pin(u32 plgpio, u32 mode)
+{
+ if (PMX_GPIO == mode)
+ configure_gpio(plgpio);
+}
+
+/**
+ * spear320_plgpio_get - Get the gpio input
+ * @plgpio: Pin Number (plgpio number)
+ */
+int spear320_plgpio_get(u32 plgpio)
+{
+ if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+ return -1;
+
+ /* Set the pin to GPIO IN mode */
+ pinmux_set_bit(plgpio, SPEAR320_GPIO_EN0);
+
+ return pinmux_test_bit(plgpio, SPEAR320_GPIO_IN0);
+}
+
+/**
+ * spear320_plgpio_set - Set the gpio value
+ * @plgpio: Pin Number (plgpio number)
+ */
+void spear320_plgpio_set(u32 plgpio, u32 val)
+{
+ if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+ return;
+
+ if (val & 0x1)
+ pinmux_set_bit(plgpio, SPEAR320_GPIO_OUT0);
+ else
+ pinmux_clear_bit(plgpio, SPEAR320_GPIO_OUT0);
+
+ /* Set the pin to GPIO OUT mode */
+ pinmux_clear_bit(plgpio, SPEAR320_GPIO_EN0);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
index 7a85fa9..612d237 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear3xx.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
@@ -25,6 +25,93 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
+
+/* Pinmux support for all fixed spear3xx devices */
+
+/* Pinmux for I2C0 */
+static void enable_i2c0_pins(void)
+{
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_I2C_MASK,
+ PMX_I2C_MASK);
+}
+
+/* Pinmux for SSP0 */
+static void enable_ssp0_pins(void)
+{
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_SSP_MASK,
+ PMX_SSP_MASK);
+}
+
+/* Pinmux for ETH0 */
+static void enable_eth0_pins(void)
+{
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_MII_MASK,
+ PMX_MII_MASK);
+}
+
+/* Pinmux for UART0 ext */
+static void enable_uart0_ext_pins(void)
+{
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_UART0_MODEM_MASK,
+ PMX_UART0_MODEM_MASK);
+
+}
+
+/* Pinmux for UART0 */
+static void enable_uart0_simple_pins(void)
+{
+ pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+ PMX_UART0_MASK,
+ PMX_UART0_MASK);
+}
+
+static void enable_uart0_pins(u32 mode)
+{
+ switch (mode) {
+ case PMX_UART_SIMPLE:
+ enable_uart0_simple_pins();
+ break;
+ case PMX_UART_MODEM:
+ enable_uart0_ext_pins();
+ break;
+ }
+}
+
+/**
+ * spear3xx_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip: Peripheral index
+ * @mode: Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear3xx_enable_pins(u32 ip, u32 mode)
+{
+ switch (ip) {
+ case PMX_I2C0:
+ enable_i2c0_pins();
+ break;
+ case PMX_SSP0:
+ enable_ssp0_pins();
+ break;
+ case PMX_ETH0:
+ enable_eth0_pins();
+ break;
+ case PMX_UART0:
+ enable_uart0_pins(mode);
+ break;
+ default:
+ printf("Unsupported device\n");
+ break;
+ }
+}
#if defined(CONFIG_USB_EHCI_SPEAR)
void spear3xx_usbh_stop(void)
diff --git a/arch/arm/include/asm/arch-spear/pinmux.h b/arch/arm/include/asm/arch-spear/pinmux.h
new file mode 100644
index 0000000..faa46aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/pinmux.h
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR_PINMUX_H
+#define _ASM_ARCH_SPEAR_PINMUX_H
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+static inline void pinmux_maskval(ulong reg, u32 mask, u32 val)
+{
+ u32 temp = readl((u32 *)reg);
+ temp &= ~mask;
+ temp |= val & mask;
+ writel(temp, (u32 *)reg);
+}
+
+static inline void pinmux_set_bit(int nr, unsigned long addr)
+{
+ __set_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline void pinmux_clear_bit(int nr, unsigned long addr)
+{
+ __clear_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline int pinmux_test_bit(int nr, unsigned long addr)
+{
+ return __test_bit(nr, (volatile unsigned long *)addr);
+}
+
+enum pinmux_ip {
+ PMX_UART0,
+ PMX_UART1,
+ PMX_UART2,
+ PMX_UART3,
+ PMX_UART4,
+ PMX_UART5,
+ PMX_I2C0,
+ PMX_I2C1,
+ PMX_I2C2,
+ PMX_SSP0,
+ PMX_SSP1,
+ PMX_SSP2,
+ PMX_ETH0,
+ PMX_ETH1,
+ PMX_ETH2,
+ PMX_ETH1_ETH2,
+ PMX_FSMCNAND,
+ PMX_FSMCPNOR,
+ PMX_SDMMC,
+ PMX_EMI,
+ PMX_SMI,
+};
+
+/* UART0 modem modes */
+#define PMX_UART_SIMPLE 1
+#define PMX_UART_MODEM 2
+#define PMX_UART_MDM_2_7 3
+#define PMX_UART_MDM_31_36 4
+#define PMX_UART_MDM_34_45 5
+#define PMX_UART_MDM_80_85 6
+
+/* I2C modes */
+#define PMX_I2C_8_9 1
+#define PMX_I2C_98_99 2
+#define PMX_I2C_0_1 3
+#define PMX_I2C_2_3 4
+#define PMX_I2C_19_20 5
+#define PMX_I2C_75_76 6
+#define PMX_I2C_96_97 7
+
+/* SSP modes */
+#define PMX_SSP_13_16 1
+#define PMX_SSP_17_20 2
+#define PMX_SSP_32_35 3
+#define PMX_SSP_36_39 4
+#define PMX_SSP_44_47 5
+#define PMX_SSP_48_51 6
+#define PMX_SSP_61_64 7
+#define PMX_SSP_65_68 8
+#define PMX_SSP_90_93 9
+#define PMX_SSP_94_97 10
+
+/* ETH modes */
+#define PMX_ETH_GMII 1
+#define PMX_ETH_MII 2
+#define PMX_ETH_RGMII 3
+#define PMX_ETH_RMII 4
+#define PMX_ETH_SGMII 5
+#define PMX_ETH_SMII 6
+
+/* NAND modes */
+#define PMX_NAND_8BIT 1
+#define PMX_NAND_16BIT 2
+#define PMX_NAND_2CHIP 3
+#define PMX_NAND_4CHIP 4
+
+/* SDMMC modes */
+#define PMX_SDMMC_LED 1
+#define PMX_SDMMC_CD12 2
+#define PMX_SDMMC_CD51 3
+#define PMX_SDMMC_4BIT 4
+#define PMX_SDMMC_8BIT 5
+
+/* PLGPIO modes */
+#define PMX_GPIO 1
+#define PMX_PULLUP 2
+#define PMX_PULLDOWN 3
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear300.h b/arch/arm/include/asm/arch-spear/spear300.h
index 24faaea..4bfa619 100644
--- a/arch/arm/include/asm/arch-spear/spear300.h
+++ b/arch/arm/include/asm/arch-spear/spear300.h
@@ -30,4 +30,31 @@
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
+/* RAS misc registers and respective bitmasks */
+#define CONFIG_SYS_RAS_BASE 0x99000000
+#define SPEAR300_RAS_REG1 CONFIG_SYS_RAS_BASE
+ /* Bitmaks for REG1 are in spear3xx.h */
+#define SPEAR300_RAS_REG2 (CONFIG_SYS_RAS_BASE + 0x04)
+ #define SPEAR300_MODE_MSK (0xF << 0)
+ #define SPEAR300_MODE_NAND (0x0 << 0)
+ #define SPEAR300_MODE_NOR (0x1 << 0)
+ #define SPEAR300_MODE_PHOTOFRAME (0x2 << 0)
+ #define SPEAR300_MODE_LENDIPFONE (0x3 << 0)
+ #define SPEAR300_MODE_HENDIPFONE (0x4 << 0)
+ #define SPEAR300_MODE_LENDWIFIFONE (0x5 << 0)
+ #define SPEAR300_MODE_HENDWIFIFONE (0x6 << 0)
+ #define SPEAR300_MODE_ATAPABXWI2S (0x7 << 0)
+ #define SPEAR300_MODE_ATAPABXI2S (0x8 << 0)
+ #define SPEAR300_MODE_CAM1LCDW (0xC << 0)
+ #define SPEAR300_MODE_CAMULCD (0xD << 0)
+ #define SPEAR300_MODE_CAMULCDW (0xE << 0)
+ #define SPEAR300_MODE_CAM1LCD (0xF << 0)
+
+#define SPEAR3XX_FUNC_ENB_REG SPEAR300_RAS_REG1
+
+/* externs related to pinmux */
+extern void spear300_pins_default(void);
+extern void spear300_select_mode(u32 mode);
+extern void spear300_enable_pins(u32 ip, u32 mode);
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/spear310.h b/arch/arm/include/asm/arch-spear/spear310.h
index 0f6223e..9d20237 100644
--- a/arch/arm/include/asm/arch-spear/spear310.h
+++ b/arch/arm/include/asm/arch-spear/spear310.h
@@ -37,4 +37,17 @@
#define CONFIG_SYS_MACB3_BASE 0xB1800000
#define CONFIG_SPEAR_RASBASE 0xB4000000
+/* SPEAr310 RAS misc space registers and bitmasks */
+#define SPEAR310_FUNCENB_REG (CONFIG_SPEAR_RASBASE + 0x8)
+
+#define SPEAR310_SMII_REG (CONFIG_SPEAR_RASBASE + 0xC)
+ #define SPEAR310_SMII_PHY_SHIFT 0x0
+ #define SPEAR310_SMII_PHY_MASK 0x3
+
+#define SPEAR3XX_FUNC_ENB_REG SPEAR310_FUNCENB_REG
+
+/* externs related to pinmux */
+extern void spear310_pins_default(void);
+extern void spear310_enable_pins(u32 ip, u32 mode);
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h
index 110afc3..abdcda6 100644
--- a/arch/arm/include/asm/arch-spear/spear320.h
+++ b/arch/arm/include/asm/arch-spear/spear320.h
@@ -35,4 +35,430 @@
#define CONFIG_SYS_MACB1_BASE 0xAB000000
#define CONFIG_SPEAR_RASBASE 0xB3000000
+/* SPEAr320 SoC device modes */
+#define SPEAR320_AUTO_NET_SMII_MODE (1 << 0)
+#define SPEAR320_AUTO_NET_MII_MODE (1 << 1)
+#define SPEAR320_AUTO_EXP_MODE (1 << 2)
+#define SPEAR320_SMALL_PRINTERS_MODE (1 << 3)
+#define SPEAR320_EXTENDED_MODE (1 << 4)
+
+/* SPEAr320 RAS misc space registers and bitmasks */
+#define SPEAR320_RASSELECT_REG (CONFIG_SPEAR_RASBASE + 0x000C)
+
+#define SPEAR320_CONTROL_REG (CONFIG_SPEAR_RASBASE + 0x0010)
+ #define MII_ENB_SHFT 5
+
+/* Extended mode registers and their offsets */
+#define SPEAR320_EXT_CTRL_REG (CONFIG_SPEAR_RASBASE + 0x0018)
+ #define EXT_MODE_MASK (1 << 0)
+ #define MII_MDIO_MASK (1 << 4)
+ #define MII_MDIO_10_11_VAL 0
+ #define MII_MDIO_81_VAL (1 << 4)
+ #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
+ #define MAC_MODE_MII 0
+ #define MAC_MODE_RMII 1
+ #define MAC_MODE_SMII 2
+ #define MAC_MODE_SS_SMII 3
+ #define MAC_MODE_MASK 0x3
+ #define MAC1_MODE_SHIFT 16
+ #define MAC2_MODE_SHIFT 18
+
+#define SPEAR320_GPIO_SELECT0 (CONFIG_SPEAR_RASBASE + 0x0024)
+#define SPEAR320_GPIO_OUT0 (CONFIG_SPEAR_RASBASE + 0x0034)
+#define SPEAR320_GPIO_EN0 (CONFIG_SPEAR_RASBASE + 0x0044)
+#define SPEAR320_GPIO_IN0 (CONFIG_SPEAR_RASBASE + 0x0054)
+
+#define SPEAR320_IP_SEL_PAD_0_9_REG (CONFIG_SPEAR_RASBASE + 0x00A4)
+ #define PMX_PL_0_1_MASK (0x3F << 0)
+ #define PMX_UART2_PL_0_1_VAL 0x0
+ #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
+
+ #define PMX_PL_2_3_MASK (0x3F << 6)
+ #define PMX_I2C2_PL_2_3_VAL 0x0
+ #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
+ #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
+
+ #define PMX_PL_4_5_MASK (0x3F << 12)
+ #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
+ #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
+ #define PMX_PL_5_MASK (0x7 << 15)
+ #define PMX_TOUCH_Y_PL_5_VAL 0x0
+
+ #define PMX_PL_6_7_MASK (0x3F << 18)
+ #define PMX_PL_6_MASK (0x7 << 18)
+ #define PMX_PL_7_MASK (0x7 << 21)
+ #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
+ #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
+ #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
+ #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
+
+ #define PMX_PL_8_9_MASK (0x3F << 24)
+ #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
+ #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
+ #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_10_19_REG (CONFIG_SPEAR_RASBASE + 0x00A8)
+ #define PMX_PL_10_11_MASK (0x3F << 0)
+ #define PMX_SMII_PL_10_11_VAL 0
+ #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
+
+ #define PMX_PL_12_MASK (0x7 << 6)
+ #define PMX_PWM3_PL_12_VAL 0
+ #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
+
+ #define PMX_PL_13_14_MASK (0x3F << 9)
+ #define PMX_PL_13_MASK (0x7 << 9)
+ #define PMX_PL_14_MASK (0x7 << 12)
+ #define PMX_SSP2_PL_13_14_15_16_VAL 0
+ #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
+ #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
+ #define PMX_PWM2_PL_13_VAL (0x2 << 9)
+ #define PMX_PWM1_PL_14_VAL (0x2 << 12)
+
+ #define PMX_PL_15_MASK (0x7 << 15)
+ #define PMX_PWM0_PL_15_VAL (0x2 << 15)
+ #define PMX_PL_15_16_MASK (0x3F << 15)
+ #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
+ #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
+
+ #define PMX_PL_17_18_MASK (0x3F << 21)
+ #define PMX_SSP1_PL_17_18_19_20_VAL 0
+ #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
+
+ #define PMX_PL_19_MASK (0x7 << 27)
+ #define PMX_I2C2_PL_19_VAL (0x1 << 27)
+ #define PMX_RMII_PL_19_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_20_29_REG (CONFIG_SPEAR_RASBASE + 0x00AC)
+ #define PMX_PL_20_MASK (0x7 << 0)
+ #define PMX_I2C2_PL_20_VAL (0x1 << 0)
+ #define PMX_RMII_PL_20_VAL (0x4 << 0)
+
+ #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
+ #define PMX_SMII_PL_21_TO_27_VAL 0
+ #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | \
+ (0x4 << 9) | (0x4 << 12) | \
+ (0x4 << 15) | (0x4 << 18) | \
+ (0x4 << 21))
+
+ #define PMX_PL_28_29_MASK (0x3F << 24)
+ #define PMX_PL_28_MASK (0x7 << 24)
+ #define PMX_PL_29_MASK (0x7 << 27)
+ #define PMX_UART1_PL_28_29_VAL 0
+ #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
+ #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_30_39_REG (CONFIG_SPEAR_RASBASE + 0x00B0)
+ #define PMX_PL_30_31_MASK (0x3F << 0)
+ #define PMX_CAN1_PL_30_31_VAL (0)
+ #define PMX_PL_30_MASK (0x7 << 0)
+ #define PMX_PL_31_MASK (0x7 << 3)
+ #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
+ #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
+ #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
+
+ #define PMX_PL_32_33_MASK (0x3F << 6)
+ #define PMX_CAN0_PL_32_33_VAL 0
+ #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
+ #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
+
+ #define PMX_PL_34_MASK (0x7 << 12)
+ #define PMX_PWM2_PL_34_VAL 0
+ #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
+ #define PMX_SSP2_PL_34_VAL (0x4 << 12)
+
+ #define PMX_PL_35_MASK (0x7 << 15)
+ #define PMX_I2S_REF_CLK_PL_35_VAL 0
+ #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
+ #define PMX_SSP2_PL_35_VAL (0x4 << 15)
+
+ #define PMX_PL_36_MASK (0x7 << 18)
+ #define PMX_TOUCH_X_PL_36_VAL 0
+ #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
+ #define PMX_SSP1_PL_36_VAL (0x4 << 18)
+
+ #define PMX_PL_37_38_MASK (0x3F << 21)
+ #define PMX_PWM0_1_PL_37_38_VAL 0
+ #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
+ #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
+
+ #define PMX_PL_39_MASK (0x7 << 27)
+ #define PMX_I2S_PL_39_VAL 0
+ #define PMX_UART4_PL_39_VAL (0x2 << 27)
+ #define PMX_SSP1_PL_39_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_40_49_REG (CONFIG_SPEAR_RASBASE + 0x00B4)
+ #define PMX_PL_40_MASK (0x7 << 0)
+ #define PMX_I2S_PL_40_VAL 0
+ #define PMX_UART4_PL_40_VAL (0x2 << 0)
+ #define PMX_PWM3_PL_40_VAL (0x4 << 0)
+
+ #define PMX_PL_41_42_MASK (0x3F << 3)
+ #define PMX_PL_41_MASK (0x7 << 3)
+ #define PMX_PL_42_MASK (0x7 << 6)
+ #define PMX_I2S_PL_41_42_VAL 0
+ #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
+ #define PMX_PWM2_PL_41_VAL (0x4 << 3)
+ #define PMX_PWM1_PL_42_VAL (0x4 << 6)
+
+ #define PMX_PL_43_MASK (0x7 << 9)
+ #define PMX_SDHCI_PL_43_VAL 0
+ #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
+ #define PMX_PWM0_PL_43_VAL (0x4 << 9)
+
+ #define PMX_PL_44_45_MASK (0x3F << 12)
+ #define PMX_SDHCI_PL_44_45_VAL 0
+ #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
+ #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
+
+ #define PMX_PL_46_47_MASK (0x3F << 18)
+ #define PMX_SDHCI_PL_46_47_VAL 0
+ #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
+ #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
+
+ #define PMX_PL_48_49_MASK (0x3F << 24)
+ #define PMX_SDHCI_PL_48_49_VAL 0
+ #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
+ #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_50_59_REG (CONFIG_SPEAR_RASBASE + 0x00B8)
+ #define PMX_PL_50_51_MASK (0x3F << 0)
+ #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
+ #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
+ #define PMX_PL_50_MASK (0x7 << 0)
+ #define PMX_PL_51_MASK (0x7 << 3)
+ #define PMX_SDHCI_PL_50_VAL 0
+ #define PMX_SDHCI_CD_PL_51_VAL 0
+
+ #define PMX_PL_52_53_MASK (0x3F << 6)
+ #define PMX_FSMC_PL_52_53_VAL 0
+ #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
+ #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
+
+ #define PMX_PL_54_55_56_MASK (0x1FF << 12)
+ #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | \
+ (0x2 << 18))
+
+ #define PMX_PL_57_MASK (0x7 << 21)
+ #define PMX_FSMC_PL_57_VAL 0
+ #define PMX_PWM3_PL_57_VAL (0x4 << 21)
+
+ #define PMX_PL_58_59_MASK (0x3F << 24)
+ #define PMX_PL_58_MASK (0x7 << 24)
+ #define PMX_PL_59_MASK (0x7 << 27)
+ #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
+ #define PMX_PWM2_PL_58_VAL (0x4 << 24)
+ #define PMX_PWM1_PL_59_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_60_69_REG (CONFIG_SPEAR_RASBASE + 0x00BC)
+ #define PMX_PL_60_MASK (0x7 << 0)
+ #define PMX_FSMC_PL_60_VAL 0
+ #define PMX_PWM0_PL_60_VAL (0x4 << 0)
+
+ #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
+ #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | \
+ (0x2 << 9) | (0x2 << 12))
+ #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | \
+ (0x4 << 9) | (0x4 << 12))
+
+ #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
+ #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | \
+ (0x2 << 21) | (0x2 << 24))
+ #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | \
+ (0x4 << 21) | (0x4 << 24))
+
+ #define PMX_PL_69_MASK (0x7 << 27)
+ #define PMX_CLCD_PL_69_VAL (0)
+ #define PMX_EMI_PL_69_VAL (0x2 << 27)
+ #define PMX_SPP_PL_69_VAL (0x3 << 27)
+ #define PMX_UART5_PL_69_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_70_79_REG (CONFIG_SPEAR_RASBASE + 0x00C0)
+ #define PMX_PL_70_MASK (0x7 << 0)
+ #define PMX_CLCD_PL_70_VAL (0)
+ #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
+ #define PMX_SPP_PL_70_VAL (0x3 << 0)
+ #define PMX_UART5_PL_70_VAL (0x4 << 0)
+
+ #define PMX_PL_71_72_MASK (0x3F << 3)
+ #define PMX_CLCD_PL_71_72_VAL (0)
+ #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
+ #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
+ #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
+
+ #define PMX_PL_73_MASK (0x7 << 9)
+ #define PMX_CLCD_PL_73_VAL (0)
+ #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
+ #define PMX_SPP_PL_73_VAL (0x3 << 9)
+ #define PMX_UART3_PL_73_VAL (0x4 << 9)
+
+ #define PMX_PL_74_MASK (0x7 << 12)
+ #define PMX_CLCD_PL_74_VAL (0)
+ #define PMX_EMI_PL_74_VAL (0x2 << 12)
+ #define PMX_SPP_PL_74_VAL (0x3 << 12)
+ #define PMX_UART3_PL_74_VAL (0x4 << 12)
+
+ #define PMX_PL_75_76_MASK (0x3F << 15)
+ #define PMX_CLCD_PL_75_76_VAL (0)
+ #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
+ #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
+ #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
+
+ #define PMX_PL_77_78_79_MASK (0x1FF << 21)
+ #define PMX_CLCD_PL_77_78_79_VAL (0)
+ #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | \
+ (0x2 << 27))
+ #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | \
+ (0x3 << 27))
+ #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | \
+ (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_80_89_REG (CONFIG_SPEAR_RASBASE + 0x00C4)
+ #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
+ #define PMX_CLCD_PL_80_TO_85_VAL 0
+ #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | \
+ (0x1 << 6) | (0x1 << 9) | \
+ (0x1 << 12) | (0x1 << 15))
+ #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | \
+ (0x2 << 6) | (0x2 << 9) | \
+ (0x2 << 12) | (0x2 << 15))
+ #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | \
+ (0x3 << 6) | (0x3 << 9) | \
+ (0x3 << 12) | (0x3 << 15))
+ #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | \
+ (0x4 << 6) | (0x4 << 9) | \
+ (0x4 << 12) | (0x4 << 15))
+
+ #define PMX_PL_86_87_MASK (0x3F << 18)
+ #define PMX_PL_86_MASK (0x7 << 18)
+ #define PMX_PL_87_MASK (0x7 << 21)
+ #define PMX_CLCD_PL_86_87_VAL 0
+ #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
+ #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
+ #define PMX_PWM3_PL_86_VAL (0x4 << 18)
+ #define PMX_PWM2_PL_87_VAL (0x4 << 21)
+
+ #define PMX_PL_88_89_MASK (0x3F << 24)
+ #define PMX_CLCD_PL_88_89_VAL 0
+ #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
+ #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
+ #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
+ #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_90_99_REG (CONFIG_SPEAR_RASBASE + 0x00C8)
+ #define PMX_PL_90_91_MASK (0x3F << 0)
+ #define PMX_CLCD_PL_90_91_VAL 0
+ #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
+ #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
+ #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
+ #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
+
+ #define PMX_PL_92_93_MASK (0x3F << 6)
+ #define PMX_CLCD_PL_92_93_VAL 0
+ #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
+ #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
+ #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
+ #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
+
+ #define PMX_PL_94_95_MASK (0x3F << 12)
+ #define PMX_CLCD_PL_94_95_VAL 0
+ #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
+ #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
+ #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
+ #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
+
+ #define PMX_PL_96_97_MASK (0x3F << 18)
+ #define PMX_CLCD_PL_96_97_VAL 0
+ #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
+ #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
+ #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
+ #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
+
+ #define PMX_PL_98_MASK (0x7 << 24)
+ #define PMX_CLCD_PL_98_VAL 0
+ #define PMX_I2C1_PL_98_VAL (0x2 << 24)
+ #define PMX_UART3_PL_98_VAL (0x4 << 24)
+
+ #define PMX_PL_99_MASK (0x7 << 27)
+ #define PMX_SDHCI_PL_99_VAL 0
+ #define PMX_I2C1_PL_99_VAL (0x2 << 27)
+ #define PMX_UART3_PL_99_VAL (0x4 << 27)
+
+#define SPEAR320_IP_SEL_MIX_PAD_REG (CONFIG_SPEAR_RASBASE + 0x00CC)
+ #define PMX_PL_100_101_MASK (0x3F << 0)
+ #define PMX_SDHCI_PL_100_101_VAL 0
+ #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
+
+ #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
+ #define PMX_SSP1_PORT_94_TO_97_VAL 0
+ #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
+ #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
+ #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
+ #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
+
+ #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
+ #define PMX_SSP2_PORT_90_TO_93_VAL 0
+ #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
+ #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
+ #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
+ #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
+
+ #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
+ #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
+ #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
+ #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
+ #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
+
+ #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
+ #define PMX_UART3_PORT_94_VAL 0
+ #define PMX_UART3_PORT_73_VAL (0x1 << 16)
+ #define PMX_UART3_PORT_52_VAL (0x2 << 16)
+ #define PMX_UART3_PORT_41_VAL (0x3 << 16)
+ #define PMX_UART3_PORT_15_VAL (0x4 << 16)
+ #define PMX_UART3_PORT_8_VAL (0x5 << 16)
+ #define PMX_UART3_PORT_99_VAL (0x6 << 16)
+
+ #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
+ #define PMX_UART4_PORT_92_VAL 0
+ #define PMX_UART4_PORT_71_VAL (0x1 << 19)
+ #define PMX_UART4_PORT_39_VAL (0x2 << 19)
+ #define PMX_UART4_PORT_13_VAL (0x3 << 19)
+ #define PMX_UART4_PORT_6_VAL (0x4 << 19)
+ #define PMX_UART4_PORT_101_VAL (0x5 << 19)
+
+ #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
+ #define PMX_UART5_PORT_90_VAL 0
+ #define PMX_UART5_PORT_69_VAL (0x1 << 22)
+ #define PMX_UART5_PORT_37_VAL (0x2 << 22)
+ #define PMX_UART5_PORT_4_VAL (0x3 << 22)
+
+ #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
+ #define PMX_UART6_PORT_88_VAL 0
+ #define PMX_UART6_PORT_2_VAL (0x1 << 24)
+
+ #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
+ #define PMX_I2C1_PORT_8_9_VAL 0
+ #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
+
+ #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
+ #define PMX_I2C2_PORT_96_97_VAL 0
+ #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
+ #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
+ #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
+ #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
+
+ #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
+ #define PMX_SDHCI_CD_PORT_12_VAL 0
+ #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
+
+#define SPEAR3XX_FUNC_ENB_REG SPEAR320_RASSELECT_REG
+
+/* externs related to pinmux */
+extern void spear320_pins_default(void);
+extern void spear320_select_mode(u32 mode);
+extern void spear320_enable_pins(u32 ip, u32 mode);
+extern void spear320_configure_pin(u32 plgpio, u32 mode);
+extern void spear320_plgpio_set(u32 plgpio, u32 val);
+extern int spear320_plgpio_get(u32 plgpio);
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/spear3xx.h b/arch/arm/include/asm/arch-spear/spear3xx.h
index e0a72f0..f0df4e6 100644
--- a/arch/arm/include/asm/arch-spear/spear3xx.h
+++ b/arch/arm/include/asm/arch-spear/spear3xx.h
@@ -37,4 +37,26 @@
#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
#define CONFIG_SPEAR_MISCBASE 0xFCA80000
+/* spear3xx pinmux register and related bit masks */
+#define PMX_FIRDA_MASK (1 << 14)
+#define PMX_I2C_MASK (1 << 13)
+#define PMX_SSP_CS_MASK (1 << 12)
+#define PMX_SSP_MASK (1 << 11)
+#define PMX_MII_MASK (1 << 10)
+#define PMX_GPIO_PIN0_MASK (1 << 9)
+#define PMX_GPIO_PIN1_MASK (1 << 8)
+#define PMX_GPIO_PIN2_MASK (1 << 7)
+#define PMX_GPIO_PIN3_MASK (1 << 6)
+#define PMX_GPIO_PIN4_MASK (1 << 5)
+#define PMX_GPIO_PIN5_MASK (1 << 4)
+#define PMX_UART0_MODEM_MASK (1 << 3)
+#define PMX_UART0_MASK (1 << 2)
+#define PMX_TIMER_2_3_MASK (1 << 1)
+#define PMX_TIMER_0_1_MASK (1 << 0)
+
+#define SPEAR3XX_MAX_PLGPIOS 101
+
+/* externs related to pinmux */
+extern void spear3xx_enable_pins(u32 ip, u32 mode);
+
#endif
diff --git a/board/st/spear/spear300evb.c b/board/st/spear/spear300evb.c
index 46a5922..2ea598a 100644
--- a/board/st/spear/spear300evb.c
+++ b/board/st/spear/spear300evb.c
@@ -30,11 +30,30 @@
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear300_select_mode(SPEAR300_MODE_NAND);
+
+ spear300_pins_default();
+ spear3xx_enable_pins(PMX_I2C0, 0);
+ spear3xx_enable_pins(PMX_SSP0, 0);
+ spear3xx_enable_pins(PMX_ETH0, 0);
+ spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+ spear300_enable_pins(PMX_SDMMC, PMX_SDMMC_4BIT);
+ spear300_enable_pins(PMX_FSMCNAND, PMX_NAND_2CHIP);
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
diff --git a/board/st/spear/spear310evb.c b/board/st/spear/spear310evb.c
index 4ed8f01..7f70008 100644
--- a/board/st/spear/spear310evb.c
+++ b/board/st/spear/spear310evb.c
@@ -31,11 +31,27 @@
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear310_pins_default();
+ spear3xx_enable_pins(PMX_I2C0, 0);
+ spear3xx_enable_pins(PMX_SSP0, 0);
+ spear3xx_enable_pins(PMX_ETH0, 0);
+ spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+ spear310_enable_pins(PMX_ETH1, 0);
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c
index a463998..84185a5 100644
--- a/board/st/spear/spear320plc.c
+++ b/board/st/spear/spear320plc.c
@@ -31,9 +31,8 @@
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
-
-#define PLGPIO_SEL_36 0xb3000028
-#define PLGPIO_IO_36 0xb3000038
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -41,15 +40,44 @@ static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static void spear_phy_reset(void)
{
- writel(0x10, PLGPIO_IO_36);
- writel(0x10, PLGPIO_SEL_36);
+ /* GPIO36 is used to enable oscillator */
+ spear320_configure_pin(36, PMX_GPIO);
+ spear320_plgpio_set(36, 1);
+
+ /* GPIO76 is used to reset phy */
+ spear320_configure_pin(76, PMX_GPIO);
+ spear320_plgpio_set(76, 0);
+ spear320_plgpio_set(76, 1);
}
int board_init(void)
{
spear_phy_reset();
+
+ return 0;
+}
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear320_select_mode(SPEAR320_EXTENDED_MODE);
+
+ spear320_pins_default();
+
+ spear320_enable_pins(PMX_I2C0, 0);
+ spear320_enable_pins(PMX_ETH0, 0);
+ spear320_enable_pins(PMX_SSP0, 0);
+ spear320_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+ spear320_enable_pins(PMX_ETH2, PMX_ETH_MII);
+ spear320_enable_pins(PMX_SDMMC, PMX_SDMMC_CD51);
+
+ /* GPIO61 is used for card power on */
+ spear320_configure_pin(61, PMX_GPIO);
+ spear320_plgpio_set(61, 0);
+
return 0;
}
+#endif
#if defined(CONFIG_CMD_NAND)
/*
diff --git a/board/st/spear/spear600evb.c b/board/st/spear/spear600evb.c
index 17828a3..add496b 100644
--- a/board/st/spear/spear600evb.c
+++ b/board/st/spear/spear600evb.c
@@ -35,6 +35,13 @@
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ return 0;
+}
+#endif
+
#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 03/11] spear/include: Clean up the spear include files Vipin Kumar
` (8 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The spear configuration files are split into spear6xx_evb.h and spear3xx_evb.h
with the common configurations placed in spear-common.h.
This split of configuration is not very conducive to increasing number of boards
within each architecture. With number of boards supported by spear3xx_evb.h
going up to 4, managing those boards becomes a tedious task.
This patch tries to re-split the spear configuration files hierarchically into
board files (spear600-evb.h, spear300-evb.h ...)
soc files (spear600.h, spear300.h ...)
arch files (spear6xx.h, spear3xx.h)
platform file (spear.h)
board configuration file would define the driver enabler which is required for
that respective board and would also define all board related configurations.
All other generic configurations would be defined by respective config files
(either spear3xx.h or spear300.h/spear310.h etc)
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 12 +-
arch/arm/cpu/arm926ejs/spear/spl.c | 8 +-
arch/arm/cpu/arm926ejs/spear/timer.c | 4 +-
arch/arm/include/asm/arch-spear/spr_misc.h | 4 +-
include/configs/spear-common.h | 251 -------------------------
include/configs/spear.h | 193 +++++++++++++++++++
include/configs/spear300-evb.h | 99 ++++++++++
include/configs/{spear6xx_evb.h => spear300.h} | 45 ++---
include/configs/spear310-evb.h | 130 +++++++++++++
include/configs/spear310.h | 76 ++++++++
include/configs/spear320-evb.h | 128 +++++++++++++
include/configs/spear320.h | 66 +++++++
include/configs/spear3xx.h | 50 +++++
include/configs/spear3xx_evb.h | 173 -----------------
include/configs/spear600-evb.h | 99 ++++++++++
include/configs/spear600.h | 58 ++++++
include/configs/x600.h | 2 +-
17 files changed, 928 insertions(+), 470 deletions(-)
delete mode 100644 include/configs/spear-common.h
create mode 100644 include/configs/spear.h
create mode 100644 include/configs/spear300-evb.h
rename include/configs/{spear6xx_evb.h => spear300.h} (54%)
create mode 100644 include/configs/spear310-evb.h
create mode 100644 include/configs/spear310.h
create mode 100644 include/configs/spear320-evb.h
create mode 100644 include/configs/spear320.h
create mode 100644 include/configs/spear3xx.h
delete mode 100644 include/configs/spear3xx_evb.h
create mode 100644 include/configs/spear600-evb.h
create mode 100644 include/configs/spear600.h
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index e299de3..7f29514 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -34,9 +34,9 @@ int arch_cpu_init(void)
periph1_clken = readl(&misc_p->periph1_clken);
-#if defined(CONFIG_SPEAR3XX)
+#if defined(CONFIG_ARCH_SPEAR3XX)
periph1_clken |= MISC_GPT2ENB;
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_SOC_SPEAR600)
periph1_clken |= MISC_GPT3ENB;
#endif
@@ -71,13 +71,13 @@ int arch_cpu_init(void)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
-#ifdef CONFIG_SPEAR300
+#ifdef CONFIG_SOC_SPEAR300
printf("CPU: SPEAr300\n");
-#elif defined(CONFIG_SPEAR310)
+#elif defined(CONFIG_SOC_SPEAR310)
printf("CPU: SPEAr310\n");
-#elif defined(CONFIG_SPEAR320)
+#elif defined(CONFIG_SOC_SPEAR320)
printf("CPU: SPEAr320\n");
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_SOC_SPEAR600)
printf("CPU: SPEAr600\n");
#else
#error CPU not supported in spear platform
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index 48e6efb..77fe3a9 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -203,7 +203,7 @@ static void sys_init(void)
*/
int get_socrev(void)
{
-#if defined(CONFIG_SPEAR600)
+#if defined(CONFIG_SOC_SPEAR600)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 soc_id = readl(&misc_p->soc_core_id);
u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
@@ -219,11 +219,11 @@ int get_socrev(void)
return SOC_SPEAR600_BA;
else
return SOC_SPEAR_NA;
-#elif defined(CONFIG_SPEAR300)
+#elif defined(CONFIG_SOC_SPEAR300)
return SOC_SPEAR300;
-#elif defined(CONFIG_SPEAR310)
+#elif defined(CONFIG_SOC_SPEAR310)
return SOC_SPEAR310;
-#elif defined(CONFIG_SPEAR320)
+#elif defined(CONFIG_SOC_SPEAR320)
return SOC_SPEAR320;
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index 1dc7860..25a4f62 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -46,10 +46,10 @@ int timer_init(void)
u32 synth;
/* Prescaler setting */
-#if defined(CONFIG_SPEAR3XX)
+#if defined(CONFIG_ARCH_SPEAR3XX)
writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
synth = MISC_GPT4SYNTH;
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_ARCH_SPEAR6XX)
writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
synth = MISC_GPT3SYNTH;
#else
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index 5f67a5f..b86296d 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -105,10 +105,10 @@ struct misc_regs {
#define SYNTH23 0x00020003
/* PLLx_FRQ value */
-#if defined(CONFIG_SPEAR3XX)
+#if defined(CONFIG_ARCH_SPEAR3XX)
#define FREQ_332 0xA600010C
#define FREQ_266 0x8500010C
-#elif defined(CONFIG_SPEAR600)
+#elif defined(CONFIG_ARCH_SPEAR6XX)
#define FREQ_332 0xA600010F
#define FREQ_266 0x8500010F
#endif
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
deleted file mode 100644
index 192cda1..0000000
--- a/include/configs/spear-common.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPEAR_COMMON_H
-#define _SPEAR_COMMON_H
-/*
- * Common configurations used for both spear3xx as well as spear6xx
- */
-
-/* U-boot Load Address */
-#define CONFIG_SYS_TEXT_BASE 0x00700000
-
-/* Ethernet driver configuration */
-#define CONFIG_MII
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_DW0_PHY 1
-#define CONFIG_NET_MULTI
-#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#define CONFIG_DW_AUTONEG
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
-
-/* USBD driver configuration */
-#if defined(CONFIG_SPEAR_USBTTY)
-#define CONFIG_DW_UDC
-#define CONFIG_USB_DEVICE
-#define CONFIG_USBD_HS
-#define CONFIG_USB_TTY
-
-#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
-#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
-
-#endif
-
-#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
-
-/* I2C driver configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DW_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x02
-
-#define CONFIG_I2C_CHIPADDRESS 0x50
-
-/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ 1000
-
-/* Flash configuration */
-#if defined(CONFIG_FLASH_PNOR)
-#define CONFIG_SPEAR_EMI
-#else
-#define CONFIG_ST_SMI
-#endif
-
-#if defined(CONFIG_ST_SMI)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BASE 0xF8000000
-#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
-#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
-#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_CS1_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
-
-#endif
-
-/*
- * Serial Configuration (PL011)
- * CONFIG_PL01x_PORTS is defined in specific files
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
- 57600, 115200 }
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* NAND FLASH Configuration */
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_NAND_FSMC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_QUIET_TEST
-
-/*
- * Command support defines
- */
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <config_cmd_default.h>
-
-/*
- * Default Environment Varible definitions
- */
-#if defined(CONFIG_SPEAR_USBTTY)
-#define CONFIG_BOOTDELAY -1
-#else
-#define CONFIG_BOOTDELAY 1
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * U-Boot Environment placing definitions.
- */
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#ifdef CONFIG_ST_SMI
-/*
- * Environment is in serial NOR flash
- */
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_ENV_SECT_SIZE 0x00010000
-#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
-
-#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
-
-#elif defined(CONFIG_SPEAR_EMI)
-/*
- * Environment is in parallel NOR flash
- */
-#define CONFIG_SYS_MONITOR_LEN 0x00060000
-#define CONFIG_ENV_SECT_SIZE 0x00020000
-#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
-
-#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
- "0x4C0000; bootm 0x1600000"
-#endif
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-/*
- * Environment is in NAND
- */
-
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_RANGE 0x10000
-#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
-
-#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
- "0x80000 0x4C0000; " \
- "bootm 0x1600000"
-#endif
-
-#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
- "mem=128M " \
- "root="CONFIG_FSMTDBLK \
- "rootfstype=jffs2"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):$(netdev):off " \
- "console=ttyAMA0,115200 $(othbootargs);" \
- "bootm; "
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=ttyAMA0,115200 $(othbootargs);" \
- CONFIG_BOOTCOMMAND
-
-
-#define CONFIG_ENV_SIZE 0x02000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-/* Miscellaneous configurable options */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_MISC_INIT_R
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR " "
-#define CONFIG_AUTOBOOT_PROMPT \
- "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000
-#define CONFIG_SYS_MEMTEST_END 0x04000000
-#define CONFIG_SYS_MALLOC_LEN (1024*1024)
-#define CONFIG_IDENT_STRING "-SPEAr"
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "u-boot> "
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000
-#define PHYS_SDRAM_1_MAXSIZE 0x40000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
new file mode 100644
index 0000000..3a73811
--- /dev/null
+++ b/include/configs/spear.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR_H
+#define __CONFIG_SPEAR_H
+
+#include <config_cmd_default.h>
+
+#define CONFIG_PLAT_SPEAR
+
+#define CONFIG_SYS_TEXT_BASE 0x00700000
+#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
+
+/* Timer, HZ specific defines */
+#define CONFIG_SYS_HZ 1000
+
+/* Generic configuration for Designware Ethernet */
+#if defined(CONFIG_DESIGNWARE_ETH) || defined(CONFIG_MACB)
+ #define CONFIG_MII
+ #define CONFIG_NET_MULTI
+ #define CONFIG_PHY_GIGE
+
+ #define CONFIG_CMD_NET
+ #define CONFIG_CMD_MII
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_DHCP
+#else
+ #undef CONFIG_CMD_NET
+ #undef CONFIG_CMD_NFS
+#endif
+
+/* Generic configuration for USBD driver */
+#if defined(CONFIG_DW_UDC)
+ #define CONFIG_USB_DEVICE
+ #define CONFIG_USBD_HS
+ #define CONFIG_USB_TTY
+
+#ifndef CONFIG_USBD_PRODUCT_NAME
+ #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
+#endif
+#ifndef CONFIG_USBD_MANUFACTURER
+ #define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
+#endif
+
+#endif /* CONFIG_DW_UDC */
+
+#if !defined(CONFIG_BOARD_EXTRA_ENV)
+ #define CONFIG_BOARD_EXTRA_ENV ""
+#endif
+#if !defined(CONFIG_SOC_EXTRA_ENV)
+ #define CONFIG_SOC_EXTRA_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_BOARD_EXTRA_ENV \
+ CONFIG_SOC_EXTRA_ENV \
+ "usbtty=cdc_acm\0unlock=yes\0" \
+ "autoload=n\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off " \
+ "console=ttyAMA0,115200 $(othbootargs)\0"
+
+/* Generic configuration for I2C driver */
+#if defined(CONFIG_DW_I2C)
+ #define CONFIG_HARD_I2C
+ #define CONFIG_CMD_I2C
+#endif
+
+/* Generic configuration for ST SMI driver */
+#if defined(CONFIG_ST_SMI)
+ #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
+ #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
+#endif
+
+/* Generic configuration for CFI driver */
+#if defined(CONFIG_FLASH_CFI_DRIVER)
+ #define CONFIG_SYS_FLASH_CFI
+ #define CONFIG_SYS_FLASH_QUIET_TEST
+ #define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
+/* Generic configuration for AMBA PL011 driver */
+#if defined(CONFIG_PL011_SERIAL)
+ #define CONFIG_BAUDRATE 115200
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
+ 57600, 115200 }
+#endif
+
+/* Generic configuration for FSMC NAND driver */
+#if defined(CONFIG_NAND_FSMC)
+ #define CONFIG_SYS_NAND_SELF_INIT
+ #define CONFIG_MTD_DEVICE
+ #define CONFIG_MTD_PARTITIONS
+ #define CONFIG_SYS_MAX_NAND_DEVICE 1
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
+ #define CONFIG_SYS_NAND_QUIET_TEST
+
+ #define CONFIG_CMD_NAND
+#endif
+
+/* Generic configuration for environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_GREPENV
+
+#if !defined(CONFIG_ENV_SIZE)
+ #define CONFIG_ENV_SIZE 0x02000
+#endif
+
+#if defined(CONFIG_SPEAR_USBTTY)
+ #undef CONFIG_ENV_IS_IN_FLASH
+ #undef CONFIG_ENV_IS_IN_NAND
+ #define CONFIG_ENV_IS_NOWHERE
+ #define CONFIG_PREBOOT "setenv stdout usbtty;" \
+ "setenv stderr usbtty;" \
+ "setenv stdin usbtty"
+#endif
+
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_BOOTDELAY -1
+#else
+ #define CONFIG_BOOTDELAY 1
+#endif
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "bootp; run nfsargs; run loados; run loaddtb; " \
+ "bootm 0x900000 - 0x800000"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=ttyAMA0,115200 $(othbootargs);" \
+ CONFIG_BOOTCOMMAND
+
+/* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START 0x00800000
+#define CONFIG_SYS_MEMTEST_END 0x04000000
+#define CONFIG_SYS_MALLOC_LEN (1024*1024)
+#define CONFIG_IDENT_STRING "-SPEAr"
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_PROMPT "u-boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR 0x00900000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define SDRAM_MAX_SIZE 0x40000000
+
+#endif /* __CONFIG_SPEAR_H */
diff --git a/include/configs/spear300-evb.h b/include/configs/spear300-evb.h
new file mode 100644
index 0000000..cb6d764
--- /dev/null
+++ b/include/configs/spear300-evb.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR300EVB
+#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR300
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_DW0_PHY 1
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* Designware I2C configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_I2C
+ #define CONFIG_I2C_CHIPADDRESS 0x50
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x02
+#endif
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_UDC
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* ST SMI (Serial flash) configurations */
+#define CONFIG_ST_SMI
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8070000"
+
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00060000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+
+ #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
+ "0x80000 0x4C0000; " \
+ "bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear3xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear300-evb.dtb\0"
+
+#include <configs/spear300.h>
+#endif /* __CONFIG_H */
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear300.h
similarity index 54%
rename from include/configs/spear6xx_evb.h
rename to include/configs/spear300.h
index 31b8725..1f09f71 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear300.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2009
+ * (C) Copyright 2012
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
@@ -21,39 +21,22 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SPEAR300_H
+#define __CONFIG_SPEAR300_H
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SPEAR600
+#define CONFIG_SOC_SPEAR300
-#if defined(CONFIG_usbtty)
-#define CONFIG_SPEAR_USBTTY
+/* PL011 configs */
+#if defined(CONFIG_PL011_SERIAL)
+#define CONFIG_SYS_SERIAL0 0xD0000000
+#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
#endif
-#if defined(CONFIG_nand)
-#define CONFIG_ENV_IS_IN_NAND
-#else
-#define CONFIG_ENV_IS_IN_FLASH
+/* FSMC NAND configs */
+#if defined(CONFIG_NAND_FSMC)
+#define CONFIG_SYS_NAND_BASE 0x80000000
#endif
-#include <configs/spear-common.h>
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0 0xD0000000
-#define CONFIG_SYS_SERIAL1 0xD0080000
-#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1 }
-
-/* NAND flash configuration */
-#define CONFIG_SYS_FSMC_NAND_SP
-#define CONFIG_SYS_FSMC_NAND_8BIT
-#define CONFIG_SYS_NAND_BASE 0xD2000000
-
-/* Environment Settings */
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
-
-#endif /* __CONFIG_H */
+#include <configs/spear3xx.h>
+#endif /* __CONFIG_SPEAR300_H */
diff --git a/include/configs/spear310-evb.h b/include/configs/spear310-evb.h
new file mode 100644
index 0000000..cb73ba7
--- /dev/null
+++ b/include/configs/spear310-evb.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_pnor)
+ #define CONFIG_FLASH_PNOR
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR310EVB
+#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR310
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_DW0_PHY 1
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* MACB configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_MACB
+ #define CONFIG_MACB0_PHY 0x01
+ #define CONFIG_MACB1_PHY 0x03
+ #define CONFIG_MACB2_PHY 0x05
+ #define CONFIG_MACB3_PHY 0x07
+#endif
+
+/* Designware I2C configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_I2C
+ #define CONFIG_I2C_CHIPADDRESS 0x50
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x02
+#endif
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_UDC
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Flash configurations */
+#if defined(CONFIG_FLASH_PNOR)
+ #define CONFIG_ST_EMI
+#else
+ #define CONFIG_ST_SMI
+#endif
+
+/* CFI Driver configurations */
+#if defined(CONFIG_FLASH_PNOR)
+ #define CONFIG_FLASH_CFI_DRIVER
+ #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
+#endif
+
+/* Environment Variable configs */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ #if defined(CONFIG_FLASH_PNOR)
+ /* Environment is in parallel NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8050000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8060000"
+
+ #else
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8050000"
+ #endif
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00060000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+
+ #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
+ "0x200000 0x4C0000; " \
+ "bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear3xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear310-evb.dtb\0"
+
+#include <configs/spear310.h>
+#endif /* __CONFIG_H */
diff --git a/include/configs/spear310.h b/include/configs/spear310.h
new file mode 100644
index 0000000..30984a2
--- /dev/null
+++ b/include/configs/spear310.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR310_H
+#define __CONFIG_SPEAR310_H
+
+#define CONFIG_SOC_SPEAR310
+
+/* PL011 configs */
+#if defined(CONFIG_PL011_SERIAL)
+ #define CONFIG_SYS_SERIAL0 0xD0000000
+ #define CONFIG_SYS_SERIAL1 0xB2000000
+ #define CONFIG_SYS_SERIAL2 0xB2080000
+ #define CONFIG_SYS_SERIAL3 0xB2100000
+ #define CONFIG_SYS_SERIAL4 0xB2180000
+ #define CONFIG_SYS_SERIAL5 0xB2200000
+
+ #if (CONFIG_CONS_INDEX)
+ #define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
+ #else
+ #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+ #endif
+
+ #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1, \
+ (void *)CONFIG_SYS_SERIAL2, \
+ (void *)CONFIG_SYS_SERIAL3, \
+ (void *)CONFIG_SYS_SERIAL4, \
+ (void *)CONFIG_SYS_SERIAL5 }
+#endif
+
+/* CFI driver (Parallel flash) configs */
+#if defined(CONFIG_FLASH_CFI_DRIVER)
+ #define CONFIG_SYS_FLASH_PROTECTION
+ #define CONFIG_SYS_FLASH_BASE 0x50000000
+ #define CONFIG_SYS_CS1_FLASH_BASE 0x60000000
+ #define CONFIG_SYS_CS2_FLASH_BASE 0x70000000
+ #define CONFIG_SYS_CS3_FLASH_BASE 0x80000000
+ #define CONFIG_SYS_CS4_FLASH_BASE 0x90000000
+ #define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_CS1_FLASH_BASE, \
+ CONFIG_SYS_CS2_FLASH_BASE, \
+ CONFIG_SYS_CS3_FLASH_BASE, \
+ CONFIG_SYS_CS4_FLASH_BASE, \
+ CONFIG_SYS_CS5_FLASH_BASE }
+ #define CONFIG_SYS_MAX_FLASH_BANKS 6
+#endif
+
+/* FSMC NAND configs */
+#if defined(CONFIG_NAND_FSMC)
+ #define CONFIG_SYS_NAND_BASE 0x40000000
+#endif
+
+#include <configs/spear3xx.h>
+#endif /* __CONFIG_SPEAR310_H */
diff --git a/include/configs/spear320-evb.h b/include/configs/spear320-evb.h
new file mode 100644
index 0000000..a054970
--- /dev/null
+++ b/include/configs/spear320-evb.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_pnor)
+ #define CONFIG_FLASH_PNOR
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR320EVB
+#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR320
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_DW0_PHY 1
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* MACB configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_MACB
+ #define CONFIG_MACB0_PHY 0x01
+ #define CONFIG_MACB1_PHY 0x02
+#endif
+
+/* Designware I2C configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_I2C
+ #define CONFIG_I2C_CHIPADDRESS 0x50
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x02
+#endif
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_UDC
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Flash configurations */
+#if defined(CONFIG_FLASH_PNOR)
+ #define CONFIG_ST_EMI
+#else
+ #define CONFIG_ST_SMI
+#endif
+
+/* CFI Driver configurations */
+#if defined(CONFIG_FLASH_PNOR)
+ #define CONFIG_FLASH_CFI_DRIVER
+ #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
+#endif
+
+/* Environment Variable configs */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ #if defined(CONFIG_FLASH_PNOR)
+ /* Environment is in parallel NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8040000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8050000"
+
+ #else
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8070000"
+ #endif
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00060000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+
+ #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
+ "0x200000 0x4C0000; " \
+ "bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear3xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear320-evb.dtb\0"
+
+#include <configs/spear320.h>
+#endif /* __CONFIG_H */
diff --git a/include/configs/spear320.h b/include/configs/spear320.h
new file mode 100644
index 0000000..bafcb9a
--- /dev/null
+++ b/include/configs/spear320.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR320_H
+#define __CONFIG_SPEAR320_H
+
+#define CONFIG_SOC_SPEAR320
+
+/* PL011 configs */
+#if defined(CONFIG_PL011_SERIAL)
+ #define CONFIG_SYS_SERIAL0 0xD0000000
+ #define CONFIG_SYS_SERIAL1 0xA3000000
+ #define CONFIG_SYS_SERIAL2 0xA4000000
+
+ #if (CONFIG_CONS_INDEX)
+ #define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
+ #else
+ #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+ #endif
+
+ #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1, \
+ (void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+/* CFI driver (Parallel flash) configs */
+#if defined(CONFIG_FLASH_CFI_DRIVER)
+ #define CONFIG_SYS_FLASH_PROTECTION
+ #define CONFIG_SYS_FLASH_BASE 0x44000000
+ #define CONFIG_SYS_CS1_FLASH_BASE 0x45000000
+ #define CONFIG_SYS_CS2_FLASH_BASE 0x46000000
+ #define CONFIG_SYS_CS3_FLASH_BASE 0x47000000
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_CS1_FLASH_BASE, \
+ CONFIG_SYS_CS2_FLASH_BASE, \
+ CONFIG_SYS_CS3_FLASH_BASE }
+ #define CONFIG_SYS_MAX_FLASH_BANKS 4
+#endif
+
+/* FSMC NAND configs */
+#if defined(CONFIG_NAND_FSMC)
+ #define CONFIG_SYS_NAND_BASE 0x50000000
+#endif
+
+#include <configs/spear3xx.h>
+#endif /* __CONFIG_SPEAR320_H */
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
new file mode 100644
index 0000000..e89e9c2
--- /dev/null
+++ b/include/configs/spear3xx.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR3XX_H
+#define __CONFIG_SPEAR3XX_H
+
+#define CONFIG_ARCH_SPEAR3XX
+
+/* Designware Ethernet configurations */
+#if defined(CONFIG_DESIGNWARE_ETH)
+ #define CONFIG_DW_ALTDESCRIPTOR
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#if defined(CONFIG_ST_SMI)
+ #define CONFIG_SYS_MAX_FLASH_BANKS 2
+ #define CONFIG_SYS_FLASH_BASE 0xF8000000
+ #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
+ #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
+ #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_CS1_FLASH_BASE}
+ #define CONFIG_SYS_MAX_FLASH_SECT 128
+#endif
+
+/* Internal memory address for spear3xx */
+#define CONFIG_SYS_INIT_SP_ADDR (0xD2800000 + 0x2000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#include <configs/spear.h>
+#endif /* __CONFIG_SPEAR3XX_H */
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
deleted file mode 100644
index 3cd56dc..0000000
--- a/include/configs/spear3xx_evb.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#if defined(CONFIG_spear300)
-#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR300
-#elif defined(CONFIG_spear310)
-#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR310
-#elif defined(CONFIG_spear320)
-#define CONFIG_SPEAR3XX
-#define CONFIG_SPEAR320
-#endif
-
-#if defined(CONFIG_usbtty)
-#define CONFIG_SPEAR_USBTTY
-#endif
-
-#if defined(CONFIG_nand)
-#define CONFIG_ENV_IS_IN_NAND
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#include <configs/spear-common.h>
-
-/* Ethernet driver configuration */
-#define CONFIG_DW_ALTDESCRIPTOR
-
-#if defined(CONFIG_SPEAR310)
-#define CONFIG_MACB
-#define CONFIG_MACB0_PHY 0x01
-#define CONFIG_MACB1_PHY 0x03
-#define CONFIG_MACB2_PHY 0x05
-#define CONFIG_MACB3_PHY 0x07
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_MACB
-#define CONFIG_MACB0_PHY 0x01
-
-#endif
-
-/* Serial Configuration (PL011) */
-#define CONFIG_SYS_SERIAL0 0xD0000000
-
-#if defined(CONFIG_SPEAR300)
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
-
-#elif defined(CONFIG_SPEAR310)
-
-#if (CONFIG_CONS_INDEX)
-#undef CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
-#endif
-
-#define CONFIG_SYS_SERIAL1 0xB2000000
-#define CONFIG_SYS_SERIAL2 0xB2080000
-#define CONFIG_SYS_SERIAL3 0xB2100000
-#define CONFIG_SYS_SERIAL4 0xB2180000
-#define CONFIG_SYS_SERIAL5 0xB2200000
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1, \
- (void *)CONFIG_SYS_SERIAL2, \
- (void *)CONFIG_SYS_SERIAL3, \
- (void *)CONFIG_SYS_SERIAL4, \
- (void *)CONFIG_SYS_SERIAL5 }
-#elif defined(CONFIG_SPEAR320)
-
-#if (CONFIG_CONS_INDEX)
-#undef CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
-#endif
-
-#define CONFIG_SYS_SERIAL1 0xA3000000
-#define CONFIG_SYS_SERIAL2 0xA4000000
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1, \
- (void *)CONFIG_SYS_SERIAL2 }
-#endif
-
-#if defined(CONFIG_SPEAR_EMI)
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#if defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_BASE 0x50000000
-#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000
-#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000
-#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000
-#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000
-#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_CS1_FLASH_BASE, \
- CONFIG_SYS_CS2_FLASH_BASE, \
- CONFIG_SYS_CS3_FLASH_BASE, \
- CONFIG_SYS_CS4_FLASH_BASE, \
- CONFIG_SYS_CS5_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 6
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_BASE 0x44000000
-#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000
-#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000
-#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_CS1_FLASH_BASE, \
- CONFIG_SYS_CS2_FLASH_BASE, \
- CONFIG_SYS_CS3_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 4
-
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
-#define CONFIG_SYS_FLASH_QUIET_TEST
-
-#endif
-
-/* NAND flash configuration */
-#define CONFIG_SYS_FSMC_NAND_SP
-#define CONFIG_SYS_FSMC_NAND_8BIT
-
-#if defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_NAND_BASE 0x80000000
-
-#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_NAND_BASE 0x40000000
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_NAND_BASE 0x50000000
-
-#endif
-
-/* Environment Settings */
-#if defined(CONFIG_SPEAR300)
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
-
-#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
-#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0"
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \
- CONFIG_EXTRA_ENV_UNLOCK
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/spear600-evb.h b/include/configs/spear600-evb.h
new file mode 100644
index 0000000..5fe326a
--- /dev/null
+++ b/include/configs/spear600-evb.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR600EVB
+#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR600
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_DW0_PHY 1
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* Designware I2C configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_I2C
+ #define CONFIG_I2C_CHIPADDRESS 0x50
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x02
+#endif
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_UDC
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* ST SMI (Serial flash) configurations */
+#define CONFIG_ST_SMI
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
+ #define CONFIG_BOOTCOMMAND "bootm 0xF8060000"
+
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00060000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+
+ #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
+ "0x80000 0x4C0000; " \
+ "bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear600_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear600-evb.dtb\0"
+
+#include <configs/spear600.h>
+#endif
diff --git a/include/configs/spear600.h b/include/configs/spear600.h
new file mode 100644
index 0000000..e64f26d
--- /dev/null
+++ b/include/configs/spear600.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR600_H
+#define __CONFIG_SPEAR600_H
+
+#define CONFIG_SOC_SPEAR600
+#define CONFIG_ARCH_SPEAR6XX
+
+/* PL011 configs */
+#if defined(CONFIG_PL011_SERIAL)
+#define CONFIG_SYS_SERIAL0 0xD0000000
+#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
+#endif
+
+/* FSMC NAND configs */
+#if defined(CONFIG_NAND_FSMC)
+#define CONFIG_SYS_NAND_BASE 0xD2000000
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#if defined(CONFIG_ST_SMI)
+ #define CONFIG_SYS_MAX_FLASH_BANKS 2
+ #define CONFIG_SYS_FLASH_BASE 0xF8000000
+ #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
+ #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
+ #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_CS1_FLASH_BASE}
+ #define CONFIG_SYS_MAX_FLASH_SECT 128
+#endif
+
+/* Internal memory address for spear3xx */
+#define CONFIG_SYS_INIT_SP_ADDR (0xD2800000 + 0x2000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#include <configs/spear.h>
+#endif /* __CONFIG_SPEAR600_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 3082aaa..e15e36b 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -30,7 +30,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SPEAR600 /* SPEAr600 SoC */
+#define CONFIG_SOC_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
#include <asm/arch/hardware.h>
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 03/19] mtd/st_smi: Avoid issuing multiple WE commands
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 02/19] mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 04/19] mtd/st_smi: Write to flash in a tight loop Vipin Kumar
` (14 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
At the start of an smi_write, if the destination address is page aligned, the
Write Enable command is getting issued twice. This patch fixes it by keeping a
flag.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/mtd/st_smi.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index e2d1cf9..1b9ff0e 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -374,7 +374,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
u8 *src_addr8 = (u8 *)src_addr;
u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i;
+ int i, issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -394,19 +394,16 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
}
writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
-
- if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
- return -EBUSY;
+ issue_we = 1;
/* Set SMI in Hardware Mode */
writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
- if (smi_write_enable(banknum))
- return -EIO;
-
/* Perform the write command */
for (i = 0; i < length; i += 4) {
- if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+ if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ issue_we = 0;
+
if (smi_wait_till_ready(banknum,
CONFIG_SYS_FLASH_WRITE_TOUT))
return -EBUSY;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 3/7] spear1340evb: Add support for evb machine
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 2/7] spear1310: Add support for spear1310 SoC Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 4/7] spear1310evb: " Vipin Kumar
` (3 subsequent siblings)
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
MAINTAINERS | 1 +
board/st/spear13xx/Makefile | 50 ++++++++++++++
board/st/spear13xx/config.mk | 26 ++++++++
board/st/spear13xx/spear1340evb.c | 94 +++++++++++++++++++++++++++
board/st/spear13xx/spear13xx_common.c | 49 ++++++++++++++
boards.cfg | 3 +
include/configs/spear1340-evb.h | 119 ++++++++++++++++++++++++++++++++++
include/configs/spear1340.h | 30 +++++++++
include/configs/spear13xx.h | 72 ++++++++++++++++++++
9 files changed, 444 insertions(+)
create mode 100644 board/st/spear13xx/Makefile
create mode 100644 board/st/spear13xx/config.mk
create mode 100644 board/st/spear13xx/spear1340evb.c
create mode 100644 board/st/spear13xx/spear13xx_common.c
create mode 100644 include/configs/spear1340-evb.h
create mode 100644 include/configs/spear1340.h
create mode 100644 include/configs/spear13xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 18e9b6c..fe74c6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -747,6 +747,7 @@ Vipin Kumar <vipin.kumar@st.com>
spear320 ARM926EJS (spear320 Soc)
spear320-hmi ARM926EJS (spear320 SoC)
spear600 ARM926EJS (spear600 Soc)
+ spear1340-evb ARM ARMV7 (spear1340 SoC)
Sergey Lapin <slapin@ossfans.org>
diff --git a/board/st/spear13xx/Makefile b/board/st/spear13xx/Makefile
new file mode 100644
index 0000000..73a9450
--- /dev/null
+++ b/board/st/spear13xx/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+SOBJS-y :=
+COBJS-y :=
+
+COBJS-y += spear13xx_common.o
+COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spear1340evb.o
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/st/spear13xx/config.mk b/board/st/spear13xx/config.mk
new file mode 100644
index 0000000..9d5de65
--- /dev/null
+++ b/board/st/spear13xx/config.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2012 ST Microelectronics
+# Vipin Kumar <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot.img
+endif
diff --git a/board/st/spear13xx/spear1340evb.c b/board/st/spear13xx/spear1340evb.c
new file mode 100644
index 0000000..57efe8a
--- /dev/null
+++ b/board/st/spear13xx/spear1340evb.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <nand.h>
+#include <phy.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+
+#if defined(CONFIG_CMD_NAND)
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear1340_pins_default();
+
+ spear1340_enable_pins(PMX_FSMCNAND, PMX_NAND_8BIT);
+ spear1340_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+ spear1340_enable_pins(PMX_I2C0, 0);
+ spear1340_enable_pins(PMX_SSP0, PMX_SSP_CS0);
+ spear1340_enable_pins(PMX_SSP0, PMX_SSP_CS1);
+ spear1340_enable_pins(PMX_SMI, 0);
+ spear1340_enable_pins(PMX_SDMMC, 0);
+ spear1340_enable_pins(PMX_ETH0, PMX_ETH_RGMII);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+/*
+ * board_nand_init - Board specific NAND initialization
+ */
+void board_nand_init(void)
+{
+#if defined(CONFIG_NAND_FSMC)
+ fsmc_nand_init(&nand_chip[0]);
+#endif
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+ u32 interface = PHY_INTERFACE_MODE_RMII;
+#if defined(CONFIG_DESIGNWARE_ETH)
+#if defined(CONFIG_DW_AUTONEG)
+ interface = PHY_INTERFACE_MODE_RGMII;
+#endif
+ if (designware_initialize(0, CONFIG_SYS_ETH_BASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
+
+#if defined(CONFIG_CMD_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+#if defined(CONFIG_SPEAR_SDHCI)
+ if (spear_sdhci_init(CONFIG_SYS_MMC_BASE, 24000000, 6000000, 0) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/st/spear13xx/spear13xx_common.c b/board/st/spear13xx/spear13xx_common.c
new file mode 100644
index 0000000..b14e3fb
--- /dev/null
+++ b/board/st/spear13xx/spear13xx_common.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void lowlevel_init(void)
+{
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_MACH_SPEAR1340EVB
+ printf("BOARD: SPEAr1340-EVB\n");
+#else
+#error BOARD not supported
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* Store complete RAM size and return */
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
+
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 0375e9e..0214abe 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -269,6 +269,9 @@ origen arm armv7 origen samsung exynos
s5pc210_universal arm armv7 universal_c210 samsung exynos
smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
+spear1340 arm armv7 spear13xx st spear13xx spear1340-evb:spear1340
+spear1340_nand arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,nand
+spear1340_usbtty arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,usbtty
trats arm armv7 trats samsung exynos
harmony arm armv7:arm720t harmony nvidia tegra20
seaboard arm armv7:arm720t seaboard nvidia tegra20
diff --git a/include/configs/spear1340-evb.h b/include/configs/spear1340-evb.h
new file mode 100644
index 0000000..05ae8fb
--- /dev/null
+++ b/include/configs/spear1340-evb.h
@@ -0,0 +1,119 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR1340EVB
+#define CONFIG_MACH_TYPE 3394
+
+/* Timer configurations */
+#define CONFIG_ARMV7_CA9LTIMER
+#define CONFIG_ARMV7_LTMR_CLK 250000000
+
+/* AMBA PL022 SSP-SPI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_PL022_SPI
+ #define CONFIG_SPI_FLASH
+#endif
+
+/* ARASAN SD MMC configuration */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_SPEAR_SDHCI
+#endif
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_PHY_GIGE
+ #define CONFIG_DW0_PHY 1
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_OTG
+ #define CONFIG_DW_OTG_PHYINIT
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#define CONFIG_ST_SMI
+
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Environment Variable configs */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xE6060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock6 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xe6080000 - 0xe6070000"
+
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00400000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock12 "
+
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x500000 0x020000; " \
+ "nand read.jffs2 0x900000 0x600000 0x500000; " \
+ "bootm 0x900000 - 0x800000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear13xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear1340-evb.dtb\0"
+
+#include <configs/spear1340.h>
+#endif
diff --git a/include/configs/spear1340.h b/include/configs/spear1340.h
new file mode 100644
index 0000000..8cf3d1a
--- /dev/null
+++ b/include/configs/spear1340.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR1340_H
+#define __CONFIG_SPEAR1340_H
+
+#define CONFIG_SOC_SPEAR1340
+
+#include <configs/spear13xx.h>
+#endif /* __CONFIG_SPEAR1340_H */
diff --git a/include/configs/spear13xx.h b/include/configs/spear13xx.h
new file mode 100644
index 0000000..fc40e14
--- /dev/null
+++ b/include/configs/spear13xx.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR13XX_H
+#define __CONFIG_SPEAR13XX_H
+
+#define CONFIG_ARCH_SPEAR13XX
+
+/* AMBA PL022 SPI configurations */
+#if defined(CONFIG_PL022_SPI)
+ #define CONFIG_SYS_SPI_CLK 83000000
+#endif
+
+/* Designware Ethernet configurations */
+#if defined(CONFIG_DESIGNWARE_ETH)
+ #define CONFIG_DW_ALTDESCRIPTOR
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#if defined(CONFIG_ST_SMI)
+ #define CONFIG_SYS_MAX_FLASH_BANKS 2
+ #define CONFIG_SYS_FLASH_BASE 0xE6000000
+ #define CONFIG_SYS_CS1_FLASH_BASE 0xE7000000
+ #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
+ #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_CS1_FLASH_BASE}
+ #define CONFIG_SYS_MAX_FLASH_SECT 128
+#endif
+
+/* PL011 UART configurations */
+#if defined(CONFIG_PL011_SERIAL)
+ #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
+ #define CONFIG_SYS_SERIAL0 0xE0000000
+ #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
+
+#endif
+
+/* FSMC NAND UART configurations */
+#if defined(CONFIG_NAND_FSMC)
+ #define CONFIG_SYS_NAND_BASE 0xB0800000
+#endif
+
+/* Timer configurations */
+#if defined(CONFIG_ARMV7_CA9LTIMER)
+#endif
+
+/* Internal memory address for spear3xx */
+#define CONFIG_SYS_INIT_SP_ADDR (0xB3800000 + 0x8000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#include <configs/spear.h>
+#endif /* __CONFIG_SPEAR13XX_H */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 3/9] spear320plc: Correct the MACB interface
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 2/9] spear3xx: Add pinmux support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 4/9] spear/configs: Modify several configurations Vipin Kumar
` (5 subsequent siblings)
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
---
board/st/spear/spear320plc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c
index 84185a5..5a79eb6 100644
--- a/board/st/spear/spear320plc.c
+++ b/board/st/spear/spear320plc.c
@@ -116,8 +116,8 @@ int board_eth_init(bd_t *bis)
ret++;
#endif
#if defined(CONFIG_MACB)
- if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
- CONFIG_MACB0_PHY) >= 0)
+ if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+ CONFIG_MACB1_PHY) >= 0)
ret++;
#endif
return ret;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 03/11] spear/include: Clean up the spear include files
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 04/11] spear/board: Cleanup spear related board files Vipin Kumar
` (7 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
This patch targets a few cleanup actions in include files
- Split hardware.h into soc and arch base addresses
Splits the files hierarchically into architecture and soc specific
- Drop the spr_ prefix from the arch header names
- Remove extra header files
- Use only MISC_ as a prefix for misc register address bits
- Add protection against multiple inclusions
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 2 +-
arch/arm/cpu/arm926ejs/spear/reset.c | 2 +-
arch/arm/cpu/arm926ejs/spear/spear600.c | 4 +-
arch/arm/cpu/arm926ejs/spear/spl.c | 6 +-
arch/arm/cpu/arm926ejs/spear/spl_boot.c | 5 +-
arch/arm/cpu/arm926ejs/spear/timer.c | 4 +-
arch/arm/include/asm/arch-spear/clk.h | 5 ++
.../include/asm/arch-spear/{spr_emi.h => emi.h} | 8 +--
.../asm/arch-spear/{spr_defs.h => generic.h} | 15 +----
.../include/asm/arch-spear/{spr_gpt.h => gpt.h} | 4 +-
arch/arm/include/asm/arch-spear/hardware.h | 78 ++++------------------
.../include/asm/arch-spear/{spr_misc.h => misc.h} | 4 +-
.../asm/arch-spear/{spr_ssp.h => spear300.h} | 30 +++------
arch/arm/include/asm/arch-spear/spear310.h | 40 +++++++++++
arch/arm/include/asm/arch-spear/spear320.h | 38 +++++++++++
arch/arm/include/asm/arch-spear/spear3xx.h | 40 +++++++++++
arch/arm/include/asm/arch-spear/spear600.h | 45 +++++++++++++
.../asm/arch-spear/{spr_syscntl.h => syscntl.h} | 0
board/spear/common/spr_misc.c | 3 +-
board/spear/spear300/spear300.c | 4 +-
board/spear/spear310/spear310.c | 4 +-
board/spear/spear320/spear320.c | 4 +-
board/spear/spear600/spear600.c | 4 +-
23 files changed, 219 insertions(+), 130 deletions(-)
rename arch/arm/include/asm/arch-spear/{spr_emi.h => emi.h} (94%)
rename arch/arm/include/asm/arch-spear/{spr_defs.h => generic.h} (88%)
rename arch/arm/include/asm/arch-spear/{spr_gpt.h => gpt.h} (97%)
rename arch/arm/include/asm/arch-spear/{spr_misc.h => misc.h} (99%)
rename arch/arm/include/asm/arch-spear/{spr_ssp.h => spear300.h} (64%)
create mode 100644 arch/arm/include/asm/arch-spear/spear310.h
create mode 100644 arch/arm/include/asm/arch-spear/spear320.h
create mode 100644 arch/arm/include/asm/arch-spear/spear3xx.h
create mode 100644 arch/arm/include/asm/arch-spear/spear600.h
rename arch/arm/include/asm/arch-spear/{spr_syscntl.h => syscntl.h} (100%)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 7f29514..1301608 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/misc.h>
int arch_cpu_init(void)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c
index 73ad86d..cbefc50 100644
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ b/arch/arm/cpu/arm926ejs/spear/reset.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
+#include <asm/arch/syscntl.h>
void reset_cpu(ulong ignored)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
index ff52131..f4ec10a 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -25,8 +25,8 @@
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_defs.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/generic.h>
#define FALSE 0
#define TRUE (!FALSE)
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index 77fe3a9..c0e01ea 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -27,9 +27,9 @@
#include <version.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_syscntl.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/syscntl.h>
inline void hang(void)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
index f2f9a49..c67774d 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -26,9 +26,10 @@
#include <common.h>
#include <image.h>
#include <linux/compiler.h>
-#include <asm/io.h>
-#include <asm/arch/spr_defs.h>
#include <linux/mtd/st_smi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
static const char kernel_name[] = "Linux";
static const char loader_name[] = "U-Boot";
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index 25a4f62..af4660a 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -24,8 +24,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/gpt.h>
+#include <asm/arch/misc.h>
#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h
index a45ec18..cdfbbec 100644
--- a/arch/arm/include/asm/arch-spear/clk.h
+++ b/arch/arm/include/asm/arch-spear/clk.h
@@ -21,7 +21,12 @@
* MA 02111-1307 USA
*/
+#ifndef ASM_ARCH_SPEAR_CLK_H
+#define ASM_ARCH_SPEAR_CLK_H
+
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return 83000000;
}
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/emi.h
similarity index 94%
rename from arch/arm/include/asm/arch-spear/spr_emi.h
rename to arch/arm/include/asm/arch-spear/emi.h
index c1f1c2a..bef15e9 100644
--- a/arch/arm/include/asm/arch-spear/spr_emi.h
+++ b/arch/arm/include/asm/arch-spear/emi.h
@@ -21,10 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef __SPEAR_EMI_H__
-#define __SPEAR_EMI_H__
-
-#ifdef CONFIG_SPEAR_EMI
+#ifndef ASM_ARCH_SPEAR_EMI_H
+#define ASM_ARCH_SPEAR_EMI_H
struct emi_bank_regs {
u32 tap;
@@ -50,5 +48,3 @@ struct emi_regs {
#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/generic.h
similarity index 88%
rename from arch/arm/include/asm/arch-spear/spr_defs.h
rename to arch/arm/include/asm/arch-spear/generic.h
index 71d64a1..062571c 100644
--- a/arch/arm/include/asm/arch-spear/spr_defs.h
+++ b/arch/arm/include/asm/arch-spear/generic.h
@@ -21,15 +21,13 @@
* MA 02111-1307 USA
*/
-#ifndef __SPR_DEFS_H__
-#define __SPR_DEFS_H__
+#ifndef ASM_ARCH_SPEAR_GENERIC_H
+#define ASM_ARCH_SPEAR_GENERIC_H
-extern int spear_board_init(ulong);
+/* Routines exported from baord */
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
-void plat_ddr_init(void);
-void soc_init(void);
void spear_late_init(void);
void plat_late_init(void);
@@ -45,13 +43,6 @@ int mmc_boot_selected(void);
extern u32 mpmc_conf_vals[];
-struct chip_data {
- int cpufreq;
- int dramfreq;
- int dramtype;
- uchar version[32];
-};
-
/* HW mac id in i2c memory definitions */
#define MAGIC_OFF 0x0
#define MAGIC_LEN 0x2
diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/gpt.h
similarity index 97%
rename from arch/arm/include/asm/arch-spear/spr_gpt.h
rename to arch/arm/include/asm/arch-spear/gpt.h
index d95ba52..b4c618d 100644
--- a/arch/arm/include/asm/arch-spear/spr_gpt.h
+++ b/arch/arm/include/asm/arch-spear/gpt.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef _SPR_GPT_H
-#define _SPR_GPT_H
+#ifndef ASM_ARCH_SPEAR_GPT_H
+#define ASM_ARCH_SPEAR_GPT_H
struct gpt_regs {
u8 reserved[0x80];
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index 8150911..0b018bd 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -21,71 +21,17 @@
* MA 02111-1307 USA
*/
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define CONFIG_SYS_USBD_BASE 0xE1100000
-#define CONFIG_SYS_PLUG_BASE 0xE1200000
-#define CONFIG_SYS_FIFO_BASE 0xE1000800
-#define CONFIG_SYS_SMI_BASE 0xFC000000
-#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
-#define CONFIG_SPEAR_TIMERBASE 0xFC800000
-#define CONFIG_SPEAR_MISCBASE 0xFCA80000
-#define CONFIG_SPEAR_ETHBASE 0xE0800000
-#define CONFIG_SPEAR_MPMCBASE 0xFC600000
-#define CONFIG_SSP1_BASE 0xD0100000
-#define CONFIG_SSP2_BASE 0xD0180000
-#define CONFIG_SSP3_BASE 0xD8180000
-#define CONFIG_GPIO_BASE 0xD8100000
-
-#define CONFIG_SYS_NAND_CLE (1 << 16)
-#define CONFIG_SYS_NAND_ALE (1 << 17)
-
-#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE 0xD0200000
-#define CONFIG_SYS_FSMC_BASE 0xD1800000
-#define CONFIG_FSMC_NAND_BASE 0xD2000000
-
-#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000
-#define CONFIG_SPEAR_BOOTSTRAPSHFT 16
-#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB
-#define CONFIG_SPEAR_ONLYSNORBOOT 0xA
-#define CONFIG_SPEAR_NORNANDBOOT 0xB
-#define CONFIG_SPEAR_NORNAND8BOOT 0x8
-#define CONFIG_SPEAR_NORNAND16BOOT 0x9
-#define CONFIG_SPEAR_USBBOOT 0x8
-
-#define CONFIG_SPEAR_MPMCREGS 100
-
-#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
-#define CONFIG_SYS_FSMC_BASE 0x94000000
-
-#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
-#define CONFIG_SYS_FSMC_BASE 0x44000000
-
-#undef CONFIG_SYS_NAND_CLE
-#undef CONFIG_SYS_NAND_ALE
-#define CONFIG_SYS_NAND_CLE (1 << 17)
-#define CONFIG_SYS_NAND_ALE (1 << 16)
-
-#define CONFIG_SPEAR_EMIBASE 0x4F000000
-#define CONFIG_SPEAR_RASBASE 0xB4000000
-
-#define CONFIG_SYS_MACB0_BASE 0xB0000000
-#define CONFIG_SYS_MACB1_BASE 0xB0800000
-#define CONFIG_SYS_MACB2_BASE 0xB1000000
-#define CONFIG_SYS_MACB3_BASE 0xB1800000
-
-#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE 0xD0180000
-#define CONFIG_SYS_FSMC_BASE 0x4C000000
-
-#define CONFIG_SPEAR_EMIBASE 0x40000000
-#define CONFIG_SPEAR_RASBASE 0xB3000000
-
-#define CONFIG_SYS_MACB0_BASE 0xAA000000
-
+#ifndef _ASM_ARCH_SPEAR_HARDWARE_H
+#define _ASM_ARCH_SPEAR_HARDWARE_H
+
+#if defined(CONFIG_SOC_SPEAR600)
+#include <asm/arch/spear600.h>
+#elif defined(CONFIG_SOC_SPEAR300)
+#include <asm/arch/spear300.h>
+#elif defined(CONFIG_SOC_SPEAR310)
+#include <asm/arch/spear310.h>
+#elif defined(CONFIG_SOC_SPEAR320)
+#include <asm/arch/spear320.h>
#endif
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/misc.h
similarity index 99%
rename from arch/arm/include/asm/arch-spear/spr_misc.h
rename to arch/arm/include/asm/arch-spear/misc.h
index b86296d..89f7964 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/misc.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef _SPR_MISC_H
-#define _SPR_MISC_H
+#ifndef ASM_ARCH_SPEAR_MISC_H
+#define ASM_ARCH_SPEAR_MISC_H
struct misc_regs {
u32 auto_cfg_reg; /* 0x0 */
diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spear300.h
similarity index 64%
rename from arch/arm/include/asm/arch-spear/spr_ssp.h
rename to arch/arm/include/asm/arch-spear/spear300.h
index 4f144ee..24faaea 100644
--- a/arch/arm/include/asm/arch-spear/spr_ssp.h
+++ b/arch/arm/include/asm/arch-spear/spear300.h
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -11,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -20,26 +21,13 @@
* MA 02111-1307 USA
*/
-#ifndef _SPR_SSP_H
-#define _SPR_SSP_H
+#ifndef _ASM_ARCH_SPEAR300_H
+#define _ASM_ARCH_SPEAR300_H
-struct ssp_regs {
- u32 sspcr0;
- u32 sspcr1;
- u32 sspdr;
- u32 sspsr;
- u32 sspcpsr;
- u32 sspimsc;
- u32 sspicr;
- u32 sspdmacr;
-};
+#include <asm/arch/spear3xx.h>
-#define SSPCR0_FRF_MOT_SPI 0x0000
-#define SSPCR0_DSS_16BITS 0x000f
-
-#define SSPCR1_SSE 0x0002
-
-#define SSPSR_TNF 0x2
-#define SSPSR_TFE 0x1
+#define CONFIG_SYS_FSMC_BASE 0x94000000
+#define CONFIG_SYS_NAND_CLE (1 << 16)
+#define CONFIG_SYS_NAND_ALE (1 << 17)
#endif
diff --git a/arch/arm/include/asm/arch-spear/spear310.h b/arch/arm/include/asm/arch-spear/spear310.h
new file mode 100644
index 0000000..0f6223e
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spear310.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR310_H
+#define _ASM_ARCH_SPEAR310_H
+
+#include <asm/arch/spear3xx.h>
+
+#define CONFIG_SYS_FSMC_BASE 0x44000000
+#define CONFIG_SYS_NAND_CLE (1 << 17)
+#define CONFIG_SYS_NAND_ALE (1 << 16)
+
+#define CONFIG_SPEAR_EMIBASE 0x4F000000
+#define CONFIG_SYS_MACB0_BASE 0xB0000000
+#define CONFIG_SYS_MACB1_BASE 0xB0800000
+#define CONFIG_SYS_MACB2_BASE 0xB1000000
+#define CONFIG_SYS_MACB3_BASE 0xB1800000
+#define CONFIG_SPEAR_RASBASE 0xB4000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h
new file mode 100644
index 0000000..110afc3
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spear320.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR320_H
+#define _ASM_ARCH_SPEAR320_H
+
+#include <asm/arch/spear3xx.h>
+
+#define CONFIG_SPEAR_EMIBASE 0x40000000
+#define CONFIG_SYS_FSMC_BASE 0x4C000000
+#define CONFIG_SYS_NAND_CLE (1 << 16)
+#define CONFIG_SYS_NAND_ALE (1 << 17)
+
+#define CONFIG_SYS_MACB0_BASE 0xAA000000
+#define CONFIG_SYS_MACB1_BASE 0xAB000000
+#define CONFIG_SPEAR_RASBASE 0xB3000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear3xx.h b/arch/arm/include/asm/arch-spear/spear3xx.h
new file mode 100644
index 0000000..e0a72f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spear3xx.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR3XX_H
+#define _ASM_ARCH_SPEAR3XX_H
+
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_GPIO_BASE 0xD8100000
+#define CONFIG_SPEAR_ETHBASE 0xE0800000
+#define CONFIG_SYS_FIFO_BASE 0xE1000800
+#define CONFIG_SYS_USBD_BASE 0xE1100000
+#define CONFIG_SYS_PLUG_BASE 0xE1200000
+#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
+#define CONFIG_SYS_SMI_BASE 0xFC000000
+#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SPEAR_TIMERBASE 0xFC800000
+#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
+#define CONFIG_SPEAR_MISCBASE 0xFCA80000
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear600.h b/arch/arm/include/asm/arch-spear/spear600.h
new file mode 100644
index 0000000..c8b0047
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spear600.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR600_H
+#define _ASM_ARCH_SPEAR600_H
+
+#define CONFIG_SYS_I2C_BASE 0xD0200000
+#define CONFIG_GPIO_BASE 0xD8100000
+#define CONFIG_SPEAR_ETHBASE 0xE0800000
+#define CONFIG_SYS_FIFO_BASE 0xE1000800
+#define CONFIG_SYS_USBD_BASE 0xE1100000
+#define CONFIG_SYS_PLUG_BASE 0xE1200000
+#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
+#define CONFIG_SYS_SMI_BASE 0xFC000000
+#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SPEAR_TIMERBASE 0xFC800000
+#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
+#define CONFIG_SPEAR_MISCBASE 0xFCA80000
+
+#define CONFIG_SYS_FSMC_BASE 0xD1800000
+#define CONFIG_FSMC_NAND_BASE 0xD2000000
+#define CONFIG_SYS_NAND_CLE (1 << 16)
+#define CONFIG_SYS_NAND_ALE (1 << 17)
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/syscntl.h
similarity index 100%
rename from arch/arm/include/asm/arch-spear/spr_syscntl.h
rename to arch/arm/include/asm/arch-spear/syscntl.h
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 99a6595..df05ff2 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -28,8 +28,7 @@
#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_defs.h>
+#include <asm/arch/generic.h>
#define CPU 0
#define DDR 1
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index f809c2d..27a1697 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -28,8 +28,8 @@
#include <asm/io.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 8609a59..a1c45ae 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -29,8 +29,8 @@
#include <asm/io.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 54a2e10..82674f3 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -29,8 +29,8 @@
#include <asm/io.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
#define PLGPIO_SEL_36 0xb3000028
#define PLGPIO_IO_36 0xb3000038
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index 814f9cc..b4f013f 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -28,8 +28,8 @@
#include <asm/io.h>
#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 04/19] mtd/st_smi: Write to flash in a tight loop
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 02/19] mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 03/19] mtd/st_smi: Avoid issuing multiple WE commands Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 05/19] mtd/st_smi: Use page sizes respective to flash Vipin Kumar
` (13 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The write loop is checking for dest_addr alignment with page size. This
sometimes leads to smi controller coming out of write mode and eventually the
next write failing with ERF1 being set.
To avoid this, write to flash in a tight loop and write bytewise to also support
not word aligned data bytes to be written. Additionally, enable burst mode
before this loop so that the controller does not deselect the chip if the
transfer is finished.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/mtd/st_smi.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 1b9ff0e..5298723 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -368,13 +368,11 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector)
*
* Write to SMI flash
*/
-static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
unsigned int length, ulong bank_addr)
{
- u8 *src_addr8 = (u8 *)src_addr;
- u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
- int i, issue_we;
+ int issue_we;
switch (bank_addr) {
case SMIBANK0_BASE:
@@ -400,7 +398,10 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
/* Perform the write command */
- for (i = 0; i < length; i += 4) {
+ while (length) {
+ int k;
+ unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+
if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
issue_we = 0;
@@ -412,19 +413,14 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
return -EIO;
}
- if (length < 4) {
- int k;
+ writel(readl(&smicntl->smi_cr1) | WB_MODE, &smicntl->smi_cr1);
- /*
- * Handle special case, where length < 4 (redundant env)
- */
- for (k = 0; k < length; k++)
- *dst_addr8++ = *src_addr8++;
- } else {
- /* Normal 32bit write */
+ for (k = 0; k < wlen; k++)
*dst_addr++ = *src_addr++;
- }
+ writel(readl(&smicntl->smi_cr1) & ~WB_MODE, &smicntl->smi_cr1);
+
+ length -= wlen;
if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
return -EIO;
}
@@ -448,8 +444,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
- length, info->start[0]);
+ return smi_write(src, (unsigned char *)dest_addr, length,
+ info->start[0]);
}
/*
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 4/7] spear1310evb: Add support for evb machine
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 2/7] spear1310: Add support for spear1310 SoC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 3/7] spear1340evb: Add support for evb machine Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 5/7] spear1340lcad: Add support for LCAD machine Vipin Kumar
` (2 subsequent siblings)
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
MAINTAINERS | 1 +
board/st/spear13xx/Makefile | 1 +
board/st/spear13xx/spear1310evb.c | 93 ++++++++++++++++++++++++++++
board/st/spear13xx/spear13xx_common.c | 2 +
boards.cfg | 3 +
include/configs/spear1310-evb.h | 113 ++++++++++++++++++++++++++++++++++
include/configs/spear1310.h | 35 +++++++++++
7 files changed, 248 insertions(+)
create mode 100644 board/st/spear13xx/spear1310evb.c
create mode 100644 include/configs/spear1310-evb.h
create mode 100644 include/configs/spear1310.h
diff --git a/MAINTAINERS b/MAINTAINERS
index fe74c6e..f97b2cc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -747,6 +747,7 @@ Vipin Kumar <vipin.kumar@st.com>
spear320 ARM926EJS (spear320 Soc)
spear320-hmi ARM926EJS (spear320 SoC)
spear600 ARM926EJS (spear600 Soc)
+ spear1310-evb ARM ARMV7 (spear1310 SoC)
spear1340-evb ARM ARMV7 (spear1340 SoC)
Sergey Lapin <slapin@ossfans.org>
diff --git a/board/st/spear13xx/Makefile b/board/st/spear13xx/Makefile
index 73a9450..abddc7b 100644
--- a/board/st/spear13xx/Makefile
+++ b/board/st/spear13xx/Makefile
@@ -29,6 +29,7 @@ SOBJS-y :=
COBJS-y :=
COBJS-y += spear13xx_common.o
+COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spear1310evb.o
COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spear1340evb.o
COBJS := $(sort $(COBJS-y))
diff --git a/board/st/spear13xx/spear1310evb.c b/board/st/spear13xx/spear1310evb.c
new file mode 100644
index 0000000..dab298c
--- /dev/null
+++ b/board/st/spear13xx/spear1310evb.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <nand.h>
+#include <phy.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+
+#if defined(CONFIG_CMD_NAND)
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear1310_pins_default();
+
+ spear1310_enable_pins(PMX_FSMCNAND, PMX_NAND_8BIT);
+ spear1310_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+ spear1310_enable_pins(PMX_I2C0, 0);
+ spear1310_enable_pins(PMX_SSP0, PMX_SSP_CS0);
+ spear1310_enable_pins(PMX_SMI, PMX_SMI_2CHIPS);
+ spear1310_enable_pins(PMX_SDMMC, 0);
+ spear1310_enable_pins(PMX_ETH0, PMX_ETH_GMII);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+/*
+ * board_nand_init - Board specific NAND initialization
+ */
+void board_nand_init(void)
+{
+#if defined(CONFIG_NAND_FSMC)
+ fsmc_nand_init(&nand_chip[0]);
+#endif
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+ u32 interface = PHY_INTERFACE_MODE_MII;
+#if defined(CONFIG_DESIGNWARE_ETH)
+#if defined(CONFIG_DW_AUTONEG)
+ interface = PHY_INTERFACE_MODE_GMII;
+#endif
+ if (designware_initialize(0, CONFIG_SYS_ETH_BASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
+
+#if defined(CONFIG_CMD_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+#if defined(CONFIG_SPEAR_SDHCI)
+ if (spear_sdhci_init(CONFIG_SYS_MMC_BASE, 24000000, 6000000, 0) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/st/spear13xx/spear13xx_common.c b/board/st/spear13xx/spear13xx_common.c
index b14e3fb..d996c34 100644
--- a/board/st/spear13xx/spear13xx_common.c
+++ b/board/st/spear13xx/spear13xx_common.c
@@ -34,6 +34,8 @@ int checkboard(void)
{
#ifdef CONFIG_MACH_SPEAR1340EVB
printf("BOARD: SPEAr1340-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR1310EVB)
+ printf("BOARD: SPEAr1310-EVB\n");
#else
#error BOARD not supported
#endif
diff --git a/boards.cfg b/boards.cfg
index 0214abe..aecee77 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -269,6 +269,9 @@ origen arm armv7 origen samsung exynos
s5pc210_universal arm armv7 universal_c210 samsung exynos
smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
+spear1310 arm armv7 spear13xx st spear13xx spear1310-evb:spear1310
+spear1310_nand arm armv7 spear13xx st spear13xx spear1310-evb:spear1310,nand
+spear1310_usbtty arm armv7 spear13xx st spear13xx spear1310-evb:spear1310,usbtty
spear1340 arm armv7 spear13xx st spear13xx spear1340-evb:spear1340
spear1340_nand arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,nand
spear1340_usbtty arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,usbtty
diff --git a/include/configs/spear1310-evb.h b/include/configs/spear1310-evb.h
new file mode 100644
index 0000000..6c21cf4
--- /dev/null
+++ b/include/configs/spear1310-evb.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR1310EVB
+#define CONFIG_MACH_TYPE 2881
+
+/* Timer configurations */
+#define CONFIG_ARMV7_CA9LTIMER
+#define CONFIG_ARMV7_LTMR_CLK 250000000
+
+/* ARASAN SD MMC configuration */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_SPEAR_SDHCI
+#endif
+
+/* Designware Ethernet configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DESIGNWARE_ETH
+ #define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_PHY_GIGE
+ #define CONFIG_DW0_PHY 5
+ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+ #define CONFIG_DW_AUTONEG
+#endif
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_OTG
+ #define CONFIG_DW_OTG_PHYINIT
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#define CONFIG_ST_SMI
+
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Environment Variable configs */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xE6060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xe6080000 - 0xe6070000"
+
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00140000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock11 "
+
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x180000 0x020000; " \
+ "nand read.jffs2 0x900000 0x1c0000 0x4C0000; " \
+ "bootm 0x900000 - 0x800000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear13xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear1310-evb.dtb\0"
+
+#include <configs/spear1310.h>
+#endif
diff --git a/include/configs/spear1310.h b/include/configs/spear1310.h
new file mode 100644
index 0000000..ad348f7
--- /dev/null
+++ b/include/configs/spear1310.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR1310_H
+#define __CONFIG_SPEAR1310_H
+
+#define CONFIG_SOC_SPEAR1310
+
+#if defined(CONFIG_DDR_ECC_ENABLE)
+ #define CONFIG_C3
+ #define CONFIG_SPL_MISC_SUPPORT
+#endif
+
+#include <configs/spear13xx.h>
+#endif /* __CONFIG_SPEAR1310_H */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 04/11] spear/board: Cleanup spear related board files
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 03/11] spear/include: Clean up the spear include files Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 05/11] spear: Append MISC_ as prefix to misc register bitmasks Vipin Kumar
` (6 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
This patch targets to cleanup the board area for spear. The modifications in
this patch include
- Move spear board files to board/st/spear/
- Place specific init routines in respective macro
Place board_nand_init and board_eth_init in respective CONFIG_CMD_ macros
- Remove initialization of bi_arch_number
bi_arch_number gets initialized via CONFIG_MACH_TYPE through the uboot
framework itself obviating the need of this code
- Remove misc_init_r routine
- Remove routine dram_init_banksize
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
board/spear/common/Makefile | 50 ----------------------
board/spear/spear300/Makefile | 45 -------------------
board/spear/spear320/Makefile | 45 -------------------
board/spear/x600/Makefile | 47 --------------------
board/{spear/spear600 => st/spear}/Makefile | 16 ++++++-
.../spear310/Makefile => st/spear/config.mk} | 27 ++----------
.../spear300/spear300.c => st/spear/spear300evb.c} | 12 +++---
.../spear310/spear310.c => st/spear/spear310evb.c} | 12 +++---
.../spear320/spear320.c => st/spear/spear320plc.c} | 11 +++--
.../spear600/spear600.c => st/spear/spear600evb.c} | 13 +++---
.../common/spr_misc.c => st/spear/spear_common.c} | 34 ++-------------
.../spear/spear_lowlevel_init.S} | 0
board/{spear/x600 => st/spear}/x600.c | 0
board/{spear/x600/fpga.c => st/spear/x600fpga.c} | 0
board/{spear/x600/fpga.h => st/spear/x600fpga.h} | 0
boards.cfg | 28 ++++++------
16 files changed, 61 insertions(+), 279 deletions(-)
delete mode 100644 board/spear/common/Makefile
delete mode 100644 board/spear/spear300/Makefile
delete mode 100644 board/spear/spear320/Makefile
delete mode 100644 board/spear/x600/Makefile
rename board/{spear/spear600 => st/spear}/Makefile (76%)
rename board/{spear/spear310/Makefile => st/spear/config.mk} (56%)
rename board/{spear/spear300/spear300.c => st/spear/spear300evb.c} (94%)
rename board/{spear/spear310/spear310.c => st/spear/spear310evb.c} (95%)
rename board/{spear/spear320/spear320.c => st/spear/spear320plc.c} (95%)
rename board/{spear/spear600/spear600.c => st/spear/spear600evb.c} (94%)
rename board/{spear/common/spr_misc.c => st/spear/spear_common.c} (89%)
rename board/{spear/common/spr_lowlevel_init.S => st/spear/spear_lowlevel_init.S} (100%)
rename board/{spear/x600 => st/spear}/x600.c (100%)
rename board/{spear/x600/fpga.c => st/spear/x600fpga.c} (100%)
rename board/{spear/x600/fpga.h => st/spear/x600fpga.h} (100%)
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
deleted file mode 100644
index 5c66c3f..0000000
--- a/board/spear/common/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB = $(obj)lib$(VENDOR).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS := spr_misc.o
-SOBJS := spr_lowlevel_init.o
-endif
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
deleted file mode 100644
index aa10749..0000000
--- a/board/spear/spear300/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := spear300.o
-SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile
deleted file mode 100644
index 68dd734..0000000
--- a/board/spear/spear320/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := spear320.o
-SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
deleted file mode 100644
index 8c4e7e2..0000000
--- a/board/spear/x600/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS := fpga.o $(BOARD).o
-endif
-SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/spear600/Makefile b/board/st/spear/Makefile
similarity index 76%
rename from board/spear/spear600/Makefile
rename to board/st/spear/Makefile
index ee66fc6..f925c19 100644
--- a/board/spear/spear600/Makefile
+++ b/board/st/spear/Makefile
@@ -25,11 +25,23 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+SOBJS-y :=
+COBJS-y :=
+
ifndef CONFIG_SPL_BUILD
-COBJS := spear600.o
+SOBJS-y += spear_lowlevel_init.o
+COBJS-y += spear_common.o
+COBJS-$(CONFIG_MACH_X600) += x600.o
+COBJS-$(CONFIG_MACH_X600) += x600fpga.o
endif
-SOBJS :=
+COBJS-$(CONFIG_MACH_SPEAR300EVB) += spear300evb.o
+COBJS-$(CONFIG_MACH_SPEAR310EVB) += spear310evb.o
+COBJS-$(CONFIG_MACH_SPEAR320EVB) += spear320plc.o
+COBJS-$(CONFIG_MACH_SPEAR600EVB) += spear600evb.o
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/spear/spear310/Makefile b/board/st/spear/config.mk
similarity index 56%
rename from board/spear/spear310/Makefile
rename to board/st/spear/config.mk
index c5b6327..9533c5f 100644
--- a/board/spear/spear310/Makefile
+++ b/board/st/spear/config.mk
@@ -1,6 +1,6 @@
#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# Copyright (C) 2012 ST Microelectronics
+# Vipin Kumar <vipin.kumar@st.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -21,25 +21,4 @@
# MA 02111-1307 USA
#
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := spear310.o
-SOBJS :=
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ALL-y += $(obj)u-boot.img
diff --git a/board/spear/spear300/spear300.c b/board/st/spear/spear300evb.c
similarity index 94%
rename from board/spear/spear300/spear300.c
rename to board/st/spear/spear300evb.c
index 27a1697..2c7ccd6 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/st/spear/spear300evb.c
@@ -31,20 +31,17 @@
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
+#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
-int board_init(void)
-{
- return spear_board_init(MACH_TYPE_SPEAR300);
-}
-
+#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
* @nand: mtd private chip structure
*
* Called by nand_init_chip to initialize the board specific functions
*/
-
void board_nand_init()
{
struct misc_regs *const misc_regs_p =
@@ -62,7 +59,9 @@ void board_nand_init()
#endif
return;
}
+#endif
+#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
int ret = 0;
@@ -75,3 +74,4 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
+#endif
diff --git a/board/spear/spear310/spear310.c b/board/st/spear/spear310evb.c
similarity index 95%
rename from board/spear/spear310/spear310.c
rename to board/st/spear/spear310evb.c
index a1c45ae..4ed8f01 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/st/spear/spear310evb.c
@@ -32,20 +32,17 @@
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
+#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
-int board_init(void)
-{
- return spear_board_init(MACH_TYPE_SPEAR310);
-}
-
+#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
* @nand: mtd private chip structure
*
* Called by nand_init_chip to initialize the board specific functions
*/
-
void board_nand_init()
{
struct misc_regs *const misc_regs_p =
@@ -63,7 +60,9 @@ void board_nand_init()
#endif
return;
}
+#endif
+#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
int ret = 0;
@@ -93,3 +92,4 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
+#endif
diff --git a/board/spear/spear320/spear320.c b/board/st/spear/spear320plc.c
similarity index 95%
rename from board/spear/spear320/spear320.c
rename to board/st/spear/spear320plc.c
index 82674f3..a463998 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/st/spear/spear320plc.c
@@ -35,7 +35,9 @@
#define PLGPIO_SEL_36 0xb3000028
#define PLGPIO_IO_36 0xb3000038
+#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
static void spear_phy_reset(void)
{
@@ -46,23 +48,22 @@ static void spear_phy_reset(void)
int board_init(void)
{
spear_phy_reset();
- return spear_board_init(MACH_TYPE_SPEAR320);
+ return 0;
}
+#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
* @nand: mtd private chip structure
*
* Called by nand_init_chip to initialize the board specific functions
*/
-
void board_nand_init()
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
struct nand_chip *nand = &nand_chip[0];
-#if defined(CONFIG_NAND_FSMC)
if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG30) ||
((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
@@ -70,11 +71,12 @@ void board_nand_init()
fsmc_nand_init(nand);
}
-#endif
return;
}
+#endif
+#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
int ret = 0;
@@ -92,3 +94,4 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
+#endif
diff --git a/board/spear/spear600/spear600.c b/board/st/spear/spear600evb.c
similarity index 94%
rename from board/spear/spear600/spear600.c
rename to board/st/spear/spear600evb.c
index b4f013f..61cea50 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/st/spear/spear600evb.c
@@ -31,20 +31,17 @@
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
+#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
-int board_init(void)
-{
- return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
+#if defined(CONFIG_CMD_NAND)
/*
* board_nand_init - Board specific NAND initialization
* @nand: mtd private chip structure
*
* Called by nand_init_chip to initialize the board specific functions
*/
-
void board_nand_init()
{
struct misc_regs *const misc_regs_p =
@@ -57,11 +54,12 @@ void board_nand_init()
#endif
return;
}
+#endif
+#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
int ret = 0;
-
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
#if defined(CONFIG_DW_AUTONEG)
@@ -73,3 +71,4 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
+#endif
diff --git a/board/spear/common/spr_misc.c b/board/st/spear/spear_common.c
similarity index 89%
rename from board/spear/common/spr_misc.c
rename to board/st/spear/spear_common.c
index df05ff2..c760229 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/st/spear/spear_common.c
@@ -39,21 +39,18 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET)
static int i2c_read_mac(uchar *buffer);
#endif
+void lowlevel_init(void)
+{
+}
int dram_init(void)
{
/* Store complete RAM size and return */
- gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
return 0;
}
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
int board_early_init_f()
{
#if defined(CONFIG_ST_SMI)
@@ -61,27 +58,6 @@ int board_early_init_f()
#endif
return 0;
}
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_NET)
- uchar mac_id[6];
-
- if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
- eth_setenv_enetaddr("ethaddr", mac_id);
-#endif
- setenv("verify", "n");
-
-#if defined(CONFIG_SPEAR_USBTTY)
- setenv("stdin", "usbtty");
- setenv("stdout", "usbtty");
- setenv("stderr", "usbtty");
-
-#ifndef CONFIG_SYS_NO_DCACHE
- dcache_enable();
-#endif
-#endif
- return 0;
-}
#ifdef CONFIG_SPEAR_EMI
struct cust_emi_para {
@@ -140,8 +116,6 @@ void spear_emi_init(void)
int spear_board_init(ulong mach_type)
{
- gd->bd->bi_arch_number = mach_type;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
diff --git a/board/spear/common/spr_lowlevel_init.S b/board/st/spear/spear_lowlevel_init.S
similarity index 100%
rename from board/spear/common/spr_lowlevel_init.S
rename to board/st/spear/spear_lowlevel_init.S
diff --git a/board/spear/x600/x600.c b/board/st/spear/x600.c
similarity index 100%
rename from board/spear/x600/x600.c
rename to board/st/spear/x600.c
diff --git a/board/spear/x600/fpga.c b/board/st/spear/x600fpga.c
similarity index 100%
rename from board/spear/x600/fpga.c
rename to board/st/spear/x600fpga.c
diff --git a/board/spear/x600/fpga.h b/board/st/spear/x600fpga.h
similarity index 100%
rename from board/spear/x600/fpga.h
rename to board/st/spear/x600fpga.h
diff --git a/boards.cfg b/boards.cfg
index fe357e7..3b0348a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -198,19 +198,21 @@ omap730p2_cs0boot arm arm926ejs omap730p2 ti omap
omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
-spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300
-spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand
-spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty
-spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310
-spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR
-spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand
-spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty
-spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320
-spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty
-spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600
-spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
-spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
-x600 arm arm926ejs - spear spear x600
+x600 arm arm926ejs - st spear x600
+spear300 arm arm926ejs spear st spear spear300-evb:spear300
+spear300_nand arm arm926ejs spear st spear spear300-evb:spear300,nand
+spear300_usbtty arm arm926ejs spear st spear spear300-evb:spear300,usbtty
+spear310 arm arm926ejs spear st spear spear310-evb:spear310
+spear310_pnor arm arm926ejs spear st spear spear310-evb:spear310,pnor
+spear310_nand arm arm926ejs spear st spear spear310-evb:spear310,nand
+spear310_usbtty arm arm926ejs spear st spear spear310-evb:spear310,usbtty
+spear320 arm arm926ejs spear st spear spear320-evb:spear320
+spear320_pnor arm arm926ejs spear st spear spear320-evb:spear320,pnor
+spear320_nand arm arm926ejs spear st spear spear320-evb:spear320,nand
+spear320_usbtty arm arm926ejs spear st spear spear320-evb:spear320,usbtty
+spear600 arm arm926ejs spear st spear spear600-evb:spear600
+spear600_nand arm arm926ejs spear st spear spear600-evb:spear600,nand
+spear600_usbtty arm arm926ejs spear st spear spear600-evb:spear600,usbtty
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 4/9] spear/configs: Modify several configurations
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 2/9] spear3xx: Add pinmux support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 3/9] spear320plc: Correct the MACB interface Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 5/9] spear320: Add support for SD/MMC Vipin Kumar
` (4 subsequent siblings)
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
- Define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Define CONFIG_SYS_EXCEPTION_VECTORS_HIGH and remove specific initialization
of CPU as high vector
- Define CONFIG_DISPLAY_BOARDINFO and print board info
- Add GPIO support
- Define CONFIG_BOOT_PARAMS_P for all spear boards
It also makes a few board_init calls redundant so remove them from the code
- Enable OTG support
- Enable SPI and SDMMC support
- Enable USBH EHCI support
- Disable caches explicitly
- Keep ATAG interface for kernel booting
The older kernel needs an ATAG interface to boot. The bootloader needs to
pass the information in the form of ATAGS. Keep this ATAG interface with the
new DT interface for kernel booting
- Remove extraneous configurations
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
board/st/spear/spear_common.c | 16 +++++++++
board/st/spear/spear_lowlevel_init.S | 14 --------
include/configs/spear.h | 49 +++++++++++++++++++++++++--
include/configs/spear300-evb.h | 24 ++++++++++----
include/configs/spear310-evb.h | 24 ++++++++++----
include/configs/spear320-evb.h | 64 +++++++++++-------------------------
include/configs/spear600-evb.h | 32 ++++++++++++++----
7 files changed, 141 insertions(+), 82 deletions(-)
diff --git a/board/st/spear/spear_common.c b/board/st/spear/spear_common.c
index f274b6e..2257779 100644
--- a/board/st/spear/spear_common.c
+++ b/board/st/spear/spear_common.c
@@ -39,6 +39,22 @@ void lowlevel_init(void)
{
}
+int checkboard(void)
+{
+#ifdef CONFIG_MACH_SPEAR300EVB
+ printf("BOARD: SPEAr300-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR310EVB)
+ printf("BOARD: SPEAr310-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR320EVB)
+ printf("BOARD: SPEAr320-PLC\n");
+#elif defined(CONFIG_MACH_SPEAR600EVB)
+ printf("BOARD: SPEAr600-EVB\n");
+#else
+#error BOARD not supported
+#endif
+ return 0;
+}
+
int dram_init(void)
{
/* Store complete RAM size and return */
diff --git a/board/st/spear/spear_lowlevel_init.S b/board/st/spear/spear_lowlevel_init.S
index 6fbe579..77fa821 100644
--- a/board/st/spear/spear_lowlevel_init.S
+++ b/board/st/spear/spear_lowlevel_init.S
@@ -23,20 +23,6 @@
#include <config.h>
-/*
- * platform specific initializations are already done in Xloader
- * Initializations already done include
- * DDR, PLLs, IP's clock enable and reset release etc
- */
-.globl lowlevel_init
-lowlevel_init:
- /* By default, U-Boot switches CPU to low-vector */
- /* Revert this as we work in high vector even in U-Boot */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00002000
- mcr p15, 0, r0, c1, c0, 0
- mov pc, lr
-
/* void setfreq(unsigned int device, unsigned int frequency) */
.global setfreq
setfreq:
diff --git a/include/configs/spear.h b/include/configs/spear.h
index a8ddf54..4cb551d 100644
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -29,7 +29,7 @@
#define CONFIG_PLAT_SPEAR
#define CONFIG_SYS_TEXT_BASE 0x00700000
-#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
+#define CONFIG_BOOT_PARAMS_P 0x00000100
/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ 1000
@@ -38,7 +38,6 @@
#if defined(CONFIG_DESIGNWARE_ETH) || defined(CONFIG_MACB)
#define CONFIG_MII
#define CONFIG_NET_MULTI
- #define CONFIG_PHY_GIGE
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
@@ -50,7 +49,7 @@
#endif
/* Generic configuration for USBD driver */
-#if defined(CONFIG_DW_UDC)
+#if defined(CONFIG_DW_UDC) || defined(CONFIG_DW_OTG)
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_HS
#define CONFIG_USB_TTY
@@ -87,6 +86,25 @@
#define CONFIG_CMD_I2C
#endif
+/* Generic configuration for GPIO driver */
+#if defined(CONFIG_SPEAR_GPIO)
+ #define CONFIG_CMD_GPIO
+#endif
+
+/* Generic configuration for USB EHCI driver */
+#if defined(CONFIG_USB_EHCI_SPEAR)
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_STORAGE
+ #define CONFIG_CMD_USB
+#endif
+
+/* Enable FAT and Partition types */
+#if defined(CONFIG_USB_STORAGE)
+ #define CONFIG_CMD_FAT
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_ISO_PARTITION
+#endif
+
/* Generic configuration for ST SMI driver */
#if defined(CONFIG_ST_SMI)
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
@@ -107,6 +125,23 @@
57600, 115200 }
#endif
+/* Generic configuration for AMBA PL022 driver */
+#if defined(CONFIG_PL022_SPI)
+ #define CONFIG_CMD_SPI
+ #if defined(CONFIG_SPI_FLASH)
+ #define CONFIG_CMD_SF
+ #define CONFIG_SPI_FLASH_STMICRO
+ #endif
+#endif
+
+/* Generic configuration for Arasan SD/MMC driver */
+#if defined(CONFIG_SPEAR_SDHCI)
+ #define CONFIG_MMC
+ #define CONFIG_SDHCI
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_CMD_MMC
+#endif
+
/* Generic configuration for FSMC NAND driver */
#if defined(CONFIG_NAND_FSMC)
#define CONFIG_SYS_NAND_SELF_INIT
@@ -153,12 +188,20 @@
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_POST CONFIG_SYS_POST_MEMORY
#define CONFIG_SYS_POST_WORD_ADDR 0x0
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+#if !defined(CONFIG_SPL_BUILD)
+ #define CONFIG_SYS_DCACHE_OFF
+#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_AUTOBOOT_KEYED
diff --git a/include/configs/spear300-evb.h b/include/configs/spear300-evb.h
index cb6d764..e3f4ab4 100644
--- a/include/configs/spear300-evb.h
+++ b/include/configs/spear300-evb.h
@@ -54,6 +54,14 @@
#define CONFIG_SYS_I2C_SLAVE 0x02
#endif
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
/* AMBA PL011 configurations */
#define CONFIG_PL011_SERIAL
#define CONFIG_CONS_INDEX 0
@@ -74,17 +82,19 @@
/* Environment is in serial NOR flash */
#define CONFIG_ENV_ADDR 0xF8060000
#define CONFIG_ENV_SECT_SIZE 0x00010000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
- #define CONFIG_BOOTCOMMAND "bootm 0xF8070000"
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xf8080000 - 0xf8070000"
#elif defined(CONFIG_ENV_IS_IN_NAND)
/* Environment is in NAND */
- #define CONFIG_ENV_OFFSET 0x00060000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+ #define CONFIG_ENV_OFFSET 0x00070000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock11 "
- #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
- "0x80000 0x4C0000; " \
- "bootm 0x1600000"
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x78000 0x008000; " \
+ "nand read.jffs2 0x900000 0x80000 0x4C0000; " \
+ "bootm 0x900000 - 0x800000"
#endif
#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
diff --git a/include/configs/spear310-evb.h b/include/configs/spear310-evb.h
index cb73ba7..505c8a4 100644
--- a/include/configs/spear310-evb.h
+++ b/include/configs/spear310-evb.h
@@ -67,6 +67,14 @@
#define CONFIG_SYS_I2C_SLAVE 0x02
#endif
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
/* AMBA PL011 configurations */
#define CONFIG_PL011_SERIAL
#define CONFIG_CONS_INDEX 0
@@ -105,17 +113,19 @@
/* Environment is in serial NOR flash */
#define CONFIG_ENV_ADDR 0xF8060000
#define CONFIG_ENV_SECT_SIZE 0x00010000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
- #define CONFIG_BOOTCOMMAND "bootm 0xF8050000"
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xf8080000 - 0xf8070000"
#endif
#elif defined(CONFIG_ENV_IS_IN_NAND)
/* Environment is in NAND */
- #define CONFIG_ENV_OFFSET 0x00060000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+ #define CONFIG_ENV_OFFSET 0x00140000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock11 "
- #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
- "0x200000 0x4C0000; " \
- "bootm 0x1600000"
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x180000 0x020000; " \
+ "nand read.jffs2 0x900000 0x1c0000 0x4C0000; " \
+ "bootm 0x900000 - 0x800000"
#endif
#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
diff --git a/include/configs/spear320-evb.h b/include/configs/spear320-evb.h
index a054970..229fa83 100644
--- a/include/configs/spear320-evb.h
+++ b/include/configs/spear320-evb.h
@@ -28,15 +28,7 @@
#define CONFIG_SPEAR_USBTTY
#endif
-#if defined(CONFIG_pnor)
- #define CONFIG_FLASH_PNOR
-#endif
-
-#if defined(CONFIG_nand)
- #define CONFIG_ENV_IS_IN_NAND
-#else
- #define CONFIG_ENV_IS_IN_FLASH
-#endif
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_MACH_SPEAR320EVB
#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR320
@@ -69,51 +61,35 @@
#define CONFIG_PL011_SERIAL
#define CONFIG_CONS_INDEX 0
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
/* Designware UDC configurations */
#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DW_UDC
#endif
-/* FSMC NAND configurations */
-#define CONFIG_NAND_FSMC
-#define CONFIG_SYS_FSMC_NAND_8BIT
-
/* Flash configurations */
-#if defined(CONFIG_FLASH_PNOR)
- #define CONFIG_ST_EMI
-#else
- #define CONFIG_ST_SMI
-#endif
+#define CONFIG_ST_SMI
-/* CFI Driver configurations */
-#if defined(CONFIG_FLASH_PNOR)
- #define CONFIG_FLASH_CFI_DRIVER
- #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
-#endif
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_SPEAR_DDR_2HCLK
+#define CONFIG_DDR_MT47H64M16
/* Environment Variable configs */
#if defined(CONFIG_ENV_IS_IN_FLASH)
- #if defined(CONFIG_FLASH_PNOR)
- /* Environment is in parallel NOR flash */
- #define CONFIG_ENV_ADDR 0xF8040000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
- #define CONFIG_BOOTCOMMAND "bootm 0xF8050000"
-
- #else
- /* Environment is in serial NOR flash */
- #define CONFIG_ENV_ADDR 0xF8060000
- #define CONFIG_ENV_SECT_SIZE 0x00010000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
- #define CONFIG_BOOTCOMMAND "bootm 0xF8070000"
- #endif
-#elif defined(CONFIG_ENV_IS_IN_NAND)
- /* Environment is in NAND */
- #define CONFIG_ENV_OFFSET 0x00060000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
-
- #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
- "0x200000 0x4C0000; " \
- "bootm 0x1600000"
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xf8080000 - 0xf8070000"
#endif
#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
diff --git a/include/configs/spear600-evb.h b/include/configs/spear600-evb.h
index 5fe326a..e7c5ee3 100644
--- a/include/configs/spear600-evb.h
+++ b/include/configs/spear600-evb.h
@@ -41,6 +41,7 @@
#if !defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_SEARCH_PHY
+ #define CONFIG_PHY_GIGE
#define CONFIG_DW0_PHY 1
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_DW_AUTONEG
@@ -54,6 +55,14 @@
#define CONFIG_SYS_I2C_SLAVE 0x02
#endif
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
/* AMBA PL011 configurations */
#define CONFIG_PL011_SERIAL
#define CONFIG_CONS_INDEX 0
@@ -70,21 +79,30 @@
/* ST SMI (Serial flash) configurations */
#define CONFIG_ST_SMI
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_SPEAR_DDR_2HCLK
+#define CONFIG_DDR_MT47H32M16
+#define CONFIG_SPL_TEXT_BASE 0xD2800B00
+#define CONFIG_SYS_SNOR_BOOT_BASE 0xF8010000
+
#if defined(CONFIG_ENV_IS_IN_FLASH)
/* Environment is in serial NOR flash */
#define CONFIG_ENV_ADDR 0xF8060000
#define CONFIG_ENV_SECT_SIZE 0x00010000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock3 "
- #define CONFIG_BOOTCOMMAND "bootm 0xF8060000"
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND "" \
+ "bootm 0xf8080000 - 0xf8070000"
#elif defined(CONFIG_ENV_IS_IN_NAND)
/* Environment is in NAND */
- #define CONFIG_ENV_OFFSET 0x00060000
- #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock7 "
+ #define CONFIG_ENV_OFFSET 0x00140000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock11 "
- #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
- "0x80000 0x4C0000; " \
- "bootm 0x1600000"
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x180000 0x020000; " \
+ "nand read.jffs2 0x900000 0x1c0000 0x4C0000; " \
+ "bootm 0x900000 - 0x800000"
#endif
#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 05/19] mtd/st_smi: Use page sizes respective to flash
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (2 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 04/19] mtd/st_smi: Write to flash in a tight loop Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 06/19] usbh/ehci: Increase timeout for enumeration Vipin Kumar
` (12 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The page size is a flash dependent property and the driver was using a macro in
place of page size. This patch uses the proper page size wrt the flash device
connected on board
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/mtd/st_smi.c | 41 +++++++++++++++++++++++++++++++++--------
include/linux/mtd/st_smi.h | 1 -
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 5298723..ac10a3d 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -96,6 +96,25 @@ static struct flash_device flash_devices[] = {
};
/*
+ * get_flash_device - Return flash_device pointer for a particular device id
+ * @id: Device id
+ *
+ * Return flash_device pointer for a particular device id
+ */
+static struct flash_device *get_flash_device(u32 id)
+{
+ struct flash_device *flash_dev_p = &flash_devices[0];
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(flash_devices); i++, flash_dev_p++) {
+ if (flash_dev_p->device_id == id)
+ return flash_dev_p;
+ }
+
+ return NULL;
+}
+
+/*
* smi_wait_xfer_finish - Wait until TFF is set in status register
* @timeout: timeout in milliseconds
*
@@ -361,20 +380,27 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector)
/*
* smi_write - Write to SMI flash
+ * @info: flash info structure
* @src_addr: source buffer
* @dst_addr: destination buffer
* @length: length to write in bytes
- * @bank: bank base address
*
* Write to SMI flash
*/
-static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
- unsigned int length, ulong bank_addr)
+static int smi_write(flash_info_t *info, unsigned char *src_addr,
+ unsigned char *dst_addr, unsigned int length)
{
+ struct flash_device *flash_device_p = get_flash_device(info->flash_id);
+ u32 page_size;
int banknum;
int issue_we;
- switch (bank_addr) {
+ if (!flash_device_p)
+ return -EIO;
+
+ page_size = flash_device_p->pagesize;
+
+ switch (info->start[0]) {
case SMIBANK0_BASE:
banknum = BANK0;
break;
@@ -400,9 +426,9 @@ static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
/* Perform the write command */
while (length) {
int k;
- unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+ unsigned int wlen = min(page_size, length);
- if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+ if (issue_we || (((ulong)(dst_addr) % page_size) == 0)) {
issue_we = 0;
if (smi_wait_till_ready(banknum,
@@ -444,8 +470,7 @@ static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
*/
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
- return smi_write(src, (unsigned char *)dest_addr, length,
- info->start[0]);
+ return smi_write(info, src, (unsigned char *)dest_addr, length);
}
/*
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
index 04f81ea..5837493 100644
--- a/include/linux/mtd/st_smi.h
+++ b/include/linux/mtd/st_smi.h
@@ -108,7 +108,6 @@ struct flash_dev {
ushort sector_count;
};
-#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
#define WMODE_TOUT 15 /* write enable timeout(in ms) */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 5/7] spear1340lcad: Add support for LCAD machine
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
` (2 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 4/7] spear1310evb: " Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 6/7] spear1340evb: Add SPL support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 7/7] spear1310evb: " Vipin Kumar
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
MAINTAINERS | 1 +
board/st/spear13xx/Makefile | 1 +
board/st/spear13xx/spear1340lcad.c | 89 ++++++++++++++++++++++++++++++++++
board/st/spear13xx/spear13xx_common.c | 2 +
boards.cfg | 1 +
include/configs/spear1340-lcad.h | 91 +++++++++++++++++++++++++++++++++++
6 files changed, 185 insertions(+)
create mode 100644 board/st/spear13xx/spear1340lcad.c
create mode 100644 include/configs/spear1340-lcad.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f97b2cc..9513fd0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -749,6 +749,7 @@ Vipin Kumar <vipin.kumar@st.com>
spear600 ARM926EJS (spear600 Soc)
spear1310-evb ARM ARMV7 (spear1310 SoC)
spear1340-evb ARM ARMV7 (spear1340 SoC)
+ spear1340-lcad ARM ARMV7 (spear1340 SoC)
Sergey Lapin <slapin@ossfans.org>
diff --git a/board/st/spear13xx/Makefile b/board/st/spear13xx/Makefile
index abddc7b..a662ac4 100644
--- a/board/st/spear13xx/Makefile
+++ b/board/st/spear13xx/Makefile
@@ -31,6 +31,7 @@ COBJS-y :=
COBJS-y += spear13xx_common.o
COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spear1310evb.o
COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spear1340evb.o
+COBJS-$(CONFIG_MACH_SPEAR1340LCAD) += spear1340lcad.o
COBJS := $(sort $(COBJS-y))
SOBJS := $(sort $(SOBJS-y))
diff --git a/board/st/spear13xx/spear1340lcad.c b/board/st/spear13xx/spear1340lcad.c
new file mode 100644
index 0000000..719e4ee
--- /dev/null
+++ b/board/st/spear13xx/spear1340lcad.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <nand.h>
+#include <phy.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+
+#if defined(CONFIG_CMD_NAND)
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear1340_pins_default();
+
+ spear1340_enable_pins(PMX_FSMCNAND, PMX_NAND_8BIT);
+ spear1340_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+ spear1340_enable_pins(PMX_SDMMC, 0);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+/*
+ * board_nand_init - Board specific NAND initialization
+ */
+void board_nand_init(void)
+{
+#if defined(CONFIG_NAND_FSMC)
+ fsmc_nand_init(&nand_chip[0]);
+#endif
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+ u32 interface = PHY_INTERFACE_MODE_RMII;
+#if defined(CONFIG_DESIGNWARE_ETH)
+#if defined(CONFIG_DW_AUTONEG)
+ interface = PHY_INTERFACE_MODE_RGMII;
+#endif
+ if (designware_initialize(0, CONFIG_SYS_ETH_BASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
+
+#if defined(CONFIG_CMD_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+#if defined(CONFIG_SPEAR_SDHCI)
+ if (spear_sdhci_init(CONFIG_SYS_MMC_BASE, 24000000, 6000000, 0) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/st/spear13xx/spear13xx_common.c b/board/st/spear13xx/spear13xx_common.c
index d996c34..7da6333 100644
--- a/board/st/spear13xx/spear13xx_common.c
+++ b/board/st/spear13xx/spear13xx_common.c
@@ -36,6 +36,8 @@ int checkboard(void)
printf("BOARD: SPEAr1340-EVB\n");
#elif defined(CONFIG_MACH_SPEAR1310EVB)
printf("BOARD: SPEAr1310-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR1340LCAD)
+ printf("BOARD: SPEAr1340-LCAD\n");
#else
#error BOARD not supported
#endif
diff --git a/boards.cfg b/boards.cfg
index aecee77..2a50773 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -275,6 +275,7 @@ spear1310_usbtty arm armv7 spear13xx st
spear1340 arm armv7 spear13xx st spear13xx spear1340-evb:spear1340
spear1340_nand arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,nand
spear1340_usbtty arm armv7 spear13xx st spear13xx spear1340-evb:spear1340,usbtty
+spear1340lcad arm armv7 spear13xx st spear13xx spear1340-lcad:spear1340
trats arm armv7 trats samsung exynos
harmony arm armv7:arm720t harmony nvidia tegra20
seaboard arm armv7:arm720t seaboard nvidia tegra20
diff --git a/include/configs/spear1340-lcad.h b/include/configs/spear1340-lcad.h
new file mode 100644
index 0000000..770a16f
--- /dev/null
+++ b/include/configs/spear1340-lcad.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_SPEAR1340LCAD
+#define CONFIG_MACH_TYPE 3395
+
+/* Timer configurations */
+#define CONFIG_ARMV7_CA9LTIMER
+#define CONFIG_ARMV7_LTMR_CLK 250000000
+
+/* ARASAN SD MMC configuration */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_SPEAR_SDHCI
+#endif
+
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_OTG
+ #define CONFIG_DW_OTG_PHYINIT
+#endif
+
+/* ST SMI (Serial flash) configurations */
+#define CONFIG_ST_SMI
+
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Environment Variable configs */
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+
+#define CONFIG_ENV_OFFSET 0x00480000
+
+#define CONFIG_BOOTCOMMAND "run bootusb; run bootupg;" \
+ "nand read.jffs2 0x800000 0x500000 0x020000; " \
+ "nand read.jffs2 0x900000 0x600000 0x500000; " \
+ "bootm 0x900000 - 0x800000"
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "mem=960M noinitrd no_console_suspend androidboot.console=ttyAMA0 " \
+ "android.checkjni=0 root=/dev/mtdblock5 rw rootfstype=yaffs2 " \
+ "rootflags=inband-tags,tags-ecc-off rootdelay=3" \
+ "video=db9000:800x480-32 at 0 init=/init"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "bootusb=mw 0x0 0x0; usb start; fatload usb 0:2 0x0 run.img; " \
+ "source 0x0\0" \
+ "bootupg=mw 0x0 0x0; fatload usb 0:1 0x0 vInstaller/upgrade.img; " \
+ "source 0x0\0" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear13xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear1340-lcad.dtb\0"
+
+#include <configs/spear1340.h>
+#endif
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 5/9] spear320: Add support for SD/MMC
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (2 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 4/9] spear/configs: Modify several configurations Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 6/9] spear320-hmi: Add support for hmi machine Vipin Kumar
` (3 subsequent siblings)
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/include/asm/arch-spear/mmc.h | 29 +++++++++++++++++++++++++++++
arch/arm/include/asm/arch-spear/spear320.h | 1 +
board/st/spear/spear320plc.c | 12 ++++++++++++
include/configs/spear320-evb.h | 5 +++++
4 files changed, 47 insertions(+)
create mode 100644 arch/arm/include/asm/arch-spear/mmc.h
diff --git a/arch/arm/include/asm/arch-spear/mmc.h b/arch/arm/include/asm/arch-spear/mmc.h
new file mode 100644
index 0000000..5c01a7e
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/mmc.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_MMC_H
+#define _ASM_ARCH_MMC_H
+
+extern int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h
index abdcda6..a027e10 100644
--- a/arch/arm/include/asm/arch-spear/spear320.h
+++ b/arch/arm/include/asm/arch-spear/spear320.h
@@ -31,6 +31,7 @@
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
+#define CONFIG_SYS_MMC_BASE 0x70000000
#define CONFIG_SYS_MACB0_BASE 0xAA000000
#define CONFIG_SYS_MACB1_BASE 0xAB000000
#define CONFIG_SPEAR_RASBASE 0xB3000000
diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c
index 5a79eb6..315fe2d 100644
--- a/board/st/spear/spear320plc.c
+++ b/board/st/spear/spear320plc.c
@@ -123,3 +123,15 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_CMD_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+#if defined(CONFIG_SPEAR_SDHCI)
+ if (spear_sdhci_init(CONFIG_SYS_MMC_BASE, 24000000, 6000000, 0) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/include/configs/spear320-evb.h b/include/configs/spear320-evb.h
index 229fa83..955266b 100644
--- a/include/configs/spear320-evb.h
+++ b/include/configs/spear320-evb.h
@@ -33,6 +33,11 @@
#define CONFIG_MACH_SPEAR320EVB
#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR320
+/* ARASAN SD MMC configuration */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_SPEAR_SDHCI
+#endif
+
/* Designware Ethernet configurations */
#if !defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DESIGNWARE_ETH
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 05/11] spear: Append MISC_ as prefix to misc register bitmasks
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (2 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 04/11] spear/board: Cleanup spear related board files Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 06/11] spear: Read ethaddr from I2C memory Vipin Kumar
` (5 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 4 ++--
arch/arm/cpu/arm926ejs/spear/spear600.c | 22 +++++++++-------------
arch/arm/include/asm/arch-spear/misc.h | 10 ++++++++--
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 1301608..311f31b 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -44,8 +44,8 @@ int arch_cpu_init(void)
periph1_clken |= MISC_UART0ENB;
periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
- periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
- periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+ periph_clk_cfg &= ~MISC_UARTCLKMSK;
+ periph_clk_cfg |= MISC_UART48M;
writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
#if defined(CONFIG_DESIGNWARE_ETH)
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
index f4ec10a..bd8cb7a 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -138,8 +138,9 @@ void soc_init(void)
*/
static u32 read_bootstrap(void)
{
- return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
- & CONFIG_SPEAR_BOOTSTRAPMASK;
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ return readl(&misc_p->auto_cfg_reg) & MISC_BOOTSTRAPMASK;
}
int snor_boot_selected(void)
@@ -148,16 +149,13 @@ int snor_boot_selected(void)
if (SNOR_BOOT_SUPPORTED) {
/* Check whether SNOR boot is selected */
- if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
- CONFIG_SPEAR_ONLYSNORBOOT)
+ if ((bootstrap & MISC_ONLYSNORBOOT) == MISC_ONLYSNORBOOT)
return TRUE;
- if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND8BOOT)
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
return TRUE;
- if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND16BOOT)
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
return TRUE;
}
@@ -170,12 +168,10 @@ int nand_boot_selected(void)
if (NAND_BOOT_SUPPORTED) {
/* Check whether NAND boot is selected */
- if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND8BOOT)
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
return TRUE;
- if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
- CONFIG_SPEAR_NORNAND16BOOT)
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
return TRUE;
}
@@ -194,7 +190,7 @@ int usb_boot_selected(void)
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
- if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+ if (!(bootstrap & MISC_USBBOOT))
return TRUE;
}
diff --git a/arch/arm/include/asm/arch-spear/misc.h b/arch/arm/include/asm/arch-spear/misc.h
index 89f7964..2696203 100644
--- a/arch/arm/include/asm/arch-spear/misc.h
+++ b/arch/arm/include/asm/arch-spear/misc.h
@@ -137,12 +137,18 @@ struct misc_regs {
#define MISC_SOCCFG30 0x0000000C
#define MISC_SOCCFG31 0x0000000D
#define MISC_NANDDIS 0x00020000
+#define MISC_BOOTSTRAPMASK 0x000B0000
+#define MISC_ONLYSNORBOOT 0x000A0000
+#define MISC_NORNANDBOOT 0x000B0000
+#define MISC_NORNAND8BOOT 0x00080000
+#define MISC_NORNAND16BOOT 0x00090000
+#define MISC_USBBOOT 0x00080000
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
-#define CONFIG_SPEAR_UART48M 0
-#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
+#define MISC_UART48M 0x00000000
+#define MISC_UARTCLKMSK 0x00000010
/* PRSC_CLK_CFG value */
/*
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 6/7] spear1340evb: Add SPL support
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
` (3 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 5/7] spear1340lcad: Add support for LCAD machine Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 7/7] spear1310evb: " Vipin Kumar
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
This patch adds SPL support for spear1340-evb. The major piece of code is
addition of
* system initialization code
* ddr driver code
This patch also factors the code for spear13xx and board support etc. In other
words, it also paves way for other spear13xx architecture based SoCs and other
boards based on spear1340
The source of the original code is git at git.bri.st.com:/spear/xloader.git
Another change is the way xloader runs, xloader now returns to BootROM for all
cases. The return value determines how the next level bootloader will be booted.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/armv7/Makefile | 6 +
arch/arm/cpu/armv7/spear13xx/Makefile | 26 +-
arch/arm/cpu/armv7/spear13xx/spear13xx.c | 30 +
arch/arm/cpu/armv7/spear13xx/spl-boot.c | 76 +++
arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c | 239 ++++++++
arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c | 229 ++++++++
arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c | 608 +++++++++++++++++++++
arch/arm/cpu/armv7/spear13xx/spl-spear1340.c | 210 +++++++
arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c | 162 ++++++
arch/arm/cpu/armv7/spear13xx/spl-swlvl.c | 93 ++++
arch/arm/cpu/armv7/spear13xx/start.S | 137 +++++
arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds | 45 ++
arch/arm/cpu/armv7/spear13xx/wakeup.S | 60 ++
arch/arm/include/asm/arch-spear13xx/boot.h | 106 ++++
arch/arm/include/asm/arch-spear13xx/generic.h | 8 +
arch/arm/include/asm/arch-spear13xx/mpmc.h | 332 +++++++++++
.../include/asm/arch-spear13xx/spear1340_misc.h | 76 ++-
arch/arm/include/asm/arch-spear13xx/spear13xx.h | 4 +
board/st/spear13xx/Makefile | 5 +
board/st/spear13xx/config.mk | 4 +
board/st/spear13xx/ddr/Makefile | 64 +++
board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c | 238 ++++++++
board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c | 238 ++++++++
board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c | 238 ++++++++
board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c | 238 ++++++++
.../ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c | 238 ++++++++
.../ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c | 246 +++++++++
.../ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c | 246 +++++++++
.../ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c | 238 ++++++++
.../ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c | 238 ++++++++
.../spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c | 239 ++++++++
.../spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c | 239 ++++++++
board/st/spear13xx/spl-spear1340evb.c | 57 ++
include/configs/spear1340-evb.h | 5 +
include/configs/spear13xx.h | 51 +-
spl/Makefile | 6 +
36 files changed, 5245 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-boot.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
create mode 100644 arch/arm/cpu/armv7/spear13xx/start.S
create mode 100644 arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
create mode 100644 arch/arm/cpu/armv7/spear13xx/wakeup.S
create mode 100644 arch/arm/include/asm/arch-spear13xx/boot.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/mpmc.h
create mode 100644 board/st/spear13xx/ddr/Makefile
create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
create mode 100644 board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
create mode 100644 board/st/spear13xx/spl-spear1340evb.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 3ef01f6..6d670ca 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -37,6 +37,12 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
SOBJS-y += lowlevel_init.o
endif
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE
+START :=
+endif
+endif
+
COBJS := $(sort $(COBJS-y))
SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
index cacf268..daeffa2 100644
--- a/arch/arm/cpu/armv7/spear13xx/Makefile
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -28,19 +28,37 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
+SOBJS-y :=
+COBJS-y :=
+
COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310.o
COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310-pinmux.o
COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o
COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o
-SRCS := $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
+ifdef CONFIG_SPL_BUILD
+SOBJS-y += wakeup.o
+
+COBJS-y += spl-boot.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-spear13xx.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_gatetrn.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_read.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_write.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-swlvl.o
+COBJS-$(CONFIG_SOC_SPEAR1340) += spl-spear1340.o
+endif
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
all: $(obj).depend $(LIB)
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+$(LIB): $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
diff --git a/arch/arm/cpu/armv7/spear13xx/spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
index 351e8cd..13e5422 100644
--- a/arch/arm/cpu/armv7/spear13xx/spear13xx.c
+++ b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
@@ -30,3 +30,33 @@ void enable_caches(void)
dcache_enable();
#endif
}
+
+#ifdef CONFIG_POST
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ /*
+ * Run the POST test on 64 MB memory starting from CONFIG_SYS_LOAD_ADDR
+ * The assumption here is that the DDR present on board is >= 128MB.
+ *
+ * The test runs before relocation (after the code copy has taken
+ * place), so it can not touch either before or after relocation areas
+ * of U-boot
+ *
+ * DDR usage
+ * <--------->|<---------------- / --------------->|<---------->
+ * U-boot Area to be used for U-boot
+ * before POST test after
+ * relocation relocation
+ */
+
+ *vstart = CONFIG_SYS_LOAD_ADDR;
+ *size = 64 << 20;
+
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ hang();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-boot.c b/arch/arm/cpu/armv7/spear13xx/spl-boot.c
new file mode 100644
index 0000000..fb903ed
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-boot.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/boot.h>
+#include <linux/mtd/st_smi.h>
+
+ulong spl_boot(void)
+{
+ ulong ret;
+
+#if defined(CONFIG_SPEAR_USBTTY)
+ return 0;
+#endif
+
+ switch (get_boot_type()) {
+ case BOOT_TYPE_BYPASS:
+ case BOOT_TYPE_SMI:
+ /* SNOR-SMI initialization */
+ smi_init();
+ ret = (ulong)CONFIG_SYS_SNOR_BOOT_BASE;
+ break;
+
+ case BOOT_TYPE_NAND:
+ ret = (ulong)CONFIG_SYS_NAND_BOOT_BASE;
+ break;
+
+ case BOOT_TYPE_PNOR8:
+ case BOOT_TYPE_PNOR16:
+ case BOOT_TYPE_PNOR32:
+ ret = (ulong)CONFIG_SYS_PNOR_BOOT_BASE;
+ break;
+
+ case BOOT_TYPE_USBD:
+ case BOOT_TYPE_TFTP:
+ case BOOT_TYPE_PCIE:
+ case BOOT_TYPE_UART:
+ ret = 0;
+ break;
+
+ case BOOT_TYPE_MMC:
+ ret = (ulong)CONFIG_SYS_MMC_BOOT_FILE;
+ break;
+
+ case BOOT_TYPE_I2C:
+ case BOOT_TYPE_SPI:
+ case BOOT_TYPE_RESERVED:
+ case BOOT_TYPE_UNSUPPORTED:
+ default:
+ ret = (ulong)-1;
+ break;
+ }
+
+ return ret;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
new file mode 100644
index 0000000..2b9df8f
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+#define MIN_1_8TH_CYCLE_PREAMBLE 6
+#define MIN_NO_OF_1_8TH_CYCLE 2
+#define MAX_NO_OF_1_8TH_CYCLE 6
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static void prog_rdlvl_gate_delay(u32 slice, u32 delay)
+{
+ u32 *rdlvl_gate_delay_reg = &mpmc_p->reg86;
+ u32 shift = (slice % 2) ? 0 : 16;
+
+ rdlvl_gate_delay_reg += (slice + 1) >> 1;
+ writel_field(delay << shift, 0xFFFF << shift, rdlvl_gate_delay_reg);
+}
+
+#if defined(CONFIG_DDR2)
+void ddr2_lvl_gatetrn(void)
+{
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+ u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+ u32 final_gate_counter[DATA_SLICE_MAX];
+ u32 slice;
+
+ u32 phy_ctrl_reg6_dqs_assertval[] = {
+ (0x0 << 0) | (0x0 << 20),
+ (0x0 << 0) | (0x0 << 20),
+ (0x8 << 0) | (0x8 << 20),
+ (0x9 << 0) | (0x9 << 20),
+ (0xa << 0) | (0xa << 20),
+ (0xb << 0) | (0xb << 20)
+ };
+ u32 phy_ctrl_reg6_dqs_deassertval[] = {
+ (0x00 << 5) | (0x00 << 25),
+ (0x10 << 5) | (0x10 << 25),
+ (0x11 << 5) | (0x11 << 25),
+ (0x12 << 5) | (0x12 << 25),
+ (0x13 << 5) | (0x13 << 25),
+ (0x14 << 5) | (0x14 << 25)
+ };
+
+ int RDLVL_GATE_DELAY_VALUE[5] = {32, 32, 32, 32, 32};
+
+ RDLVL_GATE_DELAY_VALUE[0] = RDLVL_GATE_DELAY_VALUE_0;
+ RDLVL_GATE_DELAY_VALUE[1] = RDLVL_GATE_DELAY_VALUE_1;
+ RDLVL_GATE_DELAY_VALUE[2] = RDLVL_GATE_DELAY_VALUE_2;
+ RDLVL_GATE_DELAY_VALUE[3] = RDLVL_GATE_DELAY_VALUE_3;
+ RDLVL_GATE_DELAY_VALUE[4] = RDLVL_GATE_DELAY_VALUE_4;
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ final_gate_counter[slice] = RDLVL_GATE_DELAY_VALUE[slice];
+ writel_field((final_gate_counter[slice] / 8) << 20, 7 << 20,
+ phy_ctrl_reg0 + slice);
+ prog_rdlvl_gate_delay(slice, final_gate_counter[slice] % 8);
+ }
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ writel_field(phy_ctrl_reg6_dqs_assertval[final_gate_counter[slice] / 8],
+ (0x1F << 0) | (0x1F << 20), phy_ctrl_reg6 + slice);
+ writel_field(phy_ctrl_reg6_dqs_deassertval[final_gate_counter[slice] / 8],
+ (0x1F << 5) | (0x1F << 25), phy_ctrl_reg6 + slice);
+ }
+}
+#elif defined(CONFIG_DDR3)
+static void set_gate_parms(u32 gate_cnt, u32 slice)
+{
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+
+ writel_field((gate_cnt / 8) << 20, 7 << 20, phy_ctrl_reg0 + slice);
+ prog_rdlvl_gate_delay(slice, gate_cnt % 8);
+
+ swlvl_load();
+ wait_op_done();
+}
+
+static void set_gate_parms_resp(u32 *gate_cnt_p, u32 slice, u32 loopon)
+{
+ do {
+ (*gate_cnt_p)++;
+ set_gate_parms(*gate_cnt_p, slice);
+ } while (read_resp(slice) == loopon);
+}
+
+void ddr3_lvl_gatetrn(void)
+{
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+ u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+ u32 *phy_ctrl_reg7 = &mpmc_p->reg160;
+ u32 final_gate_counter[DATA_SLICE_MAX];
+ u32 slice, gate_counter, resp;
+ u32 prelim_preamble_start = 8, prelim_rise_edge = 8, prelim_fall_edge;
+ u32 prelim_dqs_low_start, prelim_dqs_low_end;
+
+ u32 phy_ctrl_reg6_dqs_assertval[] = {
+ (0x0 << 0) | (0x0 << 20),
+ (0x0 << 0) | (0x0 << 20),
+ (0x8 << 0) | (0x8 << 20),
+ (0x9 << 0) | (0x9 << 20),
+ (0xa << 0) | (0xa << 20),
+ (0xb << 0) | (0xb << 20)
+ };
+ u32 phy_ctrl_reg6_dqs_deassertval[] = {
+ (0x00 << 5) | (0x00 << 25),
+ (0x10 << 5) | (0x10 << 25),
+ (0x11 << 5) | (0x11 << 25),
+ (0x12 << 5) | (0x12 << 25),
+ (0x13 << 5) | (0x13 << 25),
+ (0x14 << 5) | (0x14 << 25)
+ };
+
+ writel_field(TDFI_RDLVL_RR, TDFI_RDLVL_RR_MSK, &mpmc_p->reg64);
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ writel_field(0 << 0, 7 << 0, phy_ctrl_reg6 + slice);
+ writel_field(0 << 3, 3 << 3, phy_ctrl_reg6 + slice);
+ writel_field(3 << 5, 7 << 5, phy_ctrl_reg6 + slice);
+ writel_field(2 << 8, 3 << 8, phy_ctrl_reg6 + slice);
+
+ writel_field(1 << 0, 7 << 0, phy_ctrl_reg7 + slice);
+ }
+
+ set_swlvl_mode(GATE_LVL);
+ swlvl_start();
+ wait_op_done();
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ gate_counter = 7;
+ set_gate_parms(++gate_counter, slice);
+
+ resp = read_resp(slice);
+ if (resp == 0) {
+ prelim_preamble_start = gate_counter;
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_rise_edge = gate_counter;
+ } else if (resp == 1) {
+ set_gate_parms_resp(&gate_counter, slice, 1);
+ prelim_preamble_start = gate_counter;
+
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_rise_edge = gate_counter;
+ }
+
+step_14:
+ while (prelim_rise_edge - prelim_preamble_start < MIN_1_8TH_CYCLE_PREAMBLE) {
+ set_gate_parms_resp(&gate_counter, slice, 1);
+ prelim_preamble_start = gate_counter;
+
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_rise_edge = gate_counter;
+ }
+
+ if (prelim_rise_edge - prelim_preamble_start >= MIN_1_8TH_CYCLE_PREAMBLE) {
+ set_gate_parms_resp(&gate_counter, slice, 1);
+ prelim_fall_edge = gate_counter;
+ }
+
+ if ((prelim_fall_edge - prelim_rise_edge < MIN_NO_OF_1_8TH_CYCLE) ||
+ (prelim_fall_edge - prelim_rise_edge > MAX_NO_OF_1_8TH_CYCLE)) {
+
+ prelim_preamble_start = gate_counter;
+
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_rise_edge = gate_counter;
+
+ goto step_14;
+ }
+
+ if ((prelim_fall_edge - prelim_rise_edge >= MIN_NO_OF_1_8TH_CYCLE) &&
+ (prelim_fall_edge - prelim_rise_edge <= MAX_NO_OF_1_8TH_CYCLE)) {
+
+ prelim_dqs_low_start = gate_counter;
+
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_dqs_low_end = gate_counter;
+ }
+
+ if ((prelim_dqs_low_end - prelim_dqs_low_start < MIN_NO_OF_1_8TH_CYCLE) ||
+ (prelim_dqs_low_end - prelim_dqs_low_start > MAX_NO_OF_1_8TH_CYCLE)) {
+
+ set_gate_parms_resp(&gate_counter, slice, 1);
+ prelim_preamble_start = gate_counter;
+
+ set_gate_parms_resp(&gate_counter, slice, 0);
+ prelim_rise_edge = gate_counter;
+
+ goto step_14;
+ }
+
+ if ((prelim_dqs_low_end - prelim_dqs_low_start >= MIN_NO_OF_1_8TH_CYCLE) &&
+ (prelim_dqs_low_end - prelim_dqs_low_start <= MAX_NO_OF_1_8TH_CYCLE)) {
+
+ final_gate_counter[slice] = prelim_rise_edge;
+ }
+
+ final_gate_counter[slice] -= 7;
+ writel_field((final_gate_counter[slice] / 8) << 20, 7 << 20, phy_ctrl_reg0 + slice);
+ prog_rdlvl_gate_delay(slice, final_gate_counter[slice] % 8);
+
+ swlvl_load();
+ wait_op_done();
+ }
+
+ swlvl_exit();
+ wait_op_done();
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ writel_field(phy_ctrl_reg6_dqs_assertval[final_gate_counter[slice] / 8],
+ (0x1F << 0) | (0x1F << 20), phy_ctrl_reg6 + slice);
+ writel_field(phy_ctrl_reg6_dqs_deassertval[final_gate_counter[slice] / 8],
+ (0x1F << 5) | (0x1F << 25), phy_ctrl_reg6 + slice);
+ }
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
new file mode 100644
index 0000000..db1a219
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static void prog_rdlvl_delay(u32 slice, u32 rdlvl_delay)
+{
+ u32 *rdlvl_delay_reg = &mpmc_p->reg81;
+ u32 shift;
+
+ rdlvl_delay_reg += (slice + 1) >> 1;
+ shift = (slice & 0x1) ? 0 : 16;
+ writel_field(rdlvl_delay << shift, 0xFFFF << shift, rdlvl_delay_reg);
+}
+
+u32 find_rdlvl_value(u32 *start, u32 *end)
+{
+ u32 edge_delta[2];
+ int diff;
+ u32 rdlvl_value;
+
+ edge_delta[0] = end[0] - start[0];
+ edge_delta[1] = end[1] - start[1];
+
+ if ((edge_delta[0] == 0) && (edge_delta[1] == 0)) {
+ if (start[0] != start[1])
+ goto error;
+ else
+ rdlvl_value = start[0];
+ } else if ((edge_delta[0] == 0) && (edge_delta[1] != 0)) {
+ if ((start[0] == start[1]) || (start[0] == (start[1] + 1)))
+ rdlvl_value = start[0];
+ else
+ goto error;
+ } else if ((edge_delta[0] != 0) && (edge_delta[1] == 0)) {
+ if ((start[1] == start[0]) || (start[1] == (start[0] + 1)))
+ rdlvl_value = start[1];
+ else
+ goto error;
+ } else {
+ diff = start[0] - start[1];
+ if (diff < 0)
+ diff = start[1] - start[0];
+
+ if ((start[1] == start[0]) && (edge_delta[0] > 2) && (edge_delta[1] > 2)) {
+ if (start[0] > 6)
+ rdlvl_value = start[0] + 1;
+ else
+ rdlvl_value = start[0] + 2;
+ } else {
+
+ if (start[1] == start[0]) {
+ rdlvl_value = start[1] + 1;
+ } else if (diff < 2) {
+ if ((edge_delta[0] == 1) && (edge_delta[1] == 1)) {
+ if (start[1] == (start[0] + 1))
+ rdlvl_value = start[1];
+ else if (start[0] == (start[1] + 1))
+ rdlvl_value = start[0];
+ else
+ goto error;
+ } else if (edge_delta[0] == edge_delta[1]) {
+ if (start[1] == (start[0] + 1))
+ rdlvl_value = start[1] + 1;
+ else if (start[0] == (start[1] + 1))
+ rdlvl_value = start[0] + 1;
+ else
+ goto error;
+ } else if (edge_delta[0] > edge_delta[1]) {
+ if (start[1] == (start[0] + 1))
+ rdlvl_value = start[0] + 2;
+ else if (start[0] == (start[1] + 1)) {
+ if (edge_delta[1] == 1)
+ rdlvl_value = start[1] + 1;
+ else
+ rdlvl_value = start[1] + 2;
+ } else
+ goto error;
+ } else {
+ if (start[0] == (start[1] + 1))
+ rdlvl_value = start[1] + 2;
+ else if (start[1] == (start[0] + 1)) {
+ if (edge_delta[0] == 1)
+ rdlvl_value = start[0] + 1;
+ else
+ rdlvl_value = start[0] + 2;
+ } else
+ goto error;
+ }
+ } else
+ goto error;
+ }
+ }
+
+ /* if allowed from actual read leveling data, adjust read phase to the default centered value 8 */
+ if ((rdlvl_value == 9) && (start[0] < 9) && (start[1] < 9))
+ return --rdlvl_value;
+ else if ((rdlvl_value == 7) && (end[0] > 7) && (end[1] > 7))
+ return ++rdlvl_value;
+ else
+ return rdlvl_value;
+
+error:
+ /* loop infinitly on read levelling error else it gets un-noticed */
+ while (1)
+ ;
+
+ /*
+ * other possibility is to reset the system
+ * in case of a leveling error
+ */
+ reset_cpu(0);
+}
+
+#if defined(CONFIG_DDR2)
+void ddr2_lvl_read(void)
+{
+ u32 slice;
+ int RDLVL_DELAY_VALUE[5] = {8, 8, 8, 8, 8};
+
+ RDLVL_DELAY_VALUE[0] = RDLVL_DELAY_VALUE_0;
+ RDLVL_DELAY_VALUE[1] = RDLVL_DELAY_VALUE_1;
+ RDLVL_DELAY_VALUE[2] = RDLVL_DELAY_VALUE_2;
+ RDLVL_DELAY_VALUE[3] = RDLVL_DELAY_VALUE_3;
+ RDLVL_DELAY_VALUE[4] = RDLVL_DELAY_VALUE_4;
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++)
+ prog_rdlvl_delay(slice, RDLVL_DELAY_VALUE[slice]);
+}
+
+#elif defined(CONFIG_DDR3)
+void ddr3_lvl_read(void)
+{
+ u8 resp_array[DATA_SLICE_MAX][RDLVL_DELAY_VALS][2];
+ u32 i, j, k;
+ u32 count = 0;
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+ u32 *phy_ctrl_reg2 = &mpmc_p->reg135;
+ u32 *phy_ctrl_reg3 = &mpmc_p->reg140;
+ u32 slice, rdlvl_delay, start_point_found, rdlvl_edge;
+ u32 delay_vals;
+ u32 start_point_0[2], end_point_0[2];
+
+ writel_field(0xffff, 0xffff, &mpmc_p->reg182);
+ writel_field(0x10 << 16, 0xff << 16, &mpmc_p->reg64);
+ writel_field(0x12 << 8, 0xff << 8, &mpmc_p->reg59);
+
+ for (i = 0; i < DATA_SLICE_MAX; i++)
+ for (j = 0; j < RDLVL_DELAY_VALS; j++)
+ for (k = 0; k < 2; k++)
+ resp_array[i][j][k] = 0x0;
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ writel_field(0x21 << 14, 0x3F << 14, phy_ctrl_reg0 + slice);
+ writel_field(0x21 << 8, 0x3F << 8, phy_ctrl_reg0 + slice);
+
+ writel_field(0x1 << 24, 0x3F << 24, phy_ctrl_reg2 + slice);
+ writel_field(0x1 << 24, 0x3F << 24, phy_ctrl_reg3 + slice);
+ }
+
+ set_swlvl_mode(READ_LVL);
+ swlvl_start();
+ wait_op_done();
+
+ swlvl_load();
+ wait_op_done();
+ for (count = 0; count < 100; count++) {
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ for (rdlvl_edge = 0; rdlvl_edge <= 1; rdlvl_edge++) {
+ writel_field(rdlvl_edge << 0, 1 << 0, &mpmc_p->reg7);
+ for (delay_vals = 0; delay_vals < RDLVL_DELAY_VALS; delay_vals++) {
+ prog_rdlvl_delay(slice, delay_vals + RDLVL_DELAY_INIT);
+ swlvl_load();
+ wait_op_done();
+
+ resp_array[slice][delay_vals][rdlvl_edge] |= read_resp(slice);
+ }
+ }
+ }
+ }
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ for (rdlvl_edge = 0; rdlvl_edge <= 1; rdlvl_edge++) {
+ start_point_found = 0;
+ for (delay_vals = 0; delay_vals < RDLVL_DELAY_VALS; delay_vals++) {
+ if ((resp_array[slice][delay_vals][rdlvl_edge] == 0) && !start_point_found) {
+ start_point_0[rdlvl_edge] = delay_vals + RDLVL_DELAY_INIT;
+ start_point_found = 1;
+ }
+ if ((resp_array[slice][delay_vals][rdlvl_edge] != 0) && start_point_found) {
+ end_point_0[rdlvl_edge] = delay_vals + RDLVL_DELAY_INIT - 1;
+ break;
+ }
+ }
+ }
+
+ rdlvl_delay = find_rdlvl_value(start_point_0, end_point_0);
+ prog_rdlvl_delay(slice, rdlvl_delay);
+ swlvl_load();
+ wait_op_done();
+ }
+ swlvl_exit();
+ wait_op_done();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
new file mode 100644
index 0000000..fdb005f
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
@@ -0,0 +1,608 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static u32 source_sel_cal(u32 pattern)
+{
+ if ((pattern & 0xE1) == 0x60)
+ return 1;
+ else if ((pattern & 0xF0) == 0x30)
+ return 2;
+ else if ((pattern & 0x78) == 0x18)
+ return 3;
+ else if ((pattern & 0x3C) == 0x0C)
+ return 4;
+ else if ((pattern & 0x1E) == 0x06)
+ return 5;
+ else if ((pattern & 0x0F) == 0x03)
+ return 6;
+ else if ((pattern & 0x87) == 0x81)
+ return 7;
+ else
+ return 0;
+}
+
+static void reset_phy_ctrl_reg(u32 *reg)
+{
+ int i;
+
+ writel(readl(reg) | 0x1, reg);
+ for (i = 0; i < PHY_CTRL_DELAY; i++)
+ ;
+ writel(readl(reg) & ~0x1, reg);
+}
+
+static void prog_wrlvl_delay(u32 slice, u32 wrlvl_delay)
+{
+ u32 *wrlvl_delay_reg = &mpmc_p->reg100;
+ u32 shift;
+
+ wrlvl_delay_reg += slice >> 1;
+ shift = (slice & 0x1) ? 16 : 0;
+ writel_field(wrlvl_delay << shift, 0xFFFF << shift, wrlvl_delay_reg);
+}
+
+static u32 get_wrlvl_start(u32 wrlvl_base_off)
+{
+ u32 cal_clk_byte_patt, cal_ref_byte_patt;
+ u32 clk_source_sel_cal_pre, ref_source_sel_cal_pre;
+ int wrlvl_base, wrlvl_start;
+
+ writel_field(wrlvl_base_off << 20, 7 << 20, &mpmc_p->reg129);
+ cal_clk_byte_patt = readl_field(0, 0xFF, &mpmc_p->reg181);
+ cal_ref_byte_patt = readl_field(8, 0xFF << 8, &mpmc_p->reg181);
+
+ clk_source_sel_cal_pre = source_sel_cal(cal_clk_byte_patt);
+ ref_source_sel_cal_pre = source_sel_cal(cal_ref_byte_patt);
+
+ wrlvl_base = ref_source_sel_cal_pre - clk_source_sel_cal_pre;
+ wrlvl_base &= 7;
+ wrlvl_start = wrlvl_base - wrlvl_base_off;
+ wrlvl_start &= 7;
+
+ return wrlvl_start;
+}
+
+static void set_wrlvldelay(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+ u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+ u32 wrlvl_delay, slice, start_search;
+ u32 start_wrlvl_delay_mod, i;
+ u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+ (0 << 0) | (1 << 3),
+ (0 << 0) | (2 << 3),
+ (0 << 0) | (1 << 3),
+ (0 << 0) | (2 << 3)
+ };
+ u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+ (0 << 5) | (2 << 8),
+ (0 << 5) | (1 << 8),
+ (0 << 5) | (2 << 8),
+ (0 << 5) | (1 << 8)
+ };
+ u8 resp_total[DATA_SLICE_MAX][WRLVL_DELAY_MAX];
+
+ /*
+ * Start write leveling operation to find the wrlvldelay parameters for
+ * each data slice
+ */
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ swlvl_start();
+ wait_op_done();
+
+ for (wrlvl_delay = 0; wrlvl_delay < WRLVL_DELAY_MAX; wrlvl_delay++) {
+ start_wrlvl_delay_mod = wrlvl_start + wrlvl_delay;
+ reset_phy_ctrl_reg(phy_ctrl_reg0 + slice);
+ prog_wrlvl_delay(slice, wrlvl_delay);
+
+ writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+ DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+ DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ resp_total[slice][wrlvl_delay] = 0;
+
+ for (i = 0; i < 4; i++) {
+ swlvl_load();
+ wait_op_done();
+
+ resp_total[slice][wrlvl_delay] += read_resp(slice);
+ }
+ }
+
+ start_search = 0;
+ for (wrlvl_delay = 0; wrlvl_delay < WRLVL_DELAY_MAX; wrlvl_delay++) {
+ if ((resp_total[slice][wrlvl_delay] < 4) && !start_search)
+ start_search = 1;
+ if ((resp_total[slice][wrlvl_delay] == 4) && start_search)
+ break;
+ }
+
+ /*
+ * added 1 phase to DQS position
+ * original was final_wrlvl_delay[slice] = wrlvl_delay - 1
+ */
+ final_wrlvl_delay[slice] = wrlvl_delay;
+
+ prog_wrlvl_delay(slice, final_wrlvl_delay[slice]);
+ start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+ writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+ DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+ DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ swlvl_load();
+ wait_op_done();
+
+ swlvl_exit();
+ wait_op_done();
+ }
+}
+
+static u32 get_match_pre(u32 slice)
+{
+ u32 *obs_reg = &mpmc_p->reg175;
+ u32 dqs_byte_patt_mux_dqs = (readl(obs_reg + slice) >> 8) & 0xFF;
+
+ if ((dqs_byte_patt_mux_dqs & 0xE1) == 0x60)
+ return 1;
+ else if ((dqs_byte_patt_mux_dqs & 0xF0) == 0x30)
+ return 2;
+ else if ((dqs_byte_patt_mux_dqs & 0x78) == 0x18)
+ return 3;
+ else if ((dqs_byte_patt_mux_dqs & 0x3C) == 0x0C)
+ return 4;
+ else if ((dqs_byte_patt_mux_dqs & 0x1E) == 0x06)
+ return 5;
+ else if ((dqs_byte_patt_mux_dqs & 0x0F) == 0x03)
+ return 6;
+ else if ((dqs_byte_patt_mux_dqs & 0x87) == 0x81)
+ return 7;
+ else
+ return 0;
+}
+
+static u32 get_match0_pre(u32 slice)
+{
+ u32 *obs_reg = &mpmc_p->reg175;
+ u32 dqs_byte_patt_mux_data = (readl(obs_reg + slice) >> 16) & 0xFF;
+
+ if ((dqs_byte_patt_mux_data & 0x1F) == 0x00)
+ return 8;
+ else if ((dqs_byte_patt_mux_data & 0xF8) == 0xF8)
+ return 9;
+ else if ((dqs_byte_patt_mux_data & 0xF8) == 0x78)
+ return 1;
+ else if ((dqs_byte_patt_mux_data & 0xFC) == 0x3C)
+ return 2;
+ else if ((dqs_byte_patt_mux_data & 0xFE) == 0x1E)
+ return 3;
+ else if ((dqs_byte_patt_mux_data & 0xFF) == 0x0F)
+ return 4;
+ else if ((dqs_byte_patt_mux_data & 0x7F) == 0x07)
+ return 5;
+ else if ((dqs_byte_patt_mux_data & 0x3F) == 0x03)
+ return 6;
+ else if ((dqs_byte_patt_mux_data & 0x1F) == 0x01)
+ return 7;
+ else
+ return 0xF;
+}
+
+static u32 get_match1_pre(u32 slice)
+{
+ u32 *obs_reg = &mpmc_p->reg170;
+ u32 dqs_byte_patt_mux_data1 = (readl(obs_reg + slice) >> 23) & 0xFF;
+
+ if ((dqs_byte_patt_mux_data1 & 0x1F) == 0x00)
+ return 8;
+ else if ((dqs_byte_patt_mux_data1 & 0xF8) == 0xF8)
+ return 9;
+ else if ((dqs_byte_patt_mux_data1 & 0xF8) == 0x78)
+ return 1;
+ else if ((dqs_byte_patt_mux_data1 & 0xFC) == 0x3C)
+ return 2;
+ else if ((dqs_byte_patt_mux_data1 & 0xFE) == 0x1E)
+ return 3;
+ else if ((dqs_byte_patt_mux_data1 & 0xFF) == 0x0F)
+ return 4;
+ else if ((dqs_byte_patt_mux_data1 & 0x7F) == 0x07)
+ return 5;
+ else if ((dqs_byte_patt_mux_data1 & 0x3F) == 0x03)
+ return 6;
+ else if ((dqs_byte_patt_mux_data1 & 0x1F) == 0x01)
+ return 7;
+ else
+ return 0xF;
+}
+
+static void set_dqs_parms(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+ u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+ u32 *phy_ctrl_reg4 = &mpmc_p->reg145;
+ u32 *phy_ctrl_reg5 = &mpmc_p->reg150;
+ u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+ u32 *phy_ctrl_reg7 = &mpmc_p->reg160;
+
+ u32 wr_dq_a_timing_reg, start_wrlvl_delay_mod, slice, dqtim;
+ u32 phy_clk_phase_match_pre, dq_clk_phase_match0_pre, dq_clk_phase_match1_pre;
+ u32 dq_clk_phase_match_pre;
+
+ u32 dqs_dq_clk_phase_match_delta;
+
+ u8 dqs_dq_clk_phase_match_delta_value[DATA_SLICE_MAX];
+ u8 dqs_dq_clk_phase_match_delta_offset[DATA_SLICE_MAX];
+
+ u32 dqs_dq_clk_phase_match_delta_expected;
+
+ u8 start_wrlvl_delay_mod_value[DATA_SLICE_MAX];
+ u8 start_wrlvl_delay_mod_offset_value[DATA_SLICE_MAX];
+
+ static u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+ (0 << 0) | (1 << 3),
+ (0 << 0) | (2 << 3),
+ (1 << 0) | (1 << 3),
+ (1 << 0) | (2 << 3)
+ };
+ static u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+ (0 << 5) | (1 << 8),
+ (0 << 5) | (2 << 8),
+ (1 << 5) | (1 << 8),
+ (1 << 5) | (2 << 8)
+ };
+ static u32 phy_ctrl_reg1_dqsoe_assertval[] = {
+ (0 << 10) | (1 << 13),
+ (0 << 10) | (2 << 13),
+ (1 << 10) | (1 << 13),
+ (1 << 10) | (2 << 13)
+ };
+ static u32 phy_ctrl_reg1_dqsoe_deassertval[] = {
+ (1 << 15) | (2 << 18),
+ (2 << 15) | (1 << 18),
+ (2 << 15) | (2 << 18),
+ (3 << 15) | (1 << 18)
+ };
+ static u32 phy_ctrl_reg6_dqs_assertval[] = {
+ (0 << 10) | (1 << 13),
+ (0 << 10) | (2 << 13),
+ (1 << 10) | (1 << 13),
+ (1 << 10) | (2 << 13)
+ };
+ static u32 phy_ctrl_reg6_dqs_deassertval[] = {
+ (1 << 15) | (2 << 18),
+ (2 << 15) | (1 << 18),
+ (2 << 15) | (2 << 18),
+ (3 << 15) | (1 << 18)
+ };
+ static u16 phy_ctrl_reg5_assertval[4][15] = {
+ {0, 0, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09, 0x09, 0x11},
+ {0, 0, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09, 0x09},
+ {0, 0, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09},
+ {0, 0, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09}
+ };
+ static u16 phy_ctrl_reg5_deassertval[4][15] = {
+ {0, 0, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120, 0x120, 0x220},
+ {0, 0, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120, 0x120},
+ {0, 0, 0x000, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120},
+ {0, 0, 0x000, 0x000, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120}
+ };
+ static u32 phy_ctrl_reg1_assertval[] = {
+ (0 << 20) | (1 << 23),
+ (0 << 20) | (2 << 23),
+ (1 << 20) | (1 << 23),
+ (1 << 20) | (2 << 23)
+ };
+ static u32 phy_ctrl_reg1_deassertval[] = {
+ (1 << 25) | (2 << 28),
+ (2 << 25) | (1 << 28),
+ (2 << 25) | (2 << 28),
+ (3 << 25) | (1 << 28)
+ };
+ static u32 phy_ctrl_reg7_assertval[] = {
+ (0 << 18) | (1 << 21),
+ (0 << 18) | (2 << 21),
+ (1 << 18) | (1 << 21),
+ (1 << 18) | (2 << 21)
+ };
+ static u32 phy_ctrl_reg7_deassertval[] = {
+ (1 << 23) | (2 << 26),
+ (2 << 23) | (1 << 26),
+ (2 << 23) | (2 << 26),
+ (3 << 23) | (1 << 26)
+ };
+
+ /*
+ * first for cycle
+ * data collection on dqs_dq_clk_phase_match_delta_value[slice]
+ * data collection on start_wrlvl_delay_mod_value[slice]
+ */
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+ start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+ writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+ DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+ DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ writel_field(phy_ctrl_reg1_dqsoe_assertval[start_wrlvl_delay_mod/4],
+ DQSOE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsoe_deassertval[start_wrlvl_delay_mod/4],
+ DQSOE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ writel_field(phy_ctrl_reg6_dqs_assertval[start_wrlvl_delay_mod/4],
+ REG6_DQS_ASSERT_MSK, phy_ctrl_reg6 + slice);
+ writel_field(phy_ctrl_reg6_dqs_deassertval[start_wrlvl_delay_mod/4],
+ REG6_DQS_DEASSERT_MSK, phy_ctrl_reg6 + slice);
+
+ phy_clk_phase_match_pre = get_match_pre(slice);
+ dq_clk_phase_match0_pre = get_match0_pre(slice);
+ dq_clk_phase_match1_pre = get_match1_pre(slice);
+
+ if ((dq_clk_phase_match0_pre & 0x8) == 0)
+ dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+ else
+ dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+
+ phy_clk_phase_match_pre &= 0xF;
+
+ if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+ dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+ else
+ dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+ dqs_dq_clk_phase_match_delta &= 0xF;
+
+ if (dqs_dq_clk_phase_match_delta > 3) {
+ /* if delta is too high recalculate */
+ if ((dq_clk_phase_match0_pre & 0x8) == 0)
+ dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+ else
+ dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+
+ phy_clk_phase_match_pre &= 0xF;
+
+ if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+ dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+ else
+ dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+ dqs_dq_clk_phase_match_delta &= 0xF;
+
+ if (dqs_dq_clk_phase_match_delta > 3)
+ hang();
+ }
+
+ dqs_dq_clk_phase_match_delta_value[slice] = dqs_dq_clk_phase_match_delta;
+ start_wrlvl_delay_mod_value[slice] = start_wrlvl_delay_mod;
+ }
+
+ /* dqs_dq_clk_phase_match_delta_expected calculation on slices 0,1,2 */
+ dqs_dq_clk_phase_match_delta_expected = (unsigned int) (((dqs_dq_clk_phase_match_delta_value[0] +
+ dqs_dq_clk_phase_match_delta_value[1] +
+ dqs_dq_clk_phase_match_delta_value[2] + (3/2))/3));
+
+ /*
+ * second for cycle
+ * start_wrlvl_delay_mod_offset_value calculation
+ */
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+ dqs_dq_clk_phase_match_delta_offset[slice] =
+ (u32) (dqs_dq_clk_phase_match_delta_expected -
+ dqs_dq_clk_phase_match_delta_value[slice]);
+
+ start_wrlvl_delay_mod_offset_value[slice] =
+ (u32) (start_wrlvl_delay_mod_value[slice] -
+ dqs_dq_clk_phase_match_delta_offset[slice]);
+ }
+
+ /* third for cycle, write leveling settings */
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+ start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+ writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+ DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+ DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ writel_field(phy_ctrl_reg1_dqsoe_assertval[start_wrlvl_delay_mod/4],
+ DQSOE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsoe_deassertval[start_wrlvl_delay_mod/4],
+ DQSOE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+ writel_field(phy_ctrl_reg6_dqs_assertval[start_wrlvl_delay_mod/4],
+ REG6_DQS_ASSERT_MSK, phy_ctrl_reg6 + slice);
+ writel_field(phy_ctrl_reg6_dqs_deassertval[start_wrlvl_delay_mod/4],
+ REG6_DQS_DEASSERT_MSK, phy_ctrl_reg6 + slice);
+
+ phy_clk_phase_match_pre = get_match_pre(slice);
+ dq_clk_phase_match0_pre = get_match0_pre(slice);
+ dq_clk_phase_match1_pre = get_match1_pre(slice);
+
+ if ((dq_clk_phase_match0_pre & 0x8) == 0)
+ dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+ else
+ dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+
+ phy_clk_phase_match_pre &= 0xF;
+
+ if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+ dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+ else
+ dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+ dqs_dq_clk_phase_match_delta &= 0xF;
+
+ if (dqs_dq_clk_phase_match_delta > 3) {
+ /* if delta is too high recalculate */
+ if ((dq_clk_phase_match0_pre & 0x8) == 0)
+ dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+ else
+ dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+
+ phy_clk_phase_match_pre &= 0xF;
+
+ if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+ dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+ else
+ dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+ dqs_dq_clk_phase_match_delta &= 0xF;
+
+ if (dqs_dq_clk_phase_match_delta > 3)
+ hang();
+ }
+
+ /* here we use start_wrlvl_delay_mod_offset_value[slice], phy_ctrl_reg4 and phy_ctrl_reg5 are related to DQ phase */
+ dqtim = (start_wrlvl_delay_mod_offset_value[slice] - 2) & 0x7;
+ wr_dq_a_timing_reg = (dqtim << 0) | (dqtim << 3) | (dqtim << 6) | (dqtim << 9) |
+ (dqtim << 12) | (dqtim << 15) | (dqtim << 18) | (dqtim << 21) | (dqtim << 24);
+
+ writel(wr_dq_a_timing_reg, phy_ctrl_reg4 + slice);
+
+ writel_field(phy_ctrl_reg5_assertval[dqs_dq_clk_phase_match_delta][start_wrlvl_delay_mod_offset_value[slice]],
+ REG5_ASSERT_MSK, phy_ctrl_reg5 + slice);
+ writel_field(phy_ctrl_reg5_deassertval[dqs_dq_clk_phase_match_delta][start_wrlvl_delay_mod_offset_value[slice]],
+ REG5_DEASSERT_MSK, phy_ctrl_reg5 + slice);
+
+ /* here we use start_wrlvl_delay_mod, phy_ctrl_reg1 and phy_ctrl_reg7 are related to DQS phase */
+ writel_field(phy_ctrl_reg1_assertval[start_wrlvl_delay_mod/4],
+ REG1_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_deassertval[start_wrlvl_delay_mod/4],
+ REG1_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg7_assertval[start_wrlvl_delay_mod/4],
+ REG7_ASSERT_MSK, phy_ctrl_reg7 + slice);
+ writel_field(phy_ctrl_reg7_deassertval[start_wrlvl_delay_mod/4],
+ REG7_DEASSERT_MSK, phy_ctrl_reg7 + slice);
+ }
+}
+
+#if defined(CONFIG_DDR2)
+static void set_wrlvldelay_ddr2(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+ u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+ u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+ u32 slice;
+ u32 start_wrlvl_delay_mod;
+ u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+ (0 << 0) | (1 << 3),
+ (0 << 0) | (2 << 3),
+ (0 << 0) | (1 << 3),
+ (0 << 0) | (2 << 3)
+ };
+ u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+ (0 << 5) | (2 << 8),
+ (0 << 5) | (1 << 8),
+ (0 << 5) | (2 << 8),
+ (0 << 5) | (1 << 8)
+ };
+ int WRLVL_DELAY_VALUE[5] = {2, 2, 2, 2, 2};
+
+ WRLVL_DELAY_VALUE[0] = WRLVL_DELAY_VALUE_0;
+ WRLVL_DELAY_VALUE[1] = WRLVL_DELAY_VALUE_1;
+ WRLVL_DELAY_VALUE[2] = WRLVL_DELAY_VALUE_2;
+ WRLVL_DELAY_VALUE[3] = WRLVL_DELAY_VALUE_3;
+ WRLVL_DELAY_VALUE[4] = WRLVL_DELAY_VALUE_4;
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+ reset_phy_ctrl_reg(phy_ctrl_reg0 + slice);
+
+ final_wrlvl_delay[slice] = WRLVL_DELAY_VALUE[slice];
+
+ prog_wrlvl_delay(slice, final_wrlvl_delay[slice]);
+ start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+ writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+ DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+ writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+ DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+ }
+}
+
+void ddr2_lvl_write(void)
+{
+
+ int wrlvl_start;
+ u32 final_wrlvl_delay[DATA_SLICE_MAX];
+ u32 wrlvl_base_offset_reg = 0;
+
+ wrlvl_base_offset_reg = WRLVL_BASE_OFFSET_REG_VALUE;
+
+ /* enable also wrlvl_reg_en, rdlvl_gate_reg_en, rdlvl_reg_en when START MPMC parameter is enabled */
+ writel(readl(&mpmc_p->reg15) | WRLVL_REG_EN, &mpmc_p->reg15);
+ writel(readl(&mpmc_p->reg8) | RDLVL_GATE_REG_EN, &mpmc_p->reg8);
+ writel(readl(&mpmc_p->reg9) | RDLVL_REG_EN, &mpmc_p->reg9);
+
+ wrlvl_start = get_wrlvl_start(wrlvl_base_offset_reg);
+
+ set_wrlvldelay_ddr2(wrlvl_start, final_wrlvl_delay);
+
+ set_dqs_parms(wrlvl_start, final_wrlvl_delay);
+}
+#elif defined(CONFIG_DDR3)
+
+void ddr3_lvl_write(void)
+{
+ int wrlvl_start;
+ u32 wrlvl_base_offset_reg;
+ u32 final_wrlvl_delay[DATA_SLICE_MAX];
+ u32 wrlvl_base_offset_check;
+ u32 slice;
+
+ wrlvl_base_offset_reg = 2; /* start from default value */
+
+ do {
+ set_swlvl_mode(WRITE_LVL);
+ swlvl_start();
+ wait_op_done();
+
+ wrlvl_start = get_wrlvl_start(wrlvl_base_offset_reg);
+ swlvl_exit();
+ wait_op_done();
+
+ /* Set wrlvl_delay parameters through write leveling */
+ set_wrlvldelay(wrlvl_start, final_wrlvl_delay);
+
+ wrlvl_base_offset_check = 0;
+
+ for (slice = 0; slice < DATA_SLICE_MAX; slice++)
+ if (final_wrlvl_delay[slice] >= 8)
+ wrlvl_base_offset_check++;
+
+ if (wrlvl_base_offset_check > 0)
+ wrlvl_base_offset_reg++;
+
+ if (wrlvl_base_offset_reg >= 8)
+ wrlvl_base_offset_reg = 0;
+
+ } while ((wrlvl_base_offset_check != 0));
+
+ set_dqs_parms(wrlvl_start, final_wrlvl_delay);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c b/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
new file mode 100644
index 0000000..501c4d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
@@ -0,0 +1,210 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/mpmc.h>
+
+static void pll_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 usbphycfg;
+
+ /* Initialize PLLs */
+ writel(SPEAR1340_FREQ_1000, &misc_p->pll1_frq);
+ writel(readl(&misc_p->pll1_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll1_ctr);
+
+ writel(SPEAR1340_FREQ_125, &misc_p->pll2_frq);
+ writel(readl(&misc_p->pll2_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll2_ctr);
+
+ writel(SPEAR1340_FREQ_332, &misc_p->pll3_frq);
+ writel(readl(&misc_p->pll3_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll3_ctr);
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+ writel(SPEAR1340_FREQ_400, &misc_p->pll4_frq);
+#elif defined(CONFIG_SPEAR_DDRFREQ533)
+ writel(SPEAR1340_FREQ_533, &misc_p->pll4_frq);
+#else
+#error Define one of the valid DDR frequency(CONFIG_SPEAR_DDRFREQ[533/400])
+#endif
+ /* strobing required for pll4 */
+ writel(0x60A, &misc_p->pll4_ctr);
+ writel(0x60E, &misc_p->pll4_ctr);
+ writel(0x606, &misc_p->pll4_ctr);
+ writel(0x60E, &misc_p->pll4_ctr);
+
+ usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+ usbphycfg &= ~(SPEAR1340_COMMON_PWDN | SPEAR1340_USBPHY_POR);
+ usbphycfg |= SPEAR1340_USBPHY_RST;
+ writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+ while (!(readl(&misc_p->usbphy_gen_cfg) & SPEAR1340_USB_PLL_LOCK))
+ ;
+
+ /* AHB Master Burst is not supported for SPEAr1340 */
+ usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+
+ usbphycfg |= SPEAR1340_AUTOPPD_ON_OVRCURR | \
+ SPEAR1340_UTMI_XFER_RST0 | \
+ SPEAR1340_UTMI_XFER_RST1 | \
+ SPEAR1340_UTMI_XFER_RST2;
+
+ writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+ /* wait for pll locks */
+ while (!(readl(&misc_p->pll1_ctr) & SPEAR1340_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll2_ctr) & SPEAR1340_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll3_ctr) & SPEAR1340_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll4_ctr) & SPEAR1340_PLLLOCK))
+ ;
+}
+
+static void sys_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 sysclkctrl;
+
+ /* Set system state to SLOW */
+ sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+ sysclkctrl &= ~SPEAR1340_SYS_MODE_MASK;
+ sysclkctrl |= SPEAR1340_XTAL_TIMEOUT_ENB | \
+ SPEAR1340_PLL_TIMEOUT_ENB | \
+ SPEAR1340_SYS_MODE_REQ_SLOW;
+ writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+ writel(SPEAR1340_PLL_TIM, &misc_p->sys_clk_plltimer);
+ writel(SPEAR1340_OSCI_TIM, &misc_p->sys_clk_oscitimer);
+
+ /* Initialize PLLs */
+ pll_init();
+
+ /* Set system state to NORMAL */
+ sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+ sysclkctrl &= ~SPEAR1340_SYS_MODE_MASK;
+ sysclkctrl |= SPEAR1340_XTAL_TIMEOUT_ENB | \
+ SPEAR1340_PLL_TIMEOUT_ENB | \
+ SPEAR1340_SYS_MODE_REQ_NORMAL;
+ writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+ /* Wait for system to switch to normal mode */
+ while ((readl(&misc_p->sys_clk_ctrl) & SPEAR1340_SYS_STATE_MASK) !=
+ SPEAR1340_SYS_STATE_NORMAL)
+ ;
+#if defined(CONFIG_C3)
+ writel(readl(&misc_p->perip1_clk_enb) | SPEAR1340_C3_CLKEN,
+ &misc_p->perip1_clk_enb);
+#endif
+}
+
+static void ddr_clock_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip_clkcfg, perip2_clkenb, perip2_swrst;
+
+ perip_clkcfg = readl(&misc_p->perip_clk_cfg);
+ perip_clkcfg |= SPEAR1340_MPMCCLKPLL4;
+ writel(perip_clkcfg, &misc_p->perip_clk_cfg);
+
+ perip2_clkenb = readl(&misc_p->perip2_clk_enb);
+ perip2_clkenb |= SPEAR1340_DDRCTRL_CLKEN | SPEAR1340_DDRCORE_CLKEN;
+ writel(perip2_clkenb, &misc_p->perip2_clk_enb);
+
+ /*
+ * MISC compensation_ddr_cfg before mpmc reset
+ * disable automatic ddr pad compensation
+ * use fixed comzcp=0000 and comzcn=0000
+ */
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+
+ perip2_swrst = readl(&misc_p->perip2_sw_rst);
+ perip2_swrst |= SPEAR1340_DDRCTRL_RST | SPEAR1340_DDRCORE_RST;
+ writel(perip2_swrst, &misc_p->perip2_sw_rst);
+
+ perip2_swrst = readl(&misc_p->perip2_sw_rst);
+ perip2_swrst &= ~(SPEAR1340_DDRCTRL_RST | SPEAR1340_DDRCORE_RST);
+ writel(perip2_swrst, &misc_p->perip2_sw_rst);
+}
+
+static void ddr_pad_compensation(u8 enable)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ if (enable) {
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+
+ /* wait for comzcrdy done */
+ while (!(readl(&misc_p->compensation_ddr_cfg) & 0x1))
+ ;
+ } else {
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ }
+}
+
+void ddr_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ /* Clock related settings for DDR */
+ ddr_clock_init();
+
+ /* Initialize mpmc register values */
+ spear13xx_mpmc_init((u32 *)CONFIG_SYS_MPMC_BASE, CONFIG_SPEAR_MPMCREGS);
+
+ writel(SPEAR1340_PAD_VREF | SPEAR1340_DATA_PROGB | \
+ SPEAR1340_DATA_PROGA | SPEAR1340_CLK_PROGB | \
+ SPEAR1340_CLK_PROGA | SPEAR1340_CTRL_PROGB | \
+ SPEAR1340_CTRL_PROGA,
+ &misc_p->ddr_pad_cfg);
+
+ ddr_pad_compensation(0);
+ spear13xx_ddr_level();
+ ddr_pad_compensation(1);
+}
+
+void soc_init(void)
+{
+ struct spear1340_misc_regs *const misc_p =
+ (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ /* Initialize PLLs */
+ sys_init();
+
+ /* Enable IPs (release reset) */
+ writel(SPEAR1340_PERIPH1_RST_ALL, &misc_p->perip1_sw_rst);
+ writel(SPEAR1340_PERIPH2_RST_ALL, &misc_p->perip2_sw_rst);
+ writel(SPEAR1340_PERIPH3_RST_ALL, &misc_p->perip3_sw_rst);
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
new file mode 100644
index 0000000..49b6043
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <post.h>
+#include <asm/io.h>
+#include <asm/arch/c3.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static void spear13xx_init(void)
+{
+ /*
+ * Enable the filtering at L2 cache controller level.
+ * This code limits the address range which can be accessed through the
+ * two ports coming out of ARM core.
+ *
+ * Port 0 access -> All - (Port 1 access range)
+ * Port 1 access -> 0x0 - 0x4000,0000 (1GB) all DDR space
+ * available on evaluation board
+ */
+
+ /* L2 cache controller filtering registers */
+ writel(0x40000000, CONFIG_SYS_L2CACHE_BASE + 0xC04);
+ writel(0x00000000 | 0x1, CONFIG_SYS_L2CACHE_BASE + 0xC00);
+
+ cpu2_wake();
+
+ cleanup_before_linux();
+}
+
+void spear13xx_mpmc_init(u32 *mpmcbase, u32 reg_num)
+{
+ u32 i;
+ u32 *mpmc_reg_p = mpmcbase;
+ u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+ for (i = 0; i < reg_num; i++, mpmc_reg_p++, mpmc_val_p++)
+ writel(*mpmc_val_p, mpmc_reg_p);
+
+ mpmc_reg_p = mpmcbase;
+
+ /*
+ * Enable default DDR pad termination settings during read operations
+ * Modify MPMC registers 160-164
+ */
+ for (i = 160; i <= 164; i++)
+ writel((readl(&mpmc_reg_p[i]) & ~0x3FFFF) | 0x03219,
+ &mpmc_reg_p[i]);
+
+ /*
+ * MPMC register25 rewrite
+ * MPMC controller start
+ */
+ writel(0x03070700, &mpmc_reg_p[25]);
+ writel(0x01000101, &mpmc_reg_p[11]);
+
+ while (!(readl(&mpmc_reg_p[105]) & 0x200))
+ ;
+}
+
+void spear13xx_ddr_level(void)
+{
+#if defined(CONFIG_DDR2)
+ ddr2_lvl_write();
+ ddr2_lvl_read();
+ ddr2_lvl_gatetrn();
+#elif defined(CONFIG_DDR3)
+ ddr3_lvl_write();
+ ddr3_lvl_gatetrn();
+ ddr3_lvl_read();
+#endif
+}
+
+static void spear13xx_ddrecc_init(void)
+{
+ /*
+ * The complete memory has to be initialized so that the ECC DDR gets
+ * populated and it starts working
+ *
+ * There are two ways to handle this
+ * - Through CPU. Cache has to be enabled to make it faster.
+ * - Through accelarator (C3)
+ */
+#if defined(CONFIG_DDR_ECC_ENABLE)
+ u32 ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
+ u32 *mpmc_reg_p = (u32 *)CONFIG_SYS_MPMC_BASE;
+ u32 reg18;
+
+ reg18 = readl(&mpmc_reg_p[18]);
+ reg18 &= ~MPMC_REG18_ECC_MASK;
+ reg18 |= MPMC_REG18_ECC_CORR_ON;
+ writel(reg18, &mpmc_reg_p[18]);
+
+ while ((readl(&mpmc_reg_p[18]) & MPMC_REG18_ECC_MASK) !=
+ MPMC_REG18_ECC_CORR_ON)
+ ;
+#if defined(CONFIG_C3)
+ c3_init();
+ c3_memset((void *)0, 0, ram_size);
+#else
+#error Define CONFIG_C3 for DDR ECC support
+#endif
+#endif /* CONFIG_DDR_ECC_ENABLE */
+}
+
+void __def_board_init(void)
+{
+ return;
+}
+void board_pre_ddrinit(void) __attribute__((weak, alias("__def_board_init")));
+void board_post_ddrinit(void) __attribute__((weak, alias("__def_board_init")));
+
+void lowlevel_init(void)
+{
+ /* ARCH specific initialization */
+ spear13xx_init();
+
+ /* Board initializations required for ddr initialization */
+ board_pre_ddrinit();
+
+ /* Initialize the SoC */
+ soc_init();
+
+ /* Initialize RAM */
+ ddr_init();
+
+ /* DDR ECC related initialization */
+ spear13xx_ddrecc_init();
+
+ /* Board initializations independent of DDR */
+ board_post_ddrinit();
+
+ /* A memory test is placed in U-Boot */
+}
+
+inline void hang(void)
+{
+ while(1)
+ ;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c b/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
new file mode 100644
index 0000000..d680e90
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+void writel_field(u32 value, u32 mask, u32 *address)
+{
+ u32 reg;
+ reg = readl(address);
+ reg &= ~mask;
+ reg |= value;
+ writel(reg, address);
+}
+
+u32 readl_field(u32 shift, u32 mask, u32 *address)
+{
+ u32 reg = readl(address);
+ return (reg & mask) >> shift;
+}
+
+void set_swlvl_mode(u32 lvlmode)
+{
+ switch (lvlmode) {
+ case WRITE_LVL:
+ writel_field(WRITE_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+ break;
+ case GATE_LVL:
+ writel_field(GATE_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+ break;
+ case READ_LVL:
+ writel_field(READ_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+ break;
+ }
+}
+
+void swlvl_start(void)
+{
+ writel(readl(&mpmc_p->reg13) | SWLVL_START, &mpmc_p->reg13);
+}
+
+void swlvl_load(void)
+{
+ writel(readl(&mpmc_p->reg12) | SWLVL_LOAD, &mpmc_p->reg12);
+}
+
+void swlvl_exit(void)
+{
+ writel(readl(&mpmc_p->reg12) | SWLVL_EXIT, &mpmc_p->reg12);
+}
+
+void wait_op_done(void)
+{
+ while (!(readl(&mpmc_p->reg13) & SWLVL_OP_DONE))
+ ;
+}
+
+u32 read_resp(u32 slice)
+{
+ u32 *resp_reg = &mpmc_p->reg57;
+
+ if (slice < 2)
+ return (readl(resp_reg) >> (slice * 8 + 16)) & 0x1;
+
+ resp_reg = &mpmc_p->reg58;
+
+ /* return (readl(resp_reg) >> ((slice - 2) * 8)) & 0xFF; */
+ return (readl(resp_reg) >> ((slice - 2) * 8)) & 0x1;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/start.S b/arch/arm/cpu/armv7/spear13xx/start.S
new file mode 100644
index 0000000..8860933
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/start.S
@@ -0,0 +1,137 @@
+/*
+ * Startup Code for SPEAr13xx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+.syntax unified
+
+.globl _start
+_start:
+ .word 0xe59f0000 @ ldr r0, [pc, #0] ; <thumb_loc>
+ .word 0xe12fff10 @ bx r0
+
+thumb_loc:
+#ifdef __thumb__
+ .word thumb + 1
+#else
+ .word thumb
+#endif
+
+#ifdef __thumb__
+.thumb
+#endif
+
+/*
+ * the actual reset code (Thumb compatible)
+ * Startup Code (reset vector)
+ *
+ * Critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ */
+
+/******************************************************************************
+ PLACE ALL INITIALIZATION CODE ONLY AFTER THIS LOCATION
+ ******************************************************************************/
+
+thumb:
+
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+ push {r1-r12, lr}
+
+ /* Relocate data if needed and Clear BSS */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:
+ cmp r0, r1 /* clear loop... */
+ bhs clbss_e /* if reached end of bss, exit */
+ str r2, [r0]
+ add r0, r0, #4
+ b clbss_l
+clbss_e:
+
+ bl cpu_init_cp15
+ bl cpu_init_crit
+
+ bl spl_boot
+ pop {r1-r12, pc}
+
+/*************************************************************************
+ *
+ * cpu_init_cp15
+ *
+ * Setup CP15 registers (cache, MMU, TLBs)
+ *
+ *************************************************************************/
+ENTRY(cpu_init_cp15)
+ /*
+ * Invalidate L1 I/D
+ */
+ mov r0, #0 @ set up for MCR
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
+ bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
+ orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
+ orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
+ mcr p15, 0, r0, c1, c0, 0
+ mov pc, lr @ back to my caller
+ENDPROC(cpu_init_cp15)
+
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************/
+ENTRY(cpu_init_crit)
+ /*
+ * Jump to board specific initialization...
+ * The Mask ROM will have already initialized
+ * basic memory. Go here to bump up clock rate and handle
+ * wake up conditions.
+ */
+ push {lr}
+ bl lowlevel_init @ go setup pll,mux,memory
+ pop {pc}
+ENDPROC(cpu_init_crit)
diff --git a/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds b/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
new file mode 100644
index 0000000..dfc2d47
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+MEMORY
+{
+ xloader : ORIGIN = 0xB3801504 , LENGTH = 0x2AFC
+ xloader_bss : ORIGIN = 0xB3804000 , LENGTH = 0x1000
+}
+
+SECTIONS
+{
+ .text :
+ {
+ arch/arm/cpu/armv7/spear13xx/start.o (.text)
+ *(.text); . = ALIGN(4);
+ } > xloader
+
+ .rodata : { *(.rodata*); . = ALIGN(4); } > xloader
+ .data : { *(.data*); . = ALIGN(4); } > xloader
+ .bss : { __bss_start = .; *(.bss*); . = ALIGN(4); __bss_end = .;} > xloader_bss
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/wakeup.S b/arch/arm/cpu/armv7/spear13xx/wakeup.S
new file mode 100644
index 0000000..82a5cac
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/wakeup.S
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.syntax unified
+
+.global cleanup_before_linux
+.global cpu2_wake
+cpu2_wake:
+ push {r0 - r1}
+ ldr r0,=CONFIG_SPEAR13XX_ARM2PHOLD
+ adr r1,cpu2_jump
+ str r1,[r0]
+ dmb
+ dsb
+ sev
+ pop {r0 - r1}
+ bx r14
+
+/* CPU2 starts running from here */
+cpu2_jump:
+ /* stack init, needed for calling C routine */
+ ldr r13,=CONFIG_SPEAR13XX_ARM2STACK
+
+ bl cleanup_before_linux
+
+ ldr r0,=CONFIG_SPEAR13XX_ARM2PHOLD
+ ldr r1,=0xdeadbeef
+ str r1,[r0]
+ dmb
+ dsb
+1:
+ wfe
+ ldr r2,=0xdeadbeef
+ ldr r1,[r0]
+ cmp r1,r2
+ beq 1b
+
+ blx r1
diff --git a/arch/arm/include/asm/arch-spear13xx/boot.h b/arch/arm/include/asm/arch-spear13xx/boot.h
new file mode 100644
index 0000000..391333a
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/boot.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_BOOT_H
+#define __ASM_ARCH_BOOT_H
+
+#include <linux/compiler.h>
+
+/* This file defines the BootROM <-> Xloader interface for spear13xx devices */
+
+/*****************************************************************************
+ * SPEAr1310 as well as SPEAr1340 device support the same table version ie 2.1
+ *****************************************************************************/
+
+/*
+ * BootROM provides a table as an interface for its routines to be used in
+ * xloader. This file needs to be compatible with all the supported spear13xx
+ * bootrom table interfaces.
+ *
+ * All the following definitions are for using already existing BootROM routines
+ */
+
+struct soc_type_s {
+ u8 soc;
+ u8 revision;
+};
+
+struct table_2_1 {
+ struct soc_type_s * (*get_soc_type)(void);
+ u8 (*get_boot_type)(void);
+
+ void * nand_info;
+ int (*nand_read)(void *nand, size_t offset,
+ size_t *length, u_char *buffer);
+ u8 * (*get_version)(void);
+
+ int (*get_otpbits)(u32 bit_off, u32 bit_cnt,
+ u32 *buffer);
+
+ u32 (*hamming_encode)(u32 parity, void *data,
+ unsigned int d, unsigned int nr);
+ void (*hamming_fix)(void *data, unsigned int d,
+ unsigned int nr, unsigned int fix);
+};
+
+union table_u {
+ struct table_2_1 table_2_1;
+};
+
+struct table_s {
+ u32 table_version;
+#define TABLE_VERSION_2_1 3
+
+ union table_u table_u;
+} __packed;
+
+/* These routines are encapsulated based on the table version */
+/*
+ * getboottype routine returns one of these independent of the spear platform
+ */
+#define BOOT_TYPE_BYPASS 1
+#define BOOT_TYPE_SMI 2
+#define BOOT_TYPE_NAND 3
+#define BOOT_TYPE_RESERVED 4
+#define BOOT_TYPE_I2C 5
+#define BOOT_TYPE_SPI 6
+#define BOOT_TYPE_USBD 7
+#define BOOT_TYPE_TFTP 8
+#define BOOT_TYPE_PCIE 9
+#define BOOT_TYPE_UART 10
+#define BOOT_TYPE_MMC 11
+#define BOOT_TYPE_PNOR8 12
+#define BOOT_TYPE_PNOR16 13
+#define BOOT_TYPE_PNOR32 14
+#define BOOT_TYPE_UNSUPPORTED 0xff
+
+static inline u8 get_boot_type(void)
+{
+ struct table_s *table = (struct table_s *)0xFFFF7F00;
+
+ if (table->table_version == TABLE_VERSION_2_1)
+ return (*table->table_u.table_2_1.get_boot_type)();
+
+ return BOOT_TYPE_UNSUPPORTED;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/generic.h b/arch/arm/include/asm/arch-spear13xx/generic.h
index 7beb1c2..eb066d4 100644
--- a/arch/arm/include/asm/arch-spear13xx/generic.h
+++ b/arch/arm/include/asm/arch-spear13xx/generic.h
@@ -30,4 +30,12 @@ extern void spear1310_usbh_stop(void);
extern void spear1340_usbh_stop(void);
#endif
+#if defined(CONFIG_SPL_BUILD)
+extern void cpu2_wake(void);
+extern void soc_init(void);
+extern void board_pre_ddrinit(void);
+extern void ddr_init(void);
+extern void board_post_ddrinit(void);
+#endif
+
#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/mpmc.h b/arch/arm/include/asm/arch-spear13xx/mpmc.h
new file mode 100644
index 0000000..24aef91
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/mpmc.h
@@ -0,0 +1,332 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef SPR13XX_MPMC_H
+#define SPR13XX_MPMC_H
+
+struct mpmc_regs {
+ u32 reg0;
+ u32 reg1;
+ u32 reg2;
+ u32 reg3;
+ u32 reg4;
+ u32 reg5;
+ u32 reg6;
+ u32 reg7;
+ u32 reg8;
+ u32 reg9;
+ u32 reg10;
+ u32 reg11;
+ u32 reg12;
+ u32 reg13;
+ u32 reg14;
+ u32 reg15;
+ u32 reg16;
+ u32 reg17;
+ u32 reg18;
+ u32 reg19;
+ u32 reg20;
+ u32 reg21;
+ u32 reg22;
+ u32 reg23;
+ u32 reg24;
+ u32 reg25;
+ u32 reg26;
+ u32 reg27;
+ u32 reg28;
+ u32 reg29;
+ u32 reg30;
+ u32 reg31;
+ u32 reg32;
+ u32 reg33;
+ u32 reg34;
+ u32 reg35;
+ u32 reg36;
+ u32 reg37;
+ u32 reg38;
+ u32 reg39;
+ u32 reg40;
+ u32 reg41;
+ u32 reg42;
+ u32 reg43;
+ u32 reg44;
+ u32 reg45;
+ u32 reg46;
+ u32 reg47;
+ u32 reg48;
+ u32 reg49;
+ u32 reg50;
+ u32 reg51;
+ u32 reg52;
+ u32 reg53;
+ u32 reg54;
+ u32 reg55;
+ u32 reg56;
+ u32 reg57;
+ u32 reg58;
+ u32 reg59;
+ u32 reg60;
+ u32 reg61;
+ u32 reg62;
+ u32 reg63;
+ u32 reg64;
+ u32 reg65;
+ u32 reg66;
+ u32 reg67;
+ u32 reg68;
+ u32 reg69;
+ u32 reg70;
+ u32 reg71;
+ u32 reg72;
+ u32 reg73;
+ u32 reg74;
+ u32 reg75;
+ u32 reg76;
+ u32 reg77;
+ u32 reg78;
+ u32 reg79;
+ u32 reg80;
+ u32 reg81;
+ u32 reg82;
+ u32 reg83;
+ u32 reg84;
+ u32 reg85;
+ u32 reg86;
+ u32 reg87;
+ u32 reg88;
+ u32 reg89;
+ u32 reg90;
+ u32 reg91;
+ u32 reg92;
+ u32 reg93;
+ u32 reg94;
+ u32 reg95;
+ u32 reg96;
+ u32 reg97;
+ u32 reg98;
+ u32 reg99;
+ u32 reg100;
+ u32 reg101;
+ u32 reg102;
+ u32 reg103;
+ u32 reg104;
+ u32 reg105;
+ u32 reg106;
+ u32 reg107;
+ u32 reg108;
+ u32 reg109;
+ u32 reg110;
+ u32 reg111;
+ u32 reg112;
+ u32 reg113;
+ u32 reg114;
+ u32 reg115;
+ u32 reg116;
+ u32 reg117;
+ u32 reg118;
+ u32 reg119;
+ u32 reg120;
+ u32 reg121;
+ u32 reg122;
+ u32 reg123;
+ u32 reg124;
+ u32 reg125;
+ u32 reg126;
+ u32 reg127;
+ u32 reg128;
+ u32 reg129;
+ u32 reg130;
+ u32 reg131;
+ u32 reg132;
+ u32 reg133;
+ u32 reg134;
+ u32 reg135;
+ u32 reg136;
+ u32 reg137;
+ u32 reg138;
+ u32 reg139;
+ u32 reg140;
+ u32 reg141;
+ u32 reg142;
+ u32 reg143;
+ u32 reg144;
+ u32 reg145;
+ u32 reg146;
+ u32 reg147;
+ u32 reg148;
+ u32 reg149;
+ u32 reg150;
+ u32 reg151;
+ u32 reg152;
+ u32 reg153;
+ u32 reg154;
+ u32 reg155;
+ u32 reg156;
+ u32 reg157;
+ u32 reg158;
+ u32 reg159;
+ u32 reg160;
+ u32 reg161;
+ u32 reg162;
+ u32 reg163;
+ u32 reg164;
+ u32 reg165;
+ u32 reg166;
+ u32 reg167;
+ u32 reg168;
+ u32 reg169;
+ u32 reg170;
+ u32 reg171;
+ u32 reg172;
+ u32 reg173;
+ u32 reg174;
+ u32 reg175;
+ u32 reg176;
+ u32 reg177;
+ u32 reg178;
+ u32 reg179;
+ u32 reg180;
+ u32 reg181;
+ u32 reg182;
+ u32 reg183;
+ u32 reg184;
+ u32 reg185;
+ u32 reg186;
+ u32 reg187;
+ u32 reg188;
+ u32 reg189;
+ u32 reg190;
+ u32 reg191;
+ u32 reg192;
+ u32 reg193;
+ u32 reg194;
+ u32 reg195;
+ u32 reg196;
+ u32 reg197;
+ u32 reg198;
+ u32 reg199;
+ u32 reg200;
+ u32 reg201;
+ u32 reg202;
+ u32 reg203;
+ u32 reg204;
+ u32 reg205;
+ u32 reg206;
+ u32 reg207;
+ u32 reg208;
+ u32 reg209;
+};
+
+#define PHY_CTRL_DELAY 200
+
+#ifdef CONFIG_DDR_ECC_ENABLE
+#define DATA_SLICE_MAX 5
+#else
+#define DATA_SLICE_MAX 4
+#endif
+
+#define WRLVL_DELAY_MAX 8
+#define RDLVL_DELAY_VALS 8
+#define RDLVL_DELAY_INIT 4
+
+#define MPMC_REG18_ECC_MASK (3 << 8)
+#define MPMC_REG18_NO_ECC (0 << 8)
+#define MPMC_REG18_ECC_REPORT_ON (1 << 8)
+#define MPMC_REG18_ECC_CORR_ON (3 << 8)
+
+/* DDR2 settings*/
+#define WRLVL_BASE_OFFSET_REG_VALUE 0
+
+#define WRLVL_DELAY_VALUE_0 2
+#define WRLVL_DELAY_VALUE_1 2
+#define WRLVL_DELAY_VALUE_2 2
+#define WRLVL_DELAY_VALUE_3 2
+#define WRLVL_DELAY_VALUE_4 2
+
+#define RDLVL_GATE_DELAY_VALUE_0 31
+#define RDLVL_GATE_DELAY_VALUE_1 26
+#define RDLVL_GATE_DELAY_VALUE_2 26
+#define RDLVL_GATE_DELAY_VALUE_3 31
+#define RDLVL_GATE_DELAY_VALUE_4 31
+
+#define RDLVL_DELAY_VALUE_0 8
+#define RDLVL_DELAY_VALUE_1 8
+#define RDLVL_DELAY_VALUE_2 8
+#define RDLVL_DELAY_VALUE_3 8
+#define RDLVL_DELAY_VALUE_4 8
+
+/* mpmc register definitions */
+#define SWLVL_MODE_MSK (3 << 8)
+#define NO_LVL (0 << 8)
+#define WRITE_LVL (1 << 8)
+#define READ_LVL (2 << 8)
+#define GATE_LVL (3 << 8)
+#define SWLVL_START (1 << 8)
+#define SWLVL_LOAD (1 << 24)
+#define SWLVL_EXIT (1 << 16)
+#define SWLVL_OP_DONE (1 << 0)
+#define WRLVL_REG_EN (1 << 8)
+#define RDLVL_GATE_REG_EN (1 << 0)
+#define RDLVL_REG_EN (1 << 24)
+
+#define TDFI_RDLVL_RR (0x10 << 16)
+#define TDFI_RDLVL_RR_MSK (0x3FF << 16)
+#define DQSGATE_ASSERT_MSK (0x1F << 0)
+#define DQSGATE_DEASSERT_MSK (0x1F << 5)
+#define DQSOE_ASSERT_MSK (0x1F << 10)
+#define DQSOE_DEASSERT_MSK (0x1F << 15)
+#define REG1_ASSERT_MSK (0x1F << 20)
+#define REG1_DEASSERT_MSK (0x1F << 25)
+#define REG5_ASSERT_MSK (0x1F << 0)
+#define REG5_DEASSERT_MSK (0x1F << 5)
+#define REG6_DQS_ASSERT_MSK (0x1F << 10)
+#define REG6_DQS_DEASSERT_MSK (0x1F << 15)
+#define REG7_ASSERT_MSK (0x1F << 18)
+#define REG7_DEASSERT_MSK (0x1F << 23)
+
+/* externs */
+extern void writel_field(u32, u32, u32 *);
+extern u32 readl_field(u32, u32, u32 *);
+extern void swlvl_load(void);
+extern void wait_op_done(void);
+extern u32 read_resp(u32);
+extern void set_swlvl_mode(u32);
+extern void swlvl_start(void);
+extern void swlvl_exit(void);
+
+extern void spear13xx_mpmc_init(u32 *, u32);
+extern void spear13xx_ddr_level(void);
+
+extern u32 mpmc_conf_vals[];
+
+#if defined(CONFIG_DDR3)
+extern void ddr3_lvl_write(void);
+extern void ddr3_lvl_gatetrn(void);
+extern void ddr3_lvl_read(void);
+#elif defined(CONFIG_DDR2)
+extern void ddr2_lvl_write(void);
+extern void ddr2_lvl_gatetrn(void);
+extern void ddr2_lvl_read(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
index 090de1c..1e9c04c 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
@@ -235,28 +235,11 @@ struct spear1340_misc_regs {
u32 misc_cfg; /* 0x1008 */
};
-/* PHERIP1_CLOCK ENABLE */
-#define SPEAR1340_C3_CLKEN 0x20000000
-#define SPEAR1340_GPT1_CLKEN 0x00200000
-#define SPEAR1340_I2C_CLKEN 0x00040000
-#define SPEAR1340_SSP_CLKEN 0x00020000
-#define SPEAR1340_UART_CLKEN 0x00008000
-#define SPEAR1340_UDC_UPD_CLKEN 0x00000800
-#define SPEAR1340_UHC1_CLKEN 0x00000200
-#define SPEAR1340_GETH_CLKEN 0x00000100
-#define SPEAR1340_SD_CLKEN 0x00000040
-#define SPEAR1340_SMI_CLKEN 0x00000020
-#define SPEAR1340_FSMC_CLKEN 0x00000010
-
-/* perip1_sw_rst */
-#define SPEAR1340_C3_SWRST 0x20000000
-#define SPEAR1340_UDC_UPD_SWRST 0x00000800
-#define SPEAR1340_UHC1_SWRST 0x00000200
-
+/* sys_clk_ctrl definitions */
#define SPEAR1340_SYS_MODE_MASK 0x00000007
-#define SPEAR1340_SYS_MODE_DOZE 0x00000001
-#define SPEAR1340_SYS_MODE_SLOW 0x00000002
-#define SPEAR1340_SYS_MODE_NORMAL 0x00000004
+#define SPEAR1340_SYS_MODE_REQ_DOZE 0x00000001
+#define SPEAR1340_SYS_MODE_REQ_SLOW 0x00000002
+#define SPEAR1340_SYS_MODE_REQ_NORMAL 0x00000004
#define SPEAR1340_PLL_TIMEOUT_ENB 0x00000008
#define SPEAR1340_XTAL_TIMEOUT_ENB 0x00000010
#define SPEAR1340_SYS_STATE_MASK 0x000F0000
@@ -268,14 +251,17 @@ struct spear1340_misc_regs {
/* pll_freq definitions in MHz */
#define SPEAR1340_FREQ_1000 0x7D000006
-#define SPEAR1340_FREQ_996 0x53000004
+#define SPEAR1340_FREQ_533 0x6F000105
+#define SPEAR1340_FREQ_400 0x64000106
#define SPEAR1340_FREQ_332 0x53000203
+#define SPEAR1340_FREQ_125 0x7D000306
/* pll_ctr definitions */
#define SPEAR1340_PLLLOCK 0x00000001
#define SPEAR1340_PLLENABLE 0x00000004
/* perip_clk_cfg definitions */
+#define SPEAR1340_MPMCCLKPLL4 0x00000400
#define SPEAR1340_GPTCLKSRC 0x00000100
#define SPEAR1340_UARTCLKMSK 0x00000030
#define SPEAR1340_UART48M 0x00000000
@@ -294,10 +280,13 @@ struct spear1340_misc_regs {
/* usbphy_gen_cfg definitions */
#define SPEAR1340_USB_PLL_LOCK 0x01000000
-#define SPEAR1340_USBPHY_RST 0x00008000
-#define SPEAR1340_USBPHY_PRSNT 0x00002000
+#define SPEAR1340_UTMI_XFER_RST2 0x00010000
+#define SPEAR1340_UTMI_XFER_RST1 0x00008000
+#define SPEAR1340_UTMI_XFER_RST0 0x00004000
+#define SPEAR1340_USBPHY_RST 0x00002000
#define SPEAR1340_USBPHY_POR 0x00001000
-#define SPEAR1340_COMMON_PWDN 0x00000000
+#define SPEAR1340_AUTOPPD_ON_OVRCURR 0x00000020
+#define SPEAR1340_COMMON_PWDN 0x00000001
/* perip_cfg definitions */
#define SPEAR1340_HS_SSP_EN 0x00200000
@@ -328,4 +317,41 @@ struct spear1340_misc_regs {
#define SPEAR1340_SYNT_Y_5 0x00000005
#define SPEAR1340_SYNT_Y_21 0x00000015
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1340_C3_CLKEN 0x20000000
+#define SPEAR1340_GPT1_CLKEN 0x00200000
+#define SPEAR1340_I2C_CLKEN 0x00040000
+#define SPEAR1340_SSP_CLKEN 0x00020000
+#define SPEAR1340_UART_CLKEN 0x00008000
+#define SPEAR1340_UDC_UPD_CLKEN 0x00000800
+#define SPEAR1340_UHC1_CLKEN 0x00000200
+#define SPEAR1340_GETH_CLKEN 0x00000100
+#define SPEAR1340_SD_CLKEN 0x00000040
+#define SPEAR1340_SMI_CLKEN 0x00000020
+#define SPEAR1340_FSMC_CLKEN 0x00000010
+#define SPEAR1340_DDRCORE_CLKEN 0x00000002
+#define SPEAR1340_DDRCTRL_CLKEN 0x00000001
+
+/* perip1_sw_rst */
+#define SPEAR1340_C3_SWRST 0x20000000
+#define SPEAR1340_UDC_UPD_SWRST 0x00000800
+#define SPEAR1340_UHC1_SWRST 0x00000200
+#define SPEAR1340_DDRCORE_RST 0x00000002
+#define SPEAR1340_DDRCTRL_RST 0x00000001
+#define SPEAR1340_PERIPH1_RST_ALL 0x00000000
+#define SPEAR1340_PERIPH2_RST_ALL 0x00000000
+#define SPEAR1340_PERIPH3_RST_ALL 0x00000000
+
+/* ddr_pad_cfg definitions */
+#define SPEAR1340_PAD_VREF 0x00000200
+#define SPEAR1340_DATA_PROGB 0x00000100
+#define SPEAR1340_DATA_PROGA 0x00000080
+#define SPEAR1340_CLK_PROGB 0x00000040
+#define SPEAR1340_CLK_PROGA 0x00000020
+#define SPEAR1340_CTRL_PROGB 0x00000010
+#define SPEAR1340_CTRL_PROGA 0x00000008
+#define SPEAR1340_DDR3_PAD_SW_SEL 0x00000004
+#define SPEAR1340_DDR3_PAD_SEL 0x00000002
+#define SPEAR1340_DDR3_SW_SEL 0x00000001
+
#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear13xx.h b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
index a4fca51..916175b 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear13xx.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
@@ -26,6 +26,10 @@
#define CONFIG_SPEAR_CORTEXBASE 0xEC800000
#define CONFIG_ARMV7_LTIMER_BASE (CONFIG_SPEAR_CORTEXBASE + 0x600)
+#define CONFIG_SYS_L2CACHE_BASE 0xED000000
+
+#define CONFIG_SYS_MPMC_BASE 0xEC000000
+#define CONFIG_SPEAR_MPMCREGS 208
#define CONFIG_SYS_C3_BASE 0xE1800000
#define CONFIG_SYS_USBD_BASE 0xE3800000
diff --git a/board/st/spear13xx/Makefile b/board/st/spear13xx/Makefile
index a662ac4..ca87ee9 100644
--- a/board/st/spear13xx/Makefile
+++ b/board/st/spear13xx/Makefile
@@ -28,10 +28,15 @@ LIB = $(obj)lib$(BOARD).o
SOBJS-y :=
COBJS-y :=
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spl-spear1310evb.o
+COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spl-spear1340evb.o
+else
COBJS-y += spear13xx_common.o
COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spear1310evb.o
COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spear1340evb.o
COBJS-$(CONFIG_MACH_SPEAR1340LCAD) += spear1340lcad.o
+endif
COBJS := $(sort $(COBJS-y))
SOBJS := $(sort $(SOBJS-y))
diff --git a/board/st/spear13xx/config.mk b/board/st/spear13xx/config.mk
index 9d5de65..a8f67d4 100644
--- a/board/st/spear13xx/config.mk
+++ b/board/st/spear13xx/config.mk
@@ -23,4 +23,8 @@
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.img
+
+ifdef CONFIG_MACH_SPEAR1340EVB
+ALL-y += $(obj)spl/u-boot-spl.img
+endif
endif
diff --git a/board/st/spear13xx/ddr/Makefile b/board/st/spear13xx/ddr/Makefile
new file mode 100644
index 0000000..0f5ee7b
--- /dev/null
+++ b/board/st/spear13xx/ddr/Makefile
@@ -0,0 +1,64 @@
+#
+# (C) Copyright 2012
+# Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD)ddr.o
+
+SOBJS-y :=
+COBJS-y :=
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_DDR_H5TQ2G63BFRPBC) += h5tq2g63bfr_pbc_400_cl6.o
+COBJS-$(CONFIG_DDR_H5TQ2G63BFRPBC) += h5tq2g63bfr_pbc_533_cl8.o
+COBJS-$(CONFIG_DDR_K4B2G1646CK0) += k4b2g1646c_k0_400_cl6.o
+COBJS-$(CONFIG_DDR_K4B2G1646CK0) += k4b2g1646c_k0_533_cl8.o
+COBJS-$(CONFIG_DDR_MT41J128M16) += mt41j128m16_15e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J256M8) += mt41j256m8187e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J256M8) += mt41j256m8187e_533_cl7_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J64M16) += mt41j64m16_15e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J64M16) += mt41j64m16_15e_533_cl7_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT47H128M16) += mt47h128m16rt187e_400_cl6_ddr2.o
+COBJS-$(CONFIG_DDR_MT47H128M16) += mt47h128m16rt187e_533_cl7_ddr2.o
+endif
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
new file mode 100644
index 0000000..fa9f322
--- /dev/null
+++ b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030001, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04020402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04070600, /* MPMC_REG_46 0x04070602 */
+ 0x02000505, /* MPMC_REG_47 0x02000505 */
+ 0x0000000c, /* MPMC_REG_48 0x0000000c */
+ 0x0c040406, /* MPMC_REG_49 0x0c040406 */
+ 0x0600000c, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+ 0x19141200, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031703, /* MPMC_REG_59 0x03031703 */
+ 0x060e0c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+ 0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+ 0x04200420, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00000000, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000003, /* MPMC_REG_97 0x6da60003 */
+ 0x0044000a, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000004, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00030d40, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00304000, /* MPMC_REG_124 0x00304000 */
+ 0x00304000, /* MPMC_REG_125 0x00304000 */
+ 0x00304000, /* MPMC_REG_126 0x00304000 */
+ 0x00304000, /* MPMC_REG_127 0x00304000 */
+ 0x00304000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+ 0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+ 0x00013880, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x00006db0, /* MPMC_REG_201 0x00006db0 */
+ 0x00000040, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
new file mode 100644
index 0000000..7e862df
--- /dev/null
+++ b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030001, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04030402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04090800, /* MPMC_REG_46 0x04070602 */
+ 0x02000606, /* MPMC_REG_47 0x02000505 */
+ 0x00000010, /* MPMC_REG_48 0x0000000c */
+ 0x10040408, /* MPMC_REG_49 0x0c040406 */
+ 0x0800000d, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f08, /* MPMC_REG_51 0x3f003f06 */
+ 0x191a1800, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031a03, /* MPMC_REG_59 0x03031703 */
+ 0x08130c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x102d0200, /* MPMC_REG_67 0x0c280200 */
+ 0x0200102d, /* MPMC_REG_68 0x02000c28 */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x102d0200, /* MPMC_REG_70 0x0c280200 */
+ 0x08400840, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00080008, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000004, /* MPMC_REG_97 0x6da60003 */
+ 0x005b000d, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000006, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00040ee6, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00404000, /* MPMC_REG_124 0x00304000 */
+ 0x00404000, /* MPMC_REG_125 0x00304000 */
+ 0x00404000, /* MPMC_REG_126 0x00304000 */
+ 0x00404000, /* MPMC_REG_127 0x00304000 */
+ 0x00404000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x0000102d, /* MPMC_REG_182 0x00000c28 */
+ 0x0000102d, /* MPMC_REG_183 0x00000c28 */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x0000102d, /* MPMC_REG_185 0x00000c28 */
+ 0x00019f8f, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x000091dd, /* MPMC_REG_201 0x00006db0 */
+ 0x00000056, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x000050e1, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c b/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
new file mode 100644
index 0000000..c603906
--- /dev/null
+++ b/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030001, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04020402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04070600, /* MPMC_REG_46 0x04070602 */
+ 0x02000505, /* MPMC_REG_47 0x02000505 */
+ 0x0000000c, /* MPMC_REG_48 0x0000000c */
+ 0x0c040406, /* MPMC_REG_49 0x0c040406 */
+ 0x0600000c, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+ 0x19141000, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031703, /* MPMC_REG_59 0x03031703 */
+ 0x060e0c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x0c280200, /* MPMC_REG_67 0x0c280200 */
+ 0x02000c28, /* MPMC_REG_68 0x02000c28 */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x0c280200, /* MPMC_REG_70 0x0c280200 */
+ 0x04200420, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00000000, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000003, /* MPMC_REG_97 0x6da60003 */
+ 0x0044000a, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000004, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00030d40, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00304000, /* MPMC_REG_124 0x00304000 */
+ 0x00304000, /* MPMC_REG_125 0x00304000 */
+ 0x00304000, /* MPMC_REG_126 0x00304000 */
+ 0x00304000, /* MPMC_REG_127 0x00304000 */
+ 0x00304000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x00000c28, /* MPMC_REG_182 0x00000c28 */
+ 0x00000c28, /* MPMC_REG_183 0x00000c28 */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x00000c28, /* MPMC_REG_185 0x00000c28 */
+ 0x00013880, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x00006db0, /* MPMC_REG_201 0x00006db0 */
+ 0x00000040, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x00003cc8, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c b/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
new file mode 100644
index 0000000..159d3d7
--- /dev/null
+++ b/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030001, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04030402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04090800, /* MPMC_REG_46 0x04070602 */
+ 0x02000606, /* MPMC_REG_47 0x02000505 */
+ 0x00000010, /* MPMC_REG_48 0x0000000c */
+ 0x10040408, /* MPMC_REG_49 0x0c040406 */
+ 0x0800000d, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f08, /* MPMC_REG_51 0x3f003f06 */
+ 0x191a1600, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031a03, /* MPMC_REG_59 0x03031703 */
+ 0x08130c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x102d0200, /* MPMC_REG_67 0x0c280200 */
+ 0x0200102d, /* MPMC_REG_68 0x02000c28 */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x102d0200, /* MPMC_REG_70 0x0c280200 */
+ 0x08400840, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00080008, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000004, /* MPMC_REG_97 0x6da60003 */
+ 0x005b000d, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000006, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00040ee6, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00404000, /* MPMC_REG_124 0x00304000 */
+ 0x00404000, /* MPMC_REG_125 0x00304000 */
+ 0x00404000, /* MPMC_REG_126 0x00304000 */
+ 0x00404000, /* MPMC_REG_127 0x00304000 */
+ 0x00404000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x0000102d, /* MPMC_REG_182 0x00000c28 */
+ 0x0000102d, /* MPMC_REG_183 0x00000c28 */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x0000102d, /* MPMC_REG_185 0x00000c28 */
+ 0x00019f8f, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x000091dd, /* MPMC_REG_201 0x00006db0 */
+ 0x00000056, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x000050e1, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..1260ba1
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030001, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04030402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04070600, /* MPMC_REG_46 0x04070602 */
+ 0x02000505, /* MPMC_REG_47 0x02000505 */
+ 0x0000000c, /* MPMC_REG_48 0x0000000c */
+ 0x0c040406, /* MPMC_REG_49 0x0c040406 */
+ 0x0600000c, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+ 0x19141200, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031703, /* MPMC_REG_59 0x03031703 */
+ 0x060f0c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+ 0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+ 0x04200420, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00000000, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000003, /* MPMC_REG_97 0x6da60003 */
+ 0x0044000a, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000004, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00030d40, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00304000, /* MPMC_REG_124 0x00304000 */
+ 0x00304000, /* MPMC_REG_125 0x00304000 */
+ 0x00304000, /* MPMC_REG_126 0x00304000 */
+ 0x00304000, /* MPMC_REG_127 0x00304000 */
+ 0x00304000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+ 0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+ 0x00013880, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x00006db0, /* MPMC_REG_201 0x00006db0 */
+ 0x00000040, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..8ee680b
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 */
+ 0x00000100, /* MPMC_REG_01 */
+ 0x01000000, /* MPMC_REG_02 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+ 0x00000101, /* MPMC_REG_03 */
+#else
+ 0x00000100, /* MPMC_REG_03 */
+#endif
+ 0x00000000, /* MPMC_REG_04 */
+ 0x00010101, /* MPMC_REG_05 */
+ 0x00000001, /* MPMC_REG_06 */
+ 0x00000000, /* MPMC_REG_07 */
+ 0x00000000, /* MPMC_REG_08 */
+ 0x00000000, /* MPMC_REG_09 */
+ 0x00000000, /* MPMC_REG_10 */
+ 0x00000101, /* MPMC_REG_11 */
+ 0x00000101, /* MPMC_REG_12 */
+ 0x01010000, /* MPMC_REG_13 */
+ 0x00000000, /* MPMC_REG_14 */
+ 0x01000000, /* MPMC_REG_15 */
+ 0x00000000, /* MPMC_REG_16 */
+ 0x00000000, /* MPMC_REG_17 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+ 0x00000001, /* MPMC_REG_18 */
+#else
+ 0x00000201, /* MPMC_REG_18 */
+#endif
+ 0x02010102, /* MPMC_REG_19 */
+ 0x00020000, /* MPMC_REG_20 */
+ 0x07070000, /* MPMC_REG_21 */
+ 0x00070700, /* MPMC_REG_22 */
+ 0x07000707, /* MPMC_REG_23 */
+ 0x00000007, /* MPMC_REG_24 */
+ 0x03070700, /* MPMC_REG_25 */
+ 0x00000400, /* MPMC_REG_26 */
+ 0x02000100, /* MPMC_REG_27 */
+ 0x04030402, /* MPMC_REG_28 */
+ 0x01000104, /* MPMC_REG_29 */
+ 0x04000000, /* MPMC_REG_30 */
+ 0x0606060a, /* MPMC_REG_31 */
+ 0x06060606, /* MPMC_REG_32 */
+ 0x05050506, /* MPMC_REG_33 */
+ 0x05050505, /* MPMC_REG_34 */
+ 0x04040405, /* MPMC_REG_35 */
+ 0x04040404, /* MPMC_REG_36 */
+ 0x03030304, /* MPMC_REG_37 */
+ 0x03030303, /* MPMC_REG_38 */
+ 0x02020203, /* MPMC_REG_39 */
+ 0x02020202, /* MPMC_REG_40 */
+ 0x01010102, /* MPMC_REG_41 */
+ 0x01010101, /* MPMC_REG_42 */
+ 0x06000c01, /* MPMC_REG_43 */
+ 0x00000000, /* MPMC_REG_44 */
+ 0x00000204, /* MPMC_REG_45 */
+ 0x04070602, /* MPMC_REG_46 */
+ 0x02000505, /* MPMC_REG_47 */
+ 0x0000000c, /* MPMC_REG_48 */
+ 0x0c040406, /* MPMC_REG_49 */
+ 0x0602000c, /* MPMC_REG_50 */
+ 0x3f003f06, /* MPMC_REG_51 */
+ 0x19150f00, /* MPMC_REG_52 */
+ 0x00000028, /* MPMC_REG_53 */
+ 0x00000000, /* MPMC_REG_54 */
+ 0x00000000, /* MPMC_REG_55 */
+ 0x00000000, /* MPMC_REG_56 */
+ 0x00004000, /* MPMC_REG_57 */
+ 0x03000000, /* MPMC_REG_58 */
+ 0x03031703, /* MPMC_REG_59 */
+ 0x060f0c04, /* MPMC_REG_60 */
+ 0x00006456, /* MPMC_REG_61 */
+ 0x00640064, /* MPMC_REG_62 */
+ 0x00640064, /* MPMC_REG_63 */
+ 0x000f0064, /* MPMC_REG_64 */
+ 0x0000000a, /* MPMC_REG_65 */
+ 0x00400100, /* MPMC_REG_66 */
+ 0x0c2d0200, /* MPMC_REG_67 */
+ 0x02000c2d, /* MPMC_REG_68 */
+ 0x02000200, /* MPMC_REG_69 */
+ 0x0c2d0200, /* MPMC_REG_70 */
+ 0x04200420, /* MPMC_REG_71 */
+ 0x00440044, /* MPMC_REG_72 */
+ 0x00000000, /* MPMC_REG_73 */
+ 0x00000000, /* MPMC_REG_74 */
+ 0xff005555, /* MPMC_REG_75 */
+ 0xaaaa00ff, /* MPMC_REG_76 */
+ 0xff005555, /* MPMC_REG_77 */
+ 0x00000007, /* MPMC_REG_78 */
+ 0x00000000, /* MPMC_REG_79 */
+ 0x00000000, /* MPMC_REG_80 */
+ 0x00070000, /* MPMC_REG_81 */
+ 0x00070007, /* MPMC_REG_82 */
+ 0x00070007, /* MPMC_REG_83 */
+ 0x00000000, /* MPMC_REG_84 */
+ 0x00000000, /* MPMC_REG_85 */
+ 0x00030000, /* MPMC_REG_86 */
+ 0x00030003, /* MPMC_REG_87 */
+ 0x00030003, /* MPMC_REG_88 */
+ 0xffff0010, /* MPMC_REG_89 */
+ 0x00000000, /* MPMC_REG_90 */
+ 0x00000000, /* MPMC_REG_91 */
+ 0x00000000, /* MPMC_REG_92 */
+ 0x00000000, /* MPMC_REG_93 */
+ 0x00000000, /* MPMC_REG_94 */
+ 0x00000000, /* MPMC_REG_95 */
+ 0x02000000, /* MPMC_REG_96 */
+ 0x6da60003, /* MPMC_REG_97 */
+ 0x0044000a, /* MPMC_REG_98 */
+ 0x00000200, /* MPMC_REG_99 */
+ 0x00000000, /* MPMC_REG_100 */
+ 0x00000000, /* MPMC_REG_101 */
+ 0x00000000, /* MPMC_REG_102 */
+ 0x00000000, /* MPMC_REG_103 */
+ 0x00000000, /* MPMC_REG_104 */
+ 0x00000000, /* MPMC_REG_105 */
+ 0x00000000, /* MPMC_REG_106 */
+ 0x00000001, /* MPMC_REG_107 */
+ 0x00000001, /* MPMC_REG_108 */
+ 0x00000001, /* MPMC_REG_109 */
+ 0x00000001, /* MPMC_REG_110 */
+ 0x00000001, /* MPMC_REG_111 */
+ 0x0000ffff, /* MPMC_REG_112 */
+ 0x00000000, /* MPMC_REG_113 */
+ 0x00030d40, /* MPMC_REG_114 */
+ 0x00000050, /* MPMC_REG_115 */
+ 0x00000050, /* MPMC_REG_116 */
+ 0x00000050, /* MPMC_REG_117 */
+ 0x00000050, /* MPMC_REG_118 */
+ 0x00000050, /* MPMC_REG_119 */
+ 0x00000050, /* MPMC_REG_120 */
+ 0x00000000, /* MPMC_REG_121 */
+ 0x00000000, /* MPMC_REG_122 */
+ 0x000f1133, /* MPMC_REG_123 */
+ 0x00304000, /* MPMC_REG_124 */
+ 0x00304000, /* MPMC_REG_125 */
+ 0x00304000, /* MPMC_REG_126 */
+ 0x00304000, /* MPMC_REG_127 */
+ 0x00304000, /* MPMC_REG_128 */
+ 0x00000002, /* MPMC_REG_129 */
+ 0x1208a108, /* MPMC_REG_130 */
+ 0x1208a108, /* MPMC_REG_131 */
+ 0x1208a108, /* MPMC_REG_132 */
+ 0x1208a108, /* MPMC_REG_133 */
+ 0x1208a108, /* MPMC_REG_134 */
+ 0x01000000, /* MPMC_REG_135 */
+ 0x01000000, /* MPMC_REG_136 */
+ 0x01000000, /* MPMC_REG_137 */
+ 0x01000000, /* MPMC_REG_138 */
+ 0x01000000, /* MPMC_REG_139 */
+ 0x01000000, /* MPMC_REG_140 */
+ 0x01000000, /* MPMC_REG_141 */
+ 0x01000000, /* MPMC_REG_142 */
+ 0x01000000, /* MPMC_REG_143 */
+ 0x01000000, /* MPMC_REG_144 */
+ 0x06db6db6, /* MPMC_REG_145 */
+ 0x06db6db6, /* MPMC_REG_146 */
+ 0x06db6db6, /* MPMC_REG_147 */
+ 0x06db6db6, /* MPMC_REG_148 */
+ 0x06db6db6, /* MPMC_REG_149 */
+ 0x00000000, /* MPMC_REG_150 */
+ 0x00000000, /* MPMC_REG_151 */
+ 0x00000000, /* MPMC_REG_152 */
+ 0x00000000, /* MPMC_REG_153 */
+ 0x00000000, /* MPMC_REG_154 */
+ 0x2498a249, /* MPMC_REG_155 */
+ 0x2498a249, /* MPMC_REG_156 */
+ 0x2498a249, /* MPMC_REG_157 */
+ 0x2498a249, /* MPMC_REG_158 */
+ 0x2498a249, /* MPMC_REG_159 */
+ 0x04803219, /* MPMC_REG_160 */
+ 0x04803219, /* MPMC_REG_161 */
+ 0x04803219, /* MPMC_REG_162 */
+ 0x04803219, /* MPMC_REG_163 */
+ 0x04803219, /* MPMC_REG_164 */
+ 0x00000000, /* MPMC_REG_165 */
+ 0x00000000, /* MPMC_REG_166 */
+ 0x00000000, /* MPMC_REG_167 */
+ 0x00000000, /* MPMC_REG_168 */
+ 0x00000000, /* MPMC_REG_169 */
+ 0x00000000, /* MPMC_REG_170 */
+ 0x00000000, /* MPMC_REG_171 */
+ 0x00000000, /* MPMC_REG_172 */
+ 0x00000000, /* MPMC_REG_173 */
+ 0x00000000, /* MPMC_REG_174 */
+ 0x00000000, /* MPMC_REG_175 */
+ 0x00000000, /* MPMC_REG_176 */
+ 0x00000000, /* MPMC_REG_177 */
+ 0x00000000, /* MPMC_REG_178 */
+ 0x00000000, /* MPMC_REG_179 */
+ 0x00000000, /* MPMC_REG_180 */
+ 0x00000000, /* MPMC_REG_181 */
+ 0x00000c2d, /* MPMC_REG_182 */
+ 0x00000c2d, /* MPMC_REG_183 */
+ 0x00000000, /* MPMC_REG_184 */
+ 0x00000c2d, /* MPMC_REG_185 */
+ 0x00013880, /* MPMC_REG_186 */
+ 0x00000000, /* MPMC_REG_187 */
+ 0x00000000, /* MPMC_REG_188 */
+ 0x00000000, /* MPMC_REG_189 */
+ 0x00000000, /* MPMC_REG_190 */
+ 0x00000000, /* MPMC_REG_191 */
+ 0x00000000, /* MPMC_REG_192 */
+ 0x00000000, /* MPMC_REG_193 */
+ 0x00000000, /* MPMC_REG_194 */
+ 0x00000000, /* MPMC_REG_195 */
+ 0x00000000, /* MPMC_REG_196 */
+ 0x00000000, /* MPMC_REG_197 */
+ 0x07000000, /* MPMC_REG_198 */
+ 0x00000007, /* MPMC_REG_199 */
+ 0x00000000, /* MPMC_REG_200 */
+ 0x00006db0, /* MPMC_REG_201 */
+ 0x00000040, /* MPMC_REG_202 */
+ 0x00000000, /* MPMC_REG_203 */
+ 0x00000000, /* MPMC_REG_204 */
+ 0x02000000, /* MPMC_REG_205 */
+ 0x00000000, /* MPMC_REG_206 */
+ 0x00003ce1, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
new file mode 100644
index 0000000..0d11b36
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 */
+ 0x00000100, /* MPMC_REG_01 */
+ 0x01000000, /* MPMC_REG_02 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+ 0x00000101, /* MPMC_REG_03 */
+#else
+ 0x00000100, /* MPMC_REG_03 */
+#endif
+ 0x00000000, /* MPMC_REG_04 */
+ 0x00010101, /* MPMC_REG_05 */
+ 0x00000001, /* MPMC_REG_06 */
+ 0x00000000, /* MPMC_REG_07 */
+ 0x00000000, /* MPMC_REG_08 */
+ 0x00000000, /* MPMC_REG_09 */
+ 0x00000000, /* MPMC_REG_10 */
+ 0x00000101, /* MPMC_REG_11 */
+ 0x00000101, /* MPMC_REG_12 */
+ 0x01010000, /* MPMC_REG_13 */
+ 0x00000000, /* MPMC_REG_14 */
+ 0x01000000, /* MPMC_REG_15 */
+ 0x00000000, /* MPMC_REG_16 */
+ 0x00000000, /* MPMC_REG_17 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+ 0x00000001, /* MPMC_REG_18 */
+#else
+ 0x00000201, /* MPMC_REG_18 */
+#endif
+ 0x02010102, /* MPMC_REG_19 */
+ 0x00020000, /* MPMC_REG_20 */
+ 0x07070000, /* MPMC_REG_21 */
+ 0x00070700, /* MPMC_REG_22 */
+ 0x07000707, /* MPMC_REG_23 */
+ 0x00000007, /* MPMC_REG_24 */
+ 0x03070700, /* MPMC_REG_25 */
+ 0x00000400, /* MPMC_REG_26 */
+ 0x02000100, /* MPMC_REG_27 */
+ 0x04030402, /* MPMC_REG_28 */
+ 0x01000104, /* MPMC_REG_29 */
+ 0x04000000, /* MPMC_REG_30 */
+ 0x0606060a, /* MPMC_REG_31 */
+ 0x06060606, /* MPMC_REG_32 */
+ 0x05050506, /* MPMC_REG_33 */
+ 0x05050505, /* MPMC_REG_34 */
+ 0x04040405, /* MPMC_REG_35 */
+ 0x04040404, /* MPMC_REG_36 */
+ 0x03030304, /* MPMC_REG_37 */
+ 0x03030303, /* MPMC_REG_38 */
+ 0x02020203, /* MPMC_REG_39 */
+ 0x02020202, /* MPMC_REG_40 */
+ 0x01010102, /* MPMC_REG_41 */
+ 0x01010101, /* MPMC_REG_42 */
+ 0x06000c01, /* MPMC_REG_43 */
+ 0x00000000, /* MPMC_REG_44 */
+ 0x00000204, /* MPMC_REG_45 */
+ 0x04080702, /* MPMC_REG_46 */
+ 0x02000606, /* MPMC_REG_47 */
+ 0x0000000e, /* MPMC_REG_48 */
+ 0x0f040407, /* MPMC_REG_49 */
+ 0x0802000d, /* MPMC_REG_50 */
+ 0x3f003f08, /* MPMC_REG_51 */
+ 0x191b1400, /* MPMC_REG_52 */
+ 0x00000028, /* MPMC_REG_53 */
+ 0x00000000, /* MPMC_REG_54 */
+ 0x00000000, /* MPMC_REG_55 */
+ 0x00000000, /* MPMC_REG_56 */
+ 0x00004000, /* MPMC_REG_57 */
+ 0x03000000, /* MPMC_REG_58 */
+ 0x03031903, /* MPMC_REG_59 */
+ 0x07140c04, /* MPMC_REG_60 */
+ 0x00006456, /* MPMC_REG_61 */
+ 0x00640064, /* MPMC_REG_62 */
+ 0x00640064, /* MPMC_REG_63 */
+ 0x000f0064, /* MPMC_REG_64 */
+ 0x0000000a, /* MPMC_REG_65 */
+ 0x00400100, /* MPMC_REG_66 */
+ 0x10330200, /* MPMC_REG_67 */
+ 0x02001033, /* MPMC_REG_68 */
+ 0x02000200, /* MPMC_REG_69 */
+ 0x10330200, /* MPMC_REG_70 */
+ 0x08300830, /* MPMC_REG_71 */
+ 0x00440044, /* MPMC_REG_72 */
+ 0x00080008, /* MPMC_REG_73 */
+ 0x00000000, /* MPMC_REG_74 */
+ 0xff005555, /* MPMC_REG_75 */
+ 0xaaaa00ff, /* MPMC_REG_76 */
+ 0xff005555, /* MPMC_REG_77 */
+ 0x00000007, /* MPMC_REG_78 */
+ 0x00000000, /* MPMC_REG_79 */
+ 0x00000000, /* MPMC_REG_80 */
+ 0x00070000, /* MPMC_REG_81 */
+ 0x00070007, /* MPMC_REG_82 */
+ 0x00070007, /* MPMC_REG_83 */
+ 0x00000000, /* MPMC_REG_84 */
+ 0x00000000, /* MPMC_REG_85 */
+ 0x00030000, /* MPMC_REG_86 */
+ 0x00030003, /* MPMC_REG_87 */
+ 0x00030003, /* MPMC_REG_88 */
+ 0xffff0010, /* MPMC_REG_89 */
+ 0x00000000, /* MPMC_REG_90 */
+ 0x00000000, /* MPMC_REG_91 */
+ 0x00000000, /* MPMC_REG_92 */
+ 0x00000000, /* MPMC_REG_93 */
+ 0x00000000, /* MPMC_REG_94 */
+ 0x00000000, /* MPMC_REG_95 */
+ 0x02000000, /* MPMC_REG_96 */
+ 0x91d30004, /* MPMC_REG_97 */
+ 0x005b000d, /* MPMC_REG_98 */
+ 0x00000200, /* MPMC_REG_99 */
+ 0x00000000, /* MPMC_REG_100 */
+ 0x00000000, /* MPMC_REG_101 */
+ 0x00000000, /* MPMC_REG_102 */
+ 0x00000000, /* MPMC_REG_103 */
+ 0x00000000, /* MPMC_REG_104 */
+ 0x00000000, /* MPMC_REG_105 */
+ 0x00000000, /* MPMC_REG_106 */
+ 0x00000001, /* MPMC_REG_107 */
+ 0x00000001, /* MPMC_REG_108 */
+ 0x00000001, /* MPMC_REG_109 */
+ 0x00000001, /* MPMC_REG_110 */
+ 0x00000001, /* MPMC_REG_111 */
+ 0x0000ffff, /* MPMC_REG_112 */
+ 0x00000000, /* MPMC_REG_113 */
+ 0x00040ee6, /* MPMC_REG_114 */
+ 0x00000050, /* MPMC_REG_115 */
+ 0x00000050, /* MPMC_REG_116 */
+ 0x00000050, /* MPMC_REG_117 */
+ 0x00000050, /* MPMC_REG_118 */
+ 0x00000050, /* MPMC_REG_119 */
+ 0x00000050, /* MPMC_REG_120 */
+ 0x00000000, /* MPMC_REG_121 */
+ 0x00000000, /* MPMC_REG_122 */
+ 0x000f1133, /* MPMC_REG_123 */
+ 0x00404000, /* MPMC_REG_124 */
+ 0x00404000, /* MPMC_REG_125 */
+ 0x00404000, /* MPMC_REG_126 */
+ 0x00404000, /* MPMC_REG_127 */
+ 0x00404000, /* MPMC_REG_128 */
+ 0x00000002, /* MPMC_REG_129 */
+ 0x1208a108, /* MPMC_REG_130 */
+ 0x1208a108, /* MPMC_REG_131 */
+ 0x1208a108, /* MPMC_REG_132 */
+ 0x1208a108, /* MPMC_REG_133 */
+ 0x1208a108, /* MPMC_REG_134 */
+ 0x01000000, /* MPMC_REG_135 */
+ 0x01000000, /* MPMC_REG_136 */
+ 0x01000000, /* MPMC_REG_137 */
+ 0x01000000, /* MPMC_REG_138 */
+ 0x01000000, /* MPMC_REG_139 */
+ 0x01000000, /* MPMC_REG_140 */
+ 0x01000000, /* MPMC_REG_141 */
+ 0x01000000, /* MPMC_REG_142 */
+ 0x01000000, /* MPMC_REG_143 */
+ 0x01000000, /* MPMC_REG_144 */
+ 0x06db6db6, /* MPMC_REG_145 */
+ 0x06db6db6, /* MPMC_REG_146 */
+ 0x06db6db6, /* MPMC_REG_147 */
+ 0x06db6db6, /* MPMC_REG_148 */
+ 0x06db6db6, /* MPMC_REG_149 */
+ 0x00000000, /* MPMC_REG_150 */
+ 0x00000000, /* MPMC_REG_151 */
+ 0x00000000, /* MPMC_REG_152 */
+ 0x00000000, /* MPMC_REG_153 */
+ 0x00000000, /* MPMC_REG_154 */
+ 0x2498a249, /* MPMC_REG_155 */
+ 0x2498a249, /* MPMC_REG_156 */
+ 0x2498a249, /* MPMC_REG_157 */
+ 0x2498a249, /* MPMC_REG_158 */
+ 0x2498a249, /* MPMC_REG_159 */
+ 0x04803219, /* MPMC_REG_160 */
+ 0x04803219, /* MPMC_REG_161 */
+ 0x04803219, /* MPMC_REG_162 */
+ 0x04803219, /* MPMC_REG_163 */
+ 0x04803219, /* MPMC_REG_164 */
+ 0x00000000, /* MPMC_REG_165 */
+ 0x00000000, /* MPMC_REG_166 */
+ 0x00000000, /* MPMC_REG_167 */
+ 0x00000000, /* MPMC_REG_168 */
+ 0x00000000, /* MPMC_REG_169 */
+ 0x00000000, /* MPMC_REG_170 */
+ 0x00000000, /* MPMC_REG_171 */
+ 0x00000000, /* MPMC_REG_172 */
+ 0x00000000, /* MPMC_REG_173 */
+ 0x00000000, /* MPMC_REG_174 */
+ 0x00000000, /* MPMC_REG_175 */
+ 0x00000000, /* MPMC_REG_176 */
+ 0x00000000, /* MPMC_REG_177 */
+ 0x00000000, /* MPMC_REG_178 */
+ 0x00000000, /* MPMC_REG_179 */
+ 0x00000000, /* MPMC_REG_180 */
+ 0x00000000, /* MPMC_REG_181 */
+ 0x00001033, /* MPMC_REG_182 */
+ 0x00001033, /* MPMC_REG_183 */
+ 0x00000000, /* MPMC_REG_184 */
+ 0x00001033, /* MPMC_REG_185 */
+ 0x00019f8f, /* MPMC_REG_186 */
+ 0x00000000, /* MPMC_REG_187 */
+ 0x00000000, /* MPMC_REG_188 */
+ 0x00000000, /* MPMC_REG_189 */
+ 0x00000000, /* MPMC_REG_190 */
+ 0x00000000, /* MPMC_REG_191 */
+ 0x00000000, /* MPMC_REG_192 */
+ 0x00000000, /* MPMC_REG_193 */
+ 0x00000000, /* MPMC_REG_194 */
+ 0x00000000, /* MPMC_REG_195 */
+ 0x00000000, /* MPMC_REG_196 */
+ 0x00000000, /* MPMC_REG_197 */
+ 0x07000000, /* MPMC_REG_198 */
+ 0x00000007, /* MPMC_REG_199 */
+ 0x00000000, /* MPMC_REG_200 */
+ 0x000091dd, /* MPMC_REG_201 */
+ 0x00000056, /* MPMC_REG_202 */
+ 0x00000000, /* MPMC_REG_203 */
+ 0x00000000, /* MPMC_REG_204 */
+ 0x02000000, /* MPMC_REG_205 */
+ 0x00000000, /* MPMC_REG_206 */
+ 0x000050ff, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..708c87d
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030002, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04030402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04070600, /* MPMC_REG_46 0x04070602 */
+ 0x02000505, /* MPMC_REG_47 0x02000505 */
+ 0x0000000c, /* MPMC_REG_48 0x0000000c */
+ 0x0c040406, /* MPMC_REG_49 0x0c040406 */
+ 0x0600000c, /* MPMC_REG_50 0x0602000c */
+ 0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+ 0x19141200, /* MPMC_REG_52 0x19150f00 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031703, /* MPMC_REG_59 0x03031703 */
+ 0x060f0c04, /* MPMC_REG_60 0x060f0c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+ 0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+ 0x04200420, /* MPMC_REG_71 0x04200420 */
+ 0x00440044, /* MPMC_REG_72 0x00440044 */
+ 0x00000000, /* MPMC_REG_73 0x00000000 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000003, /* MPMC_REG_97 0x6da60003 */
+ 0x0030000a, /* MPMC_REG_98 0x0044000a */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000004, /* MPMC_REG_112 0x0000ffff */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00030d40, /* MPMC_REG_114 0x00030d40 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00304000, /* MPMC_REG_124 0x00304000 */
+ 0x00304000, /* MPMC_REG_125 0x00304000 */
+ 0x00304000, /* MPMC_REG_126 0x00304000 */
+ 0x00304000, /* MPMC_REG_127 0x00304000 */
+ 0x00304000, /* MPMC_REG_128 0x00304000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+ 0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+ 0x00013880, /* MPMC_REG_186 0x00013880 */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x00006db0, /* MPMC_REG_201 0x00006db0 */
+ 0x0000002c, /* MPMC_REG_202 0x00000040 */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
new file mode 100644
index 0000000..8ddd263
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 0x00000100 */
+ 0x00010100, /* MPMC_REG_01 0x00000100 */
+ 0x01000000, /* MPMC_REG_02 0x01000000 */
+ 0x00010100, /* MPMC_REG_03 0x00000100 */
+ 0x00000000, /* MPMC_REG_04 0x00000000 */
+ 0x00010100, /* MPMC_REG_05 0x00010101 */
+ 0x00000001, /* MPMC_REG_06 0x00000001 */
+ 0x00000000, /* MPMC_REG_07 0x00000000 */
+ 0x00000000, /* MPMC_REG_08 0x00000000 */
+ 0x00000000, /* MPMC_REG_09 0x00000000 */
+ 0x00000000, /* MPMC_REG_10 0x00000000 */
+ 0x00000101, /* MPMC_REG_11 0x00000101 */
+ 0x00000101, /* MPMC_REG_12 0x00000101 */
+ 0x01010000, /* MPMC_REG_13 0x01010000 */
+ 0x00000000, /* MPMC_REG_14 0x00000000 */
+ 0x01000000, /* MPMC_REG_15 0x01000000 */
+ 0x00000000, /* MPMC_REG_16 0x00000000 */
+ 0x00000000, /* MPMC_REG_17 0x00000000 */
+ 0x00000201, /* MPMC_REG_18 0x00000201 */
+ 0x02010102, /* MPMC_REG_19 0x02010102 */
+ 0x00020000, /* MPMC_REG_20 0x00020000 */
+ 0x03030002, /* MPMC_REG_21 0x07070000 */
+ 0x02030301, /* MPMC_REG_22 0x00070700 */
+ 0x03030303, /* MPMC_REG_23 0x07000707 */
+ 0x03030403, /* MPMC_REG_24 0x00000007 */
+ 0x03030305, /* MPMC_REG_25 0x03070700 */
+ 0x00000400, /* MPMC_REG_26 0x00000400 */
+ 0x02000100, /* MPMC_REG_27 0x02000100 */
+ 0x04030402, /* MPMC_REG_28 0x04030402 */
+ 0x01000104, /* MPMC_REG_29 0x01000104 */
+ 0x04000000, /* MPMC_REG_30 0x04000000 */
+ 0x0606060a, /* MPMC_REG_31 0x0606060a */
+ 0x06060606, /* MPMC_REG_32 0x06060606 */
+ 0x05050506, /* MPMC_REG_33 0x05050506 */
+ 0x05050505, /* MPMC_REG_34 0x05050505 */
+ 0x04040405, /* MPMC_REG_35 0x04040405 */
+ 0x04040404, /* MPMC_REG_36 0x04040404 */
+ 0x03030304, /* MPMC_REG_37 0x03030304 */
+ 0x03030303, /* MPMC_REG_38 0x03030303 */
+ 0x02020203, /* MPMC_REG_39 0x02020203 */
+ 0x02020202, /* MPMC_REG_40 0x02020202 */
+ 0x01010102, /* MPMC_REG_41 0x01010102 */
+ 0x01010101, /* MPMC_REG_42 0x01010101 */
+ 0x06000c01, /* MPMC_REG_43 0x06000c01 */
+ 0x00000000, /* MPMC_REG_44 0x00000000 */
+ 0x00000204, /* MPMC_REG_45 0x00000204 */
+ 0x04090800, /* MPMC_REG_46 0x04090800 */
+ 0x02000606, /* MPMC_REG_47 0x02000606 */
+ 0x0000000e, /* MPMC_REG_48 0x0000000e */
+ 0x10040407, /* MPMC_REG_49 0x10040407 */
+ 0x0800000d, /* MPMC_REG_50 0x0800000d */
+ 0x3f003f08, /* MPMC_REG_51 0x3f003f08 */
+ 0x191b1800, /* MPMC_REG_52 0x191b1800 */
+ 0x00000028, /* MPMC_REG_53 0x00000028 */
+ 0x00000000, /* MPMC_REG_54 0x00000000 */
+ 0x00000000, /* MPMC_REG_55 0x00000000 */
+ 0x00000000, /* MPMC_REG_56 0x00000000 */
+ 0x00004000, /* MPMC_REG_57 0x00004000 */
+ 0x03000000, /* MPMC_REG_58 0x03000000 */
+ 0x03031903, /* MPMC_REG_59 0x03031903 */
+ 0x08140c04, /* MPMC_REG_60 0x08140c04 */
+ 0x00006400, /* MPMC_REG_61 0x00006456 */
+ 0x00640064, /* MPMC_REG_62 0x00640064 */
+ 0x00640064, /* MPMC_REG_63 0x00640064 */
+ 0x000f0064, /* MPMC_REG_64 0x000f0064 */
+ 0x0000000a, /* MPMC_REG_65 0x0000000a */
+ 0x00400100, /* MPMC_REG_66 0x00400100 */
+ 0x10330200, /* MPMC_REG_67 0x10330200 */
+ 0x02001033, /* MPMC_REG_68 0x02001033 */
+ 0x02000200, /* MPMC_REG_69 0x02000200 */
+ 0x10330200, /* MPMC_REG_70 0x10330200 */
+ 0x08300830, /* MPMC_REG_71 0x08300830 */
+ 0x00460046, /* MPMC_REG_72 0x00460046 */
+ 0x00080008, /* MPMC_REG_73 0x00080008 */
+ 0x00000000, /* MPMC_REG_74 0x00000000 */
+ 0xff005555, /* MPMC_REG_75 0xff005555 */
+ 0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+ 0xff005555, /* MPMC_REG_77 0xff005555 */
+ 0x00000007, /* MPMC_REG_78 0x00000007 */
+ 0x00000000, /* MPMC_REG_79 0x00000000 */
+ 0x00000000, /* MPMC_REG_80 0x00000000 */
+ 0x00070000, /* MPMC_REG_81 0x00070000 */
+ 0x00070007, /* MPMC_REG_82 0x00070007 */
+ 0x00070007, /* MPMC_REG_83 0x00070007 */
+ 0x00000000, /* MPMC_REG_84 0x00000000 */
+ 0x00000000, /* MPMC_REG_85 0x00000000 */
+ 0x00030000, /* MPMC_REG_86 0x00030000 */
+ 0x00030003, /* MPMC_REG_87 0x00030003 */
+ 0x00030003, /* MPMC_REG_88 0x00030003 */
+ 0xffff0010, /* MPMC_REG_89 0xffff0010 */
+ 0x00000000, /* MPMC_REG_90 0x00000000 */
+ 0x00000000, /* MPMC_REG_91 0x00000000 */
+ 0x00000000, /* MPMC_REG_92 0x00000000 */
+ 0x00000000, /* MPMC_REG_93 0x00000000 */
+ 0x00000000, /* MPMC_REG_94 0x00000000 */
+ 0x00000000, /* MPMC_REG_95 0x00000000 */
+ 0x02000000, /* MPMC_REG_96 0x02000000 */
+ 0x00000004, /* MPMC_REG_97 0x00000004 */
+ 0x0040000d, /* MPMC_REG_98 0x0040000d */
+ 0x00000200, /* MPMC_REG_99 0x00000200 */
+ 0x00000000, /* MPMC_REG_100 0x00000000 */
+ 0x00000000, /* MPMC_REG_101 0x00000000 */
+ 0x00000000, /* MPMC_REG_102 0x00000000 */
+ 0x00000000, /* MPMC_REG_103 0x00000000 */
+ 0x00000000, /* MPMC_REG_104 0x00000000 */
+ 0x00000000, /* MPMC_REG_105 0x00000000 */
+ 0x00000000, /* MPMC_REG_106 0x00000000 */
+ 0x00000001, /* MPMC_REG_107 0x00000001 */
+ 0x00000001, /* MPMC_REG_108 0x00000001 */
+ 0x00000001, /* MPMC_REG_109 0x00000001 */
+ 0x00000001, /* MPMC_REG_110 0x00000001 */
+ 0x00000001, /* MPMC_REG_111 0x00000001 */
+ 0x00000006, /* MPMC_REG_112 0x00000006 */
+ 0x00000000, /* MPMC_REG_113 0x00000000 */
+ 0x00040ee6, /* MPMC_REG_114 0x00040ee6 */
+ 0x00000050, /* MPMC_REG_115 0x00000050 */
+ 0x00000050, /* MPMC_REG_116 0x00000050 */
+ 0x00000050, /* MPMC_REG_117 0x00000050 */
+ 0x00000050, /* MPMC_REG_118 0x00000050 */
+ 0x00000050, /* MPMC_REG_119 0x00000050 */
+ 0x00000050, /* MPMC_REG_120 0x00000050 */
+ 0x00000000, /* MPMC_REG_121 0x00000000 */
+ 0x00000000, /* MPMC_REG_122 0x00000000 */
+ 0x000f1133, /* MPMC_REG_123 0x000f1133 */
+ 0x00404000, /* MPMC_REG_124 0x00404000 */
+ 0x00404000, /* MPMC_REG_125 0x00404000 */
+ 0x00404000, /* MPMC_REG_126 0x00404000 */
+ 0x00404000, /* MPMC_REG_127 0x00404000 */
+ 0x00404000, /* MPMC_REG_128 0x00404000 */
+ 0x00000002, /* MPMC_REG_129 0x00000002 */
+ 0x1208a108, /* MPMC_REG_130 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_131 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_132 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_133 0x1208a108 */
+ 0x1208a108, /* MPMC_REG_134 0x1208a108 */
+ 0x01000000, /* MPMC_REG_135 0x01000000 */
+ 0x01000000, /* MPMC_REG_136 0x01000000 */
+ 0x01000000, /* MPMC_REG_137 0x01000000 */
+ 0x01000000, /* MPMC_REG_138 0x01000000 */
+ 0x01000000, /* MPMC_REG_139 0x01000000 */
+ 0x01000000, /* MPMC_REG_140 0x01000000 */
+ 0x01000000, /* MPMC_REG_141 0x01000000 */
+ 0x01000000, /* MPMC_REG_142 0x01000000 */
+ 0x01000000, /* MPMC_REG_143 0x01000000 */
+ 0x01000000, /* MPMC_REG_144 0x01000000 */
+ 0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+ 0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+ 0x00000000, /* MPMC_REG_150 0x00000000 */
+ 0x00000000, /* MPMC_REG_151 0x00000000 */
+ 0x00000000, /* MPMC_REG_152 0x00000000 */
+ 0x00000000, /* MPMC_REG_153 0x00000000 */
+ 0x00000000, /* MPMC_REG_154 0x00000000 */
+ 0x2498a249, /* MPMC_REG_155 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_156 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_157 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_158 0x2498a249 */
+ 0x2498a249, /* MPMC_REG_159 0x2498a249 */
+ 0x04803219, /* MPMC_REG_160 0x04803219 */
+ 0x04803219, /* MPMC_REG_161 0x04803219 */
+ 0x04803219, /* MPMC_REG_162 0x04803219 */
+ 0x04803219, /* MPMC_REG_163 0x04803219 */
+ 0x04803219, /* MPMC_REG_164 0x04803219 */
+ 0x00000000, /* MPMC_REG_165 0x00000000 */
+ 0x00000000, /* MPMC_REG_166 0x00000000 */
+ 0x00000000, /* MPMC_REG_167 0x00000000 */
+ 0x00000000, /* MPMC_REG_168 0x00000000 */
+ 0x00000000, /* MPMC_REG_169 0x00000000 */
+ 0x00000000, /* MPMC_REG_170 0x00000000 */
+ 0x00000000, /* MPMC_REG_171 0x00000000 */
+ 0x00000000, /* MPMC_REG_172 0x00000000 */
+ 0x00000000, /* MPMC_REG_173 0x00000000 */
+ 0x00000000, /* MPMC_REG_174 0x00000000 */
+ 0x00000000, /* MPMC_REG_175 0x00000000 */
+ 0x00000000, /* MPMC_REG_176 0x00000000 */
+ 0x00000000, /* MPMC_REG_177 0x00000000 */
+ 0x00000000, /* MPMC_REG_178 0x00000000 */
+ 0x00000000, /* MPMC_REG_179 0x00000000 */
+ 0x00000000, /* MPMC_REG_180 0x00000000 */
+ 0x00000000, /* MPMC_REG_181 0x00000000 */
+ 0x00001033, /* MPMC_REG_182 0x00001033 */
+ 0x00001033, /* MPMC_REG_183 0x00001033 */
+ 0x00000000, /* MPMC_REG_184 0x00000000 */
+ 0x00001033, /* MPMC_REG_185 0x00001033 */
+ 0x00019f8f, /* MPMC_REG_186 0x00019f8f */
+ 0x00000000, /* MPMC_REG_187 0x00000000 */
+ 0x00000000, /* MPMC_REG_188 0x00000000 */
+ 0x00000000, /* MPMC_REG_189 0x00000000 */
+ 0x00000000, /* MPMC_REG_190 0x00000000 */
+ 0x00000000, /* MPMC_REG_191 0x00000000 */
+ 0x00000000, /* MPMC_REG_192 0x00000000 */
+ 0x00000000, /* MPMC_REG_193 0x00000000 */
+ 0x00000000, /* MPMC_REG_194 0x00000000 */
+ 0x00000000, /* MPMC_REG_195 0x00000000 */
+ 0x00000000, /* MPMC_REG_196 0x00000000 */
+ 0x00000000, /* MPMC_REG_197 0x00000000 */
+ 0x07000000, /* MPMC_REG_198 0x07000000 */
+ 0x00000007, /* MPMC_REG_199 0x00000007 */
+ 0x00000000, /* MPMC_REG_200 0x00000000 */
+ 0x000091dd, /* MPMC_REG_201 0x000091dd */
+ 0x0000003b, /* MPMC_REG_202 0x0000003b */
+ 0x00000000, /* MPMC_REG_203 0x00000000 */
+ 0x00000000, /* MPMC_REG_204 0x00000000 */
+ 0x02000000, /* MPMC_REG_205 0x02000000 */
+ 0x00000000, /* MPMC_REG_206 0x00000000 */
+ 0x000050ff, /* MPMC_REG_207 0x000050ff */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c b/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
new file mode 100644
index 0000000..f986921
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_DDR_MT47H128M16) && \
+ defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 */
+ 0x00010100, /* MPMC_REG_01 */
+ 0x01000000, /* MPMC_REG_02 */
+ 0x00010100, /* MPMC_REG_03 */
+ 0x00000000, /* MPMC_REG_04 */
+ 0x00010100, /* MPMC_REG_05 */
+ 0x00000001, /* MPMC_REG_06 */
+ 0x00000000, /* MPMC_REG_07 */
+ 0x00000000, /* MPMC_REG_08 */
+ 0x00000000, /* MPMC_REG_09 */
+ 0x00000000, /* MPMC_REG_10 */
+ 0x00000101, /* MPMC_REG_11 */
+ 0x00000101, /* MPMC_REG_12 */
+ 0x01010000, /* MPMC_REG_13 */
+ 0x00000000, /* MPMC_REG_14 */
+ 0x01000000, /* MPMC_REG_15 */
+ 0x00000000, /* MPMC_REG_16 */
+ 0x00000000, /* MPMC_REG_17 */
+ 0x00000201, /* MPMC_REG_18 */
+ 0x02010000, /* MPMC_REG_19 */
+ 0x00020000, /* MPMC_REG_20 */
+ 0x03030001, /* MPMC_REG_21 */
+ 0x02030301, /* MPMC_REG_22 */
+ 0x03030303, /* MPMC_REG_23 */
+ 0x03030403, /* MPMC_REG_24 */
+ 0x03030305, /* MPMC_REG_25 */
+ 0x00000400, /* MPMC_REG_26 */
+ 0x02000200, /* MPMC_REG_27 */
+ 0x04030202, /* MPMC_REG_28 */
+ 0x01000103, /* MPMC_REG_29 */
+ 0x03000000, /* MPMC_REG_30 */
+ 0x0606060a, /* MPMC_REG_31 */
+ 0x06060606, /* MPMC_REG_32 */
+ 0x05050506, /* MPMC_REG_33 */
+ 0x05050505, /* MPMC_REG_34 */
+ 0x04040405, /* MPMC_REG_35 */
+ 0x04040404, /* MPMC_REG_36 */
+ 0x03030304, /* MPMC_REG_37 */
+ 0x03030303, /* MPMC_REG_38 */
+ 0x02020203, /* MPMC_REG_39 */
+ 0x02020202, /* MPMC_REG_40 */
+ 0x01010102, /* MPMC_REG_41 */
+ 0x01010101, /* MPMC_REG_42 */
+ 0x04000c01, /* MPMC_REG_43 */
+ 0x00000002, /* MPMC_REG_44 */
+ 0x00000204, /* MPMC_REG_45 */
+ 0x03070600, /* MPMC_REG_46 */
+ 0x02000505, /* MPMC_REG_47 */
+ 0x0000000c, /* MPMC_REG_48 */
+ 0x0c030206, /* MPMC_REG_49 */
+ 0x0200000c, /* MPMC_REG_50 */
+ 0x3f003f06, /* MPMC_REG_51 */
+ 0x19161200, /* MPMC_REG_52 */
+ 0x00000028, /* MPMC_REG_53 */
+ 0x00000000, /* MPMC_REG_54 */
+ 0x00000000, /* MPMC_REG_55 */
+ 0x00000000, /* MPMC_REG_56 */
+ 0x00004000, /* MPMC_REG_57 */
+ 0x03000000, /* MPMC_REG_58 */
+ 0x03031703, /* MPMC_REG_59 */
+ 0x06160504, /* MPMC_REG_60 */
+ 0x00006400, /* MPMC_REG_61 */
+ 0x00640064, /* MPMC_REG_62 */
+ 0x00640064, /* MPMC_REG_63 */
+ 0x000f0064, /* MPMC_REG_64 */
+ 0x0000000a, /* MPMC_REG_65 */
+ 0x00400100, /* MPMC_REG_66 */
+ 0x0c2d0200, /* MPMC_REG_67 */
+ 0x02000c2d, /* MPMC_REG_68 */
+ 0x02000200, /* MPMC_REG_69 */
+ 0x0c2d0200, /* MPMC_REG_70 */
+ 0x0a630a63, /* MPMC_REG_71 */
+ 0x00040004, /* MPMC_REG_72 */
+ 0x00000000, /* MPMC_REG_73 */
+ 0x00000000, /* MPMC_REG_74 */
+ 0xff005555, /* MPMC_REG_75 */
+ 0xaaaa00ff, /* MPMC_REG_76 */
+ 0xff005555, /* MPMC_REG_77 */
+ 0x00000007, /* MPMC_REG_78 */
+ 0x00000000, /* MPMC_REG_79 */
+ 0x00000000, /* MPMC_REG_80 */
+ 0x00070000, /* MPMC_REG_81 */
+ 0x00070007, /* MPMC_REG_82 */
+ 0x00070007, /* MPMC_REG_83 */
+ 0x00000000, /* MPMC_REG_84 */
+ 0x00000000, /* MPMC_REG_85 */
+ 0x00030000, /* MPMC_REG_86 */
+ 0x00030003, /* MPMC_REG_87 */
+ 0x00030003, /* MPMC_REG_88 */
+ 0xffff0010, /* MPMC_REG_89 */
+ 0x00000000, /* MPMC_REG_90 */
+ 0x00000000, /* MPMC_REG_91 */
+ 0x00000000, /* MPMC_REG_92 */
+ 0x00000000, /* MPMC_REG_93 */
+ 0x00000000, /* MPMC_REG_94 */
+ 0x00000000, /* MPMC_REG_95 */
+ 0x00c800a0, /* MPMC_REG_96 */
+ 0x00000003, /* MPMC_REG_97 */
+ 0x0053000a, /* MPMC_REG_98 */
+ 0x000000c8, /* MPMC_REG_99 */
+ 0x00000000, /* MPMC_REG_100 */
+ 0x00000000, /* MPMC_REG_101 */
+ 0x00000000, /* MPMC_REG_102 */
+ 0x00000000, /* MPMC_REG_103 */
+ 0x00000000, /* MPMC_REG_104 */
+ 0x00000000, /* MPMC_REG_105 */
+ 0x00000000, /* MPMC_REG_106 */
+ 0x00000000, /* MPMC_REG_107 */
+ 0x00000000, /* MPMC_REG_108 */
+ 0x00000000, /* MPMC_REG_109 */
+ 0x00000000, /* MPMC_REG_110 */
+ 0x00000000, /* MPMC_REG_111 */
+ 0x00013880, /* MPMC_REG_112 */
+ 0x00000000, /* MPMC_REG_113 */
+ 0x000000c8, /* MPMC_REG_114 */
+ 0x00000050, /* MPMC_REG_115 */
+ 0x00000050, /* MPMC_REG_116 */
+ 0x00000050, /* MPMC_REG_117 */
+ 0x00000050, /* MPMC_REG_118 */
+ 0x00000050, /* MPMC_REG_119 */
+ 0x00000050, /* MPMC_REG_120 */
+ 0x00000000, /* MPMC_REG_121 */
+ 0x00000000, /* MPMC_REG_122 */
+ 0x000f1133, /* MPMC_REG_123 */
+ 0x00386100, /* MPMC_REG_124 */
+ 0x00386100, /* MPMC_REG_125 */
+ 0x00386100, /* MPMC_REG_126 */
+ 0x00386100, /* MPMC_REG_127 */
+ 0x00386100, /* MPMC_REG_128 */
+ 0x00000002, /* MPMC_REG_129 */
+ 0x1208a108, /* MPMC_REG_130 */
+ 0x1208a108, /* MPMC_REG_131 */
+ 0x1208a108, /* MPMC_REG_132 */
+ 0x1208a108, /* MPMC_REG_133 */
+ 0x1208a108, /* MPMC_REG_134 */
+ 0x01000000, /* MPMC_REG_135 */
+ 0x01000000, /* MPMC_REG_136 */
+ 0x01000000, /* MPMC_REG_137 */
+ 0x01000000, /* MPMC_REG_138 */
+ 0x01000000, /* MPMC_REG_139 */
+ 0x01000000, /* MPMC_REG_140 */
+ 0x01000000, /* MPMC_REG_141 */
+ 0x01000000, /* MPMC_REG_142 */
+ 0x01000000, /* MPMC_REG_143 */
+ 0x01000000, /* MPMC_REG_144 */
+ 0x06db6db6, /* MPMC_REG_145 */
+ 0x06db6db6, /* MPMC_REG_146 */
+ 0x06db6db6, /* MPMC_REG_147 */
+ 0x06db6db6, /* MPMC_REG_148 */
+ 0x06db6db6, /* MPMC_REG_149 */
+ 0x00000000, /* MPMC_REG_150 */
+ 0x00000000, /* MPMC_REG_151 */
+ 0x00000000, /* MPMC_REG_152 */
+ 0x00000000, /* MPMC_REG_153 */
+ 0x00000000, /* MPMC_REG_154 */
+ 0x2498a249, /* MPMC_REG_155 */
+ 0x2498a249, /* MPMC_REG_156 */
+ 0x2498a249, /* MPMC_REG_157 */
+ 0x2498a249, /* MPMC_REG_158 */
+ 0x2498a249, /* MPMC_REG_159 */
+ 0x04803219, /* MPMC_REG_160 */
+ 0x04803219, /* MPMC_REG_161 */
+ 0x04803219, /* MPMC_REG_162 */
+ 0x04803219, /* MPMC_REG_163 */
+ 0x04803219, /* MPMC_REG_164 */
+ 0x00000000, /* MPMC_REG_165 */
+ 0x00000000, /* MPMC_REG_166 */
+ 0x00000000, /* MPMC_REG_167 */
+ 0x00000000, /* MPMC_REG_168 */
+ 0x00000000, /* MPMC_REG_169 */
+ 0x00000000, /* MPMC_REG_170 */
+ 0x00000000, /* MPMC_REG_171 */
+ 0x00000000, /* MPMC_REG_172 */
+ 0x00000000, /* MPMC_REG_173 */
+ 0x00000000, /* MPMC_REG_174 */
+ 0x00000000, /* MPMC_REG_175 */
+ 0x00000000, /* MPMC_REG_176 */
+ 0x00000000, /* MPMC_REG_177 */
+ 0x00000000, /* MPMC_REG_178 */
+ 0x00000000, /* MPMC_REG_179 */
+ 0x00000000, /* MPMC_REG_180 */
+ 0x00000000, /* MPMC_REG_181 */
+ 0x00000c2d, /* MPMC_REG_182 */
+ 0x00000c2d, /* MPMC_REG_183 */
+ 0x00000000, /* MPMC_REG_184 */
+ 0x00000c2d, /* MPMC_REG_185 */
+ 0x00000050, /* MPMC_REG_186 */
+ 0x00000000, /* MPMC_REG_187 */
+ 0x00000000, /* MPMC_REG_188 */
+ 0x00000000, /* MPMC_REG_189 */
+ 0x00000000, /* MPMC_REG_190 */
+ 0x00000000, /* MPMC_REG_191 */
+ 0x00000000, /* MPMC_REG_192 */
+ 0x00000000, /* MPMC_REG_193 */
+ 0x00000000, /* MPMC_REG_194 */
+ 0x00000000, /* MPMC_REG_195 */
+ 0x00000000, /* MPMC_REG_196 */
+ 0x00000000, /* MPMC_REG_197 */
+ 0x07000000, /* MPMC_REG_198 */
+ 0x00000007, /* MPMC_REG_199 */
+ 0x00000000, /* MPMC_REG_200 */
+ 0x00006d60, /* MPMC_REG_201 */
+ 0x0000004f, /* MPMC_REG_202 */
+ 0x00000000, /* MPMC_REG_203 */
+ 0x00000000, /* MPMC_REG_204 */
+ 0x00000000, /* MPMC_REG_205 */
+ 0x00000000, /* MPMC_REG_206 */
+ 0x00003ce1, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c b/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
new file mode 100644
index 0000000..3e3b2cd
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_DDR_MT47H128M16) && \
+ defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000100, /* MPMC_REG_00 */
+ 0x00010100, /* MPMC_REG_01 */
+ 0x01000000, /* MPMC_REG_02 */
+ 0x00010100, /* MPMC_REG_03 */
+ 0x00000000, /* MPMC_REG_04 */
+ 0x00010100, /* MPMC_REG_05 */
+ 0x00000001, /* MPMC_REG_06 */
+ 0x00000000, /* MPMC_REG_07 */
+ 0x00000000, /* MPMC_REG_08 */
+ 0x00000000, /* MPMC_REG_09 */
+ 0x00000000, /* MPMC_REG_10 */
+ 0x00000101, /* MPMC_REG_11 */
+ 0x00000101, /* MPMC_REG_12 */
+ 0x01010000, /* MPMC_REG_13 */
+ 0x00000000, /* MPMC_REG_14 */
+ 0x01000000, /* MPMC_REG_15 */
+ 0x00000000, /* MPMC_REG_16 */
+ 0x00000000, /* MPMC_REG_17 */
+ 0x00000201, /* MPMC_REG_18 */
+ 0x02010000, /* MPMC_REG_19 */
+ 0x00020000, /* MPMC_REG_20 */
+ 0x03030001, /* MPMC_REG_21 */
+ 0x02030301, /* MPMC_REG_22 */
+ 0x03030303, /* MPMC_REG_23 */
+ 0x03030403, /* MPMC_REG_24 */
+ 0x03030305, /* MPMC_REG_25 */
+ 0x00000400, /* MPMC_REG_26 */
+ 0x02000200, /* MPMC_REG_27 */
+ 0x06030202, /* MPMC_REG_28 */
+ 0x01000104, /* MPMC_REG_29 */
+ 0x03000000, /* MPMC_REG_30 */
+ 0x0606060a, /* MPMC_REG_31 */
+ 0x06060606, /* MPMC_REG_32 */
+ 0x05050506, /* MPMC_REG_33 */
+ 0x05050505, /* MPMC_REG_34 */
+ 0x04040405, /* MPMC_REG_35 */
+ 0x04040404, /* MPMC_REG_36 */
+ 0x03030304, /* MPMC_REG_37 */
+ 0x03030303, /* MPMC_REG_38 */
+ 0x02020203, /* MPMC_REG_39 */
+ 0x02020202, /* MPMC_REG_40 */
+ 0x01010102, /* MPMC_REG_41 */
+ 0x01010101, /* MPMC_REG_42 */
+ 0x04000c01, /* MPMC_REG_43 */
+ 0x00000002, /* MPMC_REG_44 */
+ 0x00000204, /* MPMC_REG_45 */
+ 0x04080700, /* MPMC_REG_46 */
+ 0x02000606, /* MPMC_REG_47 */
+ 0x0000000e, /* MPMC_REG_48 */
+ 0x0f030207, /* MPMC_REG_49 */
+ 0x0200000d, /* MPMC_REG_50 */
+ 0x3f003f08, /* MPMC_REG_51 */
+ 0x191d1800, /* MPMC_REG_52 */
+ 0x00000028, /* MPMC_REG_53 */
+ 0x00000000, /* MPMC_REG_54 */
+ 0x00000000, /* MPMC_REG_55 */
+ 0x00000000, /* MPMC_REG_56 */
+ 0x00004000, /* MPMC_REG_57 */
+ 0x03000000, /* MPMC_REG_58 */
+ 0x03031903, /* MPMC_REG_59 */
+ 0x07160704, /* MPMC_REG_60 */
+ 0x00006400, /* MPMC_REG_61 */
+ 0x00640064, /* MPMC_REG_62 */
+ 0x00640064, /* MPMC_REG_63 */
+ 0x000f0064, /* MPMC_REG_64 */
+ 0x0000000a, /* MPMC_REG_65 */
+ 0x00400100, /* MPMC_REG_66 */
+ 0x10330200, /* MPMC_REG_67 */
+ 0x02001033, /* MPMC_REG_68 */
+ 0x02000200, /* MPMC_REG_69 */
+ 0x10330200, /* MPMC_REG_70 */
+ 0x0e730e73, /* MPMC_REG_71 */
+ 0x00040004, /* MPMC_REG_72 */
+ 0x00000000, /* MPMC_REG_73 */
+ 0x00000000, /* MPMC_REG_74 */
+ 0xff005555, /* MPMC_REG_75 */
+ 0xaaaa00ff, /* MPMC_REG_76 */
+ 0xff005555, /* MPMC_REG_77 */
+ 0x00000007, /* MPMC_REG_78 */
+ 0x00000000, /* MPMC_REG_79 */
+ 0x00000000, /* MPMC_REG_80 */
+ 0x00070000, /* MPMC_REG_81 */
+ 0x00070007, /* MPMC_REG_82 */
+ 0x00070007, /* MPMC_REG_83 */
+ 0x00000000, /* MPMC_REG_84 */
+ 0x00000000, /* MPMC_REG_85 */
+ 0x00030000, /* MPMC_REG_86 */
+ 0x00030003, /* MPMC_REG_87 */
+ 0x00030003, /* MPMC_REG_88 */
+ 0xffff0010, /* MPMC_REG_89 */
+ 0x00000000, /* MPMC_REG_90 */
+ 0x00000000, /* MPMC_REG_91 */
+ 0x00000000, /* MPMC_REG_92 */
+ 0x00000000, /* MPMC_REG_93 */
+ 0x00000000, /* MPMC_REG_94 */
+ 0x00000000, /* MPMC_REG_95 */
+ 0x00c800d5, /* MPMC_REG_96 */
+ 0x00000003, /* MPMC_REG_97 */
+ 0x006f000d, /* MPMC_REG_98 */
+ 0x000000c8, /* MPMC_REG_99 */
+ 0x00000000, /* MPMC_REG_100 */
+ 0x00000000, /* MPMC_REG_101 */
+ 0x00000000, /* MPMC_REG_102 */
+ 0x00000000, /* MPMC_REG_103 */
+ 0x00000000, /* MPMC_REG_104 */
+ 0x00000000, /* MPMC_REG_105 */
+ 0x00000000, /* MPMC_REG_106 */
+ 0x00000000, /* MPMC_REG_107 */
+ 0x00000000, /* MPMC_REG_108 */
+ 0x00000000, /* MPMC_REG_109 */
+ 0x00000000, /* MPMC_REG_110 */
+ 0x00000000, /* MPMC_REG_111 */
+ 0x00019f8f, /* MPMC_REG_112 */
+ 0x00000000, /* MPMC_REG_113 */
+ 0x0000010a, /* MPMC_REG_114 */
+ 0x00000050, /* MPMC_REG_115 */
+ 0x00000050, /* MPMC_REG_116 */
+ 0x00000050, /* MPMC_REG_117 */
+ 0x00000050, /* MPMC_REG_118 */
+ 0x00000050, /* MPMC_REG_119 */
+ 0x00000050, /* MPMC_REG_120 */
+ 0x00000000, /* MPMC_REG_121 */
+ 0x00000000, /* MPMC_REG_122 */
+ 0x000f1133, /* MPMC_REG_123 */
+ 0x00486100, /* MPMC_REG_124 */
+ 0x00486100, /* MPMC_REG_125 */
+ 0x00486100, /* MPMC_REG_126 */
+ 0x00486100, /* MPMC_REG_127 */
+ 0x00486100, /* MPMC_REG_128 */
+ 0x00000002, /* MPMC_REG_129 */
+ 0x1208a108, /* MPMC_REG_130 */
+ 0x1208a108, /* MPMC_REG_131 */
+ 0x1208a108, /* MPMC_REG_132 */
+ 0x1208a108, /* MPMC_REG_133 */
+ 0x1208a108, /* MPMC_REG_134 */
+ 0x01000000, /* MPMC_REG_135 */
+ 0x01000000, /* MPMC_REG_136 */
+ 0x01000000, /* MPMC_REG_137 */
+ 0x01000000, /* MPMC_REG_138 */
+ 0x01000000, /* MPMC_REG_139 */
+ 0x01000000, /* MPMC_REG_140 */
+ 0x01000000, /* MPMC_REG_141 */
+ 0x01000000, /* MPMC_REG_142 */
+ 0x01000000, /* MPMC_REG_143 */
+ 0x01000000, /* MPMC_REG_144 */
+ 0x06db6db6, /* MPMC_REG_145 */
+ 0x06db6db6, /* MPMC_REG_146 */
+ 0x06db6db6, /* MPMC_REG_147 */
+ 0x06db6db6, /* MPMC_REG_148 */
+ 0x06db6db6, /* MPMC_REG_149 */
+ 0x00000000, /* MPMC_REG_150 */
+ 0x00000000, /* MPMC_REG_151 */
+ 0x00000000, /* MPMC_REG_152 */
+ 0x00000000, /* MPMC_REG_153 */
+ 0x00000000, /* MPMC_REG_154 */
+ 0x2498a249, /* MPMC_REG_155 */
+ 0x2498a249, /* MPMC_REG_156 */
+ 0x2498a249, /* MPMC_REG_157 */
+ 0x2498a249, /* MPMC_REG_158 */
+ 0x2498a249, /* MPMC_REG_159 */
+ 0x04803219, /* MPMC_REG_160 */
+ 0x04803219, /* MPMC_REG_161 */
+ 0x04803219, /* MPMC_REG_162 */
+ 0x04803219, /* MPMC_REG_163 */
+ 0x04803219, /* MPMC_REG_164 */
+ 0x00000000, /* MPMC_REG_165 */
+ 0x00000000, /* MPMC_REG_166 */
+ 0x00000000, /* MPMC_REG_167 */
+ 0x00000000, /* MPMC_REG_168 */
+ 0x00000000, /* MPMC_REG_169 */
+ 0x00000000, /* MPMC_REG_170 */
+ 0x00000000, /* MPMC_REG_171 */
+ 0x00000000, /* MPMC_REG_172 */
+ 0x00000000, /* MPMC_REG_173 */
+ 0x00000000, /* MPMC_REG_174 */
+ 0x00000000, /* MPMC_REG_175 */
+ 0x00000000, /* MPMC_REG_176 */
+ 0x00000000, /* MPMC_REG_177 */
+ 0x00000000, /* MPMC_REG_178 */
+ 0x00000000, /* MPMC_REG_179 */
+ 0x00000000, /* MPMC_REG_180 */
+ 0x00000000, /* MPMC_REG_181 */
+ 0x00001033, /* MPMC_REG_182 */
+ 0x00001033, /* MPMC_REG_183 */
+ 0x00000000, /* MPMC_REG_184 */
+ 0x00001033, /* MPMC_REG_185 */
+ 0x0000006b, /* MPMC_REG_186 */
+ 0x00000000, /* MPMC_REG_187 */
+ 0x00000000, /* MPMC_REG_188 */
+ 0x00000000, /* MPMC_REG_189 */
+ 0x00000000, /* MPMC_REG_190 */
+ 0x00000000, /* MPMC_REG_191 */
+ 0x00000000, /* MPMC_REG_192 */
+ 0x00000000, /* MPMC_REG_193 */
+ 0x00000000, /* MPMC_REG_194 */
+ 0x00000000, /* MPMC_REG_195 */
+ 0x00000000, /* MPMC_REG_196 */
+ 0x00000000, /* MPMC_REG_197 */
+ 0x07000000, /* MPMC_REG_198 */
+ 0x00000007, /* MPMC_REG_199 */
+ 0x00000000, /* MPMC_REG_200 */
+ 0x00009173, /* MPMC_REG_201 */
+ 0x0000006A, /* MPMC_REG_202 */
+ 0x00000000, /* MPMC_REG_203 */
+ 0x00000000, /* MPMC_REG_204 */
+ 0x00000000, /* MPMC_REG_205 */
+ 0x00000000, /* MPMC_REG_206 */
+ 0x000050ff, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/spl-spear1340evb.c b/board/st/spear13xx/spl-spear1340evb.c
new file mode 100644
index 0000000..fb0c539
--- /dev/null
+++ b/board/st/spear13xx/spl-spear1340evb.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+void board_pre_ddrinit(void)
+{
+ /*
+ * Several provisions are present on board for Power Management wrt DDR
+ *
+ * There are 4 controls with the board that it can manipulate
+ * - DDR_SHOFF_1V2 (PLGPIO 21): Shuts off DDR VDD 1V2
+ * - DDR_SHOFF_1V5 (PLGPIO 22): Shuts off DDR VDD 1V5
+ * - EN_DDR_CKE (PLGPIO 88): Enable DDR clock
+ * - EN_DDR_nRST (PLGPIO 89): Provide reset to the DDR
+ */
+
+ /*
+ * The selected configuration is as follows
+ * - DDR_SHOFF_1V2/1V5 : Enable both supply voltages (Enable pull down)
+ * - EN_DDR_CKE, EN_DDR_nRST : Force 0 in GPIO output mode
+ * (Additionally, activate pull down on both signals)
+ */
+ spear1340_configure_pin(21, PMX_PULLDOWN);
+ spear1340_configure_pin(22, PMX_PULLDOWN);
+
+ spear1340_configure_pin(88, PMX_GPIO);
+ spear1340_configure_pin(89, PMX_GPIO);
+ spear1340_plgpio_set(88, 0);
+ spear1340_plgpio_set(89, 0);
+
+ /* Activate PULL DOWN on both EN_DDR_CKE and EN_DDR_nRST */
+ spear1340_configure_pin(88, PMX_PULLDOWN);
+ spear1340_configure_pin(89, PMX_PULLDOWN);
+}
diff --git a/include/configs/spear1340-evb.h b/include/configs/spear1340-evb.h
index 05ae8fb..a5335a3 100644
--- a/include/configs/spear1340-evb.h
+++ b/include/configs/spear1340-evb.h
@@ -87,6 +87,11 @@
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_FSMC_NAND_8BIT
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_DDR_MT41J256M8
+#define CONFIG_SPEAR_DDRFREQ533
+
/* Environment Variable configs */
#if defined(CONFIG_ENV_IS_IN_FLASH)
/* Environment is in serial NOR flash */
diff --git a/include/configs/spear13xx.h b/include/configs/spear13xx.h
index fc40e14..19fc04f 100644
--- a/include/configs/spear13xx.h
+++ b/include/configs/spear13xx.h
@@ -64,9 +64,58 @@
#if defined(CONFIG_ARMV7_CA9LTIMER)
#endif
-/* Internal memory address for spear3xx */
+/* Internal memory address for spear13xx */
#define CONFIG_SYS_INIT_SP_ADDR (0xB3800000 + 0x8000 - \
GENERATED_GBL_DATA_SIZE)
+/* SPL configurations */
+#if defined(CONFIG_SPL)
+ #if !defined(CONFIG_SPL_TEXT_BASE)
+ #define CONFIG_SPL_TEXT_BASE 0xB3801504
+ #endif
+ #if !defined(CONFIG_SYS_SNOR_BOOT_BASE)
+ #define CONFIG_SYS_SNOR_BOOT_BASE 0xE6010000
+ #endif
+ #if !defined(CONFIG_SYS_NAND_BOOT_BASE)
+ #define CONFIG_SYS_NAND_BOOT_BASE 0x00080000
+ #endif
+ #if !defined(CONFIG_SYS_PNOR_BOOT_BASE)
+ #define CONFIG_SYS_PNOR_BOOT_BASE 0xA0020000
+ #endif
+ #if !defined(CONFIG_SYS_MMC_BOOT_FILE)
+ #define CONFIG_SYS_MMC_BOOT_FILE "u-boot.img"
+ #endif
+
+ #define CONFIG_SPEAR13XX_ARM2PHOLD 0xB3800600
+ #define CONFIG_SPEAR13XX_ARM2STACK 0xB3800100
+
+ #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+ #define CONFIG_SPL_MTD_SUPPORT
+ #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/spear13xx"
+ #define CONFIG_SPL_LDSCRIPT \
+ "arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds"
+
+ #if defined(CONFIG_DDR_ECC_ENABLE)
+ #define CONFIG_C3
+ #define CONFIG_SPL_MISC_SUPPORT
+ #endif
+
+ #if defined(CONFIG_DDR_MT41J64M16) || \
+ defined(CONFIG_DDR_MT41J256M8) || \
+ defined(CONFIG_DDR_H5TQ2G63BFRPBC) || \
+ defined(CONFIG_DDR_K4B2G1646CK0) || \
+ defined(CONFIG_DDR_MT41J128M16)
+
+ #define CONFIG_DDR3
+ #elif defined(CONFIG_DDR_MT47H128M16)
+
+ #define CONFIG_DDR2
+ #else
+ #error Define a supported DDR
+ #endif
+#endif
+
#include <configs/spear.h>
#endif /* __CONFIG_SPEAR13XX_H */
diff --git a/spl/Makefile b/spl/Makefile
index e38467a..78cb0a6 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -39,6 +39,7 @@ ifdef SOC
LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
endif
LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o
+
LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o
@@ -53,6 +54,7 @@ LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
+LIBS-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/libmtd.o
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
@@ -65,6 +67,10 @@ ifeq ($(BOARD),spear)
LIBS-y += board/$(BOARDDIR)/ddr/lib$(BOARD)ddr.o
endif
+ifeq ($(BOARD),spear13xx)
+LIBS-y += board/$(BOARDDIR)/ddr/lib$(BOARD)ddr.o
+endif
+
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 6/9] spear320-hmi: Add support for hmi machine
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (3 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 5/9] spear320: Add support for SD/MMC Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 7/9] spear6xx/spear3xx: Add support to boot via NAND device Vipin Kumar
` (2 subsequent siblings)
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
MAINTAINERS | 1 +
board/st/spear/Makefile | 1 +
board/st/spear/spear320hmi.c | 120 +++++++++++++++++++++++++++++++++++++++++
board/st/spear/spear_common.c | 2 +
boards.cfg | 2 +
include/configs/spear320-hmi.h | 117 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 243 insertions(+)
create mode 100644 board/st/spear/spear320hmi.c
create mode 100644 include/configs/spear320-hmi.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b2da94..18e9b6c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -745,6 +745,7 @@ Vipin Kumar <vipin.kumar@st.com>
spear300 ARM926EJS (spear300 Soc)
spear310 ARM926EJS (spear310 Soc)
spear320 ARM926EJS (spear320 Soc)
+ spear320-hmi ARM926EJS (spear320 SoC)
spear600 ARM926EJS (spear600 Soc)
Sergey Lapin <slapin@ossfans.org>
diff --git a/board/st/spear/Makefile b/board/st/spear/Makefile
index f925c19..d2634d8 100644
--- a/board/st/spear/Makefile
+++ b/board/st/spear/Makefile
@@ -38,6 +38,7 @@ endif
COBJS-$(CONFIG_MACH_SPEAR300EVB) += spear300evb.o
COBJS-$(CONFIG_MACH_SPEAR310EVB) += spear310evb.o
COBJS-$(CONFIG_MACH_SPEAR320EVB) += spear320plc.o
+COBJS-$(CONFIG_MACH_SPEAR320HMI) += spear320hmi.o
COBJS-$(CONFIG_MACH_SPEAR600EVB) += spear600evb.o
COBJS := $(sort $(COBJS-y))
diff --git a/board/st/spear/spear320hmi.c b/board/st/spear/spear320hmi.c
new file mode 100644
index 0000000..562bdda
--- /dev/null
+++ b/board/st/spear/spear320hmi.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+
+#if defined(CONFIG_CMD_NAND)
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ spear320_select_mode(SPEAR320_EXTENDED_MODE);
+
+ spear320_pins_default();
+
+ spear320_enable_pins(PMX_I2C0, 0);
+ spear320_enable_pins(PMX_SSP0, 0);
+ spear320_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+ spear320_enable_pins(PMX_FSMCNAND, PMX_NAND_8BIT);
+ spear320_enable_pins(PMX_ETH1_ETH2, PMX_ETH_RMII);
+ spear320_enable_pins(PMX_SDMMC, PMX_SDMMC_CD12);
+
+ /* GPIO50 is used for card power on */
+ spear320_configure_pin(50, PMX_GPIO);
+ spear320_plgpio_set(50, 0);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+void board_nand_init()
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG30) ||
+ ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG31)) {
+
+ fsmc_nand_init(nand);
+ }
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+#if defined(CONFIG_MACB)
+ if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+ CONFIG_MACB0_PHY) >= 0)
+ ret++;
+ if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+ CONFIG_MACB1_PHY) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
+
+#if defined(CONFIG_CMD_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+#if defined(CONFIG_SPEAR_SDHCI)
+ if (spear_sdhci_init(CONFIG_SYS_MMC_BASE, 24000000, 6000000, 0) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/st/spear/spear_common.c b/board/st/spear/spear_common.c
index 2257779..9144dd8 100644
--- a/board/st/spear/spear_common.c
+++ b/board/st/spear/spear_common.c
@@ -47,6 +47,8 @@ int checkboard(void)
printf("BOARD: SPEAr310-EVB\n");
#elif defined(CONFIG_MACH_SPEAR320EVB)
printf("BOARD: SPEAr320-PLC\n");
+#elif defined(CONFIG_MACH_SPEAR320HMI)
+ printf("BOARD: SPEAr320-HMI\n");
#elif defined(CONFIG_MACH_SPEAR600EVB)
printf("BOARD: SPEAr600-EVB\n");
#else
diff --git a/boards.cfg b/boards.cfg
index 3b0348a..0375e9e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -210,6 +210,8 @@ spear320 arm arm926ejs spear st
spear320_pnor arm arm926ejs spear st spear spear320-evb:spear320,pnor
spear320_nand arm arm926ejs spear st spear spear320-evb:spear320,nand
spear320_usbtty arm arm926ejs spear st spear spear320-evb:spear320,usbtty
+spear320_hmi arm arm926ejs spear st spear spear320-hmi:spear320
+spear320_hmi_nand arm arm926ejs spear st spear spear320-hmi:spear320,nand
spear600 arm arm926ejs spear st spear spear600-evb:spear600
spear600_nand arm arm926ejs spear st spear spear600-evb:spear600,nand
spear600_usbtty arm arm926ejs spear st spear spear600-evb:spear600,usbtty
diff --git a/include/configs/spear320-hmi.h b/include/configs/spear320-hmi.h
new file mode 100644
index 0000000..4649ed4
--- /dev/null
+++ b/include/configs/spear320-hmi.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_usbtty)
+ #define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+ #define CONFIG_ENV_IS_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_MACH_SPEAR320HMI
+#define CONFIG_MACH_TYPE MACH_TYPE_SPEAR320
+
+/* ARASAN SD MMC configuration */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_SPEAR_SDHCI
+#endif
+
+/* MACB configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_MACB
+ #define CONFIG_MACB0_PHY 0x01
+ #define CONFIG_MACB1_PHY 0x00
+#endif
+
+/* Designware I2C configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_I2C
+ #define CONFIG_I2C_CHIPADDRESS 0x50
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0x02
+#endif
+
+/* AMBA PL011 configurations */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX 0
+
+/* GPIO configurations */
+#define CONFIG_SPEAR_GPIO
+
+/* USB EHCI configurations */
+#if !defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_USB_EHCI_SPEAR
+#endif
+
+/* Designware UDC configurations */
+#if defined(CONFIG_SPEAR_USBTTY)
+ #define CONFIG_DW_UDC
+#endif
+
+/* FSMC NAND configurations */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+/* Flash configurations */
+#define CONFIG_ST_SMI
+
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_SPEAR_DDR_2HCLK
+#define CONFIG_DDR_MT47H64M16
+
+/* Environment Variable configs */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ /* Environment is in serial NOR flash */
+ #define CONFIG_ENV_ADDR 0xF8060000
+ #define CONFIG_ENV_SECT_SIZE 0x00010000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock5 "
+ #define CONFIG_BOOTCOMMAND \
+ "bootm 0xf8080000 - 0xf8070000"
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ /* Environment is in NAND */
+ #define CONFIG_ENV_OFFSET 0x00140000
+ #define CONFIG_SPEAR_ROOTFSBLK "/dev/mtdblock11 "
+
+ #define CONFIG_BOOTCOMMAND "" \
+ "nand read.jffs2 0x800000 0x180000 0x020000; " \
+ "nand read.jffs2 0x900000 0x1c0000 0x4C0000; " \
+ "bootm 0x900000 - 0x800000"
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "root="CONFIG_SPEAR_ROOTFSBLK \
+ "rootfstype=jffs2"
+
+#define CONFIG_BOARD_EXTRA_ENV "" \
+ "loados=tftpboot 0x900000 $(rootpath)/spear3xx_uImage\0" \
+ "loaddtb=tftpboot 0x800000 $(rootpath)/spear320-hmi.dtb\0"
+
+#include <configs/spear320.h>
+#endif /* __CONFIG_H */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 06/11] spear: Read ethaddr from I2C memory
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (3 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 05/11] spear: Append MISC_ as prefix to misc register bitmasks Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 07/11] spear: Cleanup SoC area Vipin Kumar
` (4 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
spear600evb and spear300evb place ethaddr on a I2C memory. This patch cleans up
reading of ethaddr
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
board/st/spear/spear300evb.c | 5 ++++
board/st/spear/spear600evb.c | 7 ++++++
board/st/spear/spear_common.c | 55 +++++++++++++++++++++++++++----------------
3 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/board/st/spear/spear300evb.c b/board/st/spear/spear300evb.c
index 2c7ccd6..46a5922 100644
--- a/board/st/spear/spear300evb.c
+++ b/board/st/spear/spear300evb.c
@@ -68,6 +68,11 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM)
+ uchar mac_id[6];
+ if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+ eth_setenv_enetaddr("ethaddr", mac_id);
+#endif
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
ret++;
diff --git a/board/st/spear/spear600evb.c b/board/st/spear/spear600evb.c
index 61cea50..b5901e6 100644
--- a/board/st/spear/spear600evb.c
+++ b/board/st/spear/spear600evb.c
@@ -60,11 +60,18 @@ void board_nand_init()
int board_eth_init(bd_t *bis)
{
int ret = 0;
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM)
+ uchar mac_id[6];
+#endif
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
#if defined(CONFIG_DW_AUTONEG)
interface = PHY_INTERFACE_MODE_GMII;
#endif
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM)
+ if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+ eth_setenv_enetaddr("ethaddr", mac_id);
+#endif
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
interface) >= 0)
ret++;
diff --git a/board/st/spear/spear_common.c b/board/st/spear/spear_common.c
index c760229..71e9348 100644
--- a/board/st/spear/spear_common.c
+++ b/board/st/spear/spear_common.c
@@ -36,9 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer);
-#endif
void lowlevel_init(void)
{
}
@@ -125,26 +122,33 @@ int spear_board_init(ulong mach_type)
return 0;
}
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer)
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM) && defined(CONFIG_CMD_NET) && \
+ defined(CONFIG_CMD_I2C)
+int i2c_read_mac(uchar *buffer)
{
u8 buf[2];
- i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+ /*
+ * A magic ID which is present at offset 0 and reads 0x55AA represents
+ * whether MACID is present starting at offset 2
+ */
+ i2c_read(CONFIG_I2C_CHIPADDRESS, 0, 1, buf, 2);
/* Check if mac in i2c memory is valid */
- if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+ if ((buf[0] == 0x55) && (buf[1] == 0xAA)) {
/* Valid mac address is saved in i2c eeprom */
- i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+ i2c_read(CONFIG_I2C_CHIPADDRESS, 0x2, 1, buffer, 6);
return 0;
}
return -1;
}
-static int write_mac(uchar *mac)
+static int i2c_write_mac(uchar *mac)
{
u8 buf[2];
+ u8 temp[MAC_LEN];
+ int i;
buf[0] = (u8)MAGIC_BYTE0;
buf[1] = (u8)MAGIC_BYTE1;
@@ -158,8 +162,15 @@ static int write_mac(uchar *mac)
/* check if valid MAC address is saved in I2C EEPROM or not? */
if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
- puts("I2C EEPROM written with mac address \n");
- return 0;
+
+ for (i = 0; i < MAC_LEN; i++)
+ temp[i] = ~mac[i];
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, temp, MAC_LEN);
+
+ if (!memcmp(mac, temp, MAC_LEN)) {
+ puts("I2C EEPROM written with mac address\n");
+ return 0;
+ }
}
puts("I2C EEPROM writing failed\n");
@@ -171,7 +182,8 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
void (*sram_setfreq) (unsigned int, unsigned int);
unsigned int frequency;
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM) && defined(CONFIG_CMD_NET) && \
+ defined(CONFIG_CMD_I2C)
unsigned char mac[6];
#endif
@@ -199,7 +211,8 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM) && defined(CONFIG_CMD_NET) && \
+ defined(CONFIG_CMD_I2C)
} else if (!strcmp(argv[1], "ethaddr")) {
u32 reg;
@@ -209,19 +222,18 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (s)
s = (*e) ? e + 1 : e;
}
- write_mac(mac);
+ i2c_write_mac(mac);
return 0;
-#endif
} else if (!strcmp(argv[1], "print")) {
-#if defined(CONFIG_CMD_NET)
if (!i2c_read_mac(mac)) {
printf("Ethaddr (from i2c mem) = %pM\n", mac);
} else {
printf("Ethaddr (from i2c mem) = Not set\n");
}
-#endif
+
return 0;
+#endif
}
return cmd_usage(cmdtp);
@@ -229,8 +241,11 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
"configure chip",
- "chip_config cpufreq/ddrfreq frequency\n"
-#if defined(CONFIG_CMD_NET)
+ "chip_config cpufreq/ddrfreq frequency"
+#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM) && defined(CONFIG_CMD_NET) && \
+ defined(CONFIG_CMD_I2C)
+ "\n"
"chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+ "chip_config print"
#endif
- "chip_config print");
+ "");
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 06/19] usbh/ehci: Increase timeout for enumeration
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (3 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 05/19] mtd/st_smi: Use page sizes respective to flash Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 07/19] sdhci: Add sdhci support for spear devices Vipin Kumar
` (11 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Few pen drives take longer than usual for enumeration. The u-boot unlike linux
does not depend on interrupts and works in polling and timeout mode.
This patch increases this timeout to increase the set of usb sticks that can be
enumerated by u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
common/usb_hub.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e4a1201..24de9b7 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -393,17 +393,34 @@ static int usb_hub_configure(struct usb_device *dev)
"" : "no ");
usb_hub_power_on(hub);
+ mdelay(1500);
+
for (i = 0; i < dev->maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret < 0) {
+ USB_HUB_PRINTF("get_port_status failed\n");
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts->wPortStatus);
+ portchange = le16_to_cpu(portsts->wPortChange);
+
+ if ((portchange & USB_PORT_STAT_C_CONNECTION) &&
+ (portstatus & USB_PORT_STAT_CONNECTION))
+ break;
- if (usb_get_port_status(dev, i + 1, portsts) < 0) {
- USB_HUB_PRINTF("get_port_status failed\n");
+ mdelay(100);
+ } while (get_timer(start) < CONFIG_SYS_HZ * 10);
+
+ if (ret < 0)
continue;
- }
- portstatus = le16_to_cpu(portsts->wPortStatus);
- portchange = le16_to_cpu(portsts->wPortChange);
USB_HUB_PRINTF("Port %d Status %X Change %X\n",
i + 1, portstatus, portchange);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 07/19] sdhci: Add sdhci support for spear devices
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (4 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 06/19] usbh/ehci: Increase timeout for enumeration Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 08/19] net/designware: Do not select MIIPORT for RGMII interface Vipin Kumar
` (10 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/mmc/Makefile | 1 +
drivers/mmc/spear_sdhci.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 drivers/mmc/spear_sdhci.c
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index a1dd730..01dd61d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -45,6 +45,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS-$(CONFIG_DWMMC) += dw_mmc.o
diff --git a/drivers/mmc/spear_sdhci.c b/drivers/mmc/spear_sdhci.c
new file mode 100644
index 0000000..23f1f4b
--- /dev/null
+++ b/drivers/mmc/spear_sdhci.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+ struct sdhci_host *host = NULL;
+ host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+ if (!host) {
+ printf("sdhci host malloc fail!\n");
+ return 1;
+ }
+
+ host->name = "sdhci";
+ host->ioaddr = (void *)regbase;
+ host->quirks = quirks;
+
+ if (quirks & SDHCI_QUIRK_REG32_RW)
+ host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+ else
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ add_sdhci(host, max_clk, min_clk);
+ return 0;
+}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr13xx PATCH 7/7] spear1310evb: Add SPL support
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
` (4 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 6/7] spear1340evb: Add SPL support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Enable SPL support for spear1310evb board. The spl binaries are generated in
$(obj)/spl directory.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/armv7/spear13xx/Makefile | 1 +
arch/arm/cpu/armv7/spear13xx/spl-spear1310.c | 230 +++++++++++++++++++++
.../include/asm/arch-spear13xx/spear1310_misc.h | 100 +++++++--
board/st/spear13xx/config.mk | 3 -
board/st/spear13xx/spl-spear1310evb.c | 50 +++++
include/configs/spear1310-evb.h | 5 +
spl/Makefile | 1 +
7 files changed, 366 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
create mode 100644 board/st/spear13xx/spl-spear1310evb.c
diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
index daeffa2..fa3c841 100644
--- a/arch/arm/cpu/armv7/spear13xx/Makefile
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_read.o
COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_write.o
COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-swlvl.o
COBJS-$(CONFIG_SOC_SPEAR1340) += spl-spear1340.o
+COBJS-$(CONFIG_SOC_SPEAR1310) += spl-spear1310.o
endif
COBJS := $(sort $(COBJS-y))
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c b/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
new file mode 100644
index 0000000..263d2e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/mpmc.h>
+
+static void pll_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 usbphycfg;
+
+ /* Initialize PLLs */
+ writel(SPEAR1310_FREQ_1000, &misc_p->pll1_frq);
+ writel(readl(&misc_p->pll1_ctr) | SPEAR1310_PLLENABLE,
+ &misc_p->pll1_ctr);
+
+ writel(SPEAR1310_FREQ_125, &misc_p->pll2_frq);
+ writel(readl(&misc_p->pll2_ctr) | SPEAR1310_PLLENABLE,
+ &misc_p->pll2_ctr);
+
+ writel(SPEAR1310_FREQ_332, &misc_p->pll3_frq);
+ writel(readl(&misc_p->pll3_ctr) | SPEAR1310_PLLENABLE,
+ &misc_p->pll3_ctr);
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+ writel(SPEAR1310_FREQ_400, &misc_p->pll4_frq);
+#elif defined(CONFIG_SPEAR_DDRFREQ533)
+ writel(SPEAR1310_FREQ_533, &misc_p->pll4_frq);
+#else
+#error Define one of the valid DDR frequency(CONFIG_SPEAR_DDRFREQ[533/400])
+#endif
+ /* strobing required for pll4 */
+ writel(0x60A, &misc_p->pll4_ctr);
+ writel(0x60E, &misc_p->pll4_ctr);
+ writel(0x606, &misc_p->pll4_ctr);
+ writel(0x60E, &misc_p->pll4_ctr);
+
+ usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+ usbphycfg &= ~(SPEAR1310_COMMON_PWDN | SPEAR1310_USBPHY_POR);
+ usbphycfg |= SPEAR1310_USBPHY_RST;
+ writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+ while (!(readl(&misc_p->usbphy_gen_cfg) & SPEAR1310_USB_PLL_LOCK))
+ ;
+ usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+
+ usbphycfg |= SPEAR1310_AUTOPPD_ON_OVRCURR | \
+ SPEAR1310_UTMI_XFER_RST0 | \
+ SPEAR1310_UTMI_XFER_RST1 | \
+ SPEAR1310_UTMI_XFER_RST2;
+
+ writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+ /* wait for pll locks */
+ while (!(readl(&misc_p->pll1_ctr) & SPEAR1310_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll2_ctr) & SPEAR1310_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll3_ctr) & SPEAR1310_PLLLOCK))
+ ;
+ while (!(readl(&misc_p->pll4_ctr) & SPEAR1310_PLLLOCK))
+ ;
+}
+
+static void sys_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 sysclkctrl;
+
+ /* Set system state to SLOW */
+ sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+ sysclkctrl &= ~SPEAR1310_SYS_MODE_MASK;
+ sysclkctrl |= SPEAR1310_XTAL_TIMEOUT_ENB | \
+ SPEAR1310_PLL_TIMEOUT_ENB | \
+ SPEAR1310_SYS_MODE_REQ_SLOW;
+ writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+ writel(SPEAR1310_PLL_TIM, &misc_p->sys_clk_plltimer);
+ writel(SPEAR1310_OSCI_TIM, &misc_p->sys_clk_oscitimer);
+
+ /* Initialize PLLs */
+ pll_init();
+
+ /* Set system state to NORMAL */
+ sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+ sysclkctrl &= ~SPEAR1310_SYS_MODE_MASK;
+ sysclkctrl |= SPEAR1310_XTAL_TIMEOUT_ENB | \
+ SPEAR1310_PLL_TIMEOUT_ENB | \
+ SPEAR1310_SYS_MODE_REQ_NORMAL;
+ writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+ /* Wait for system to switch to normal mode */
+ while ((readl(&misc_p->sys_clk_ctrl) & SPEAR1310_SYS_STATE_MASK) !=
+ SPEAR1310_SYS_STATE_NORMAL)
+ ;
+
+#if defined(CONFIG_C3)
+ writel(readl(&misc_p->perip1_clk_enb) | SPEAR1310_C3_CLKEN,
+ &misc_p->perip1_clk_enb);
+#endif
+}
+
+static void ddr_clock_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+ u32 perip_clkcfg, perip2_clkenb, perip2_swrst;
+
+ perip_clkcfg = readl(&misc_p->perip_clk_cfg);
+ perip_clkcfg |= SPEAR1310_MPMCCLKPLL4;
+ writel(perip_clkcfg, &misc_p->perip_clk_cfg);
+
+ perip2_clkenb = readl(&misc_p->perip2_clk_enb);
+ perip2_clkenb |= SPEAR1310_DDRCTRL_CLKEN | SPEAR1310_DDRCORE_CLKEN;
+ writel(perip2_clkenb, &misc_p->perip2_clk_enb);
+
+ perip2_swrst = readl(&misc_p->perip2_sw_rst);
+ perip2_swrst |= SPEAR1310_DDRCTRL_RST | SPEAR1310_DDRCORE_RST;
+ writel(perip2_swrst, &misc_p->perip2_sw_rst);
+
+ perip2_swrst = readl(&misc_p->perip2_sw_rst);
+ perip2_swrst &= ~(SPEAR1310_DDRCTRL_RST | SPEAR1310_DDRCORE_RST);
+ writel(perip2_swrst, &misc_p->perip2_sw_rst);
+}
+
+static void ddr_pad_compensation(u8 enable)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ if (enable) {
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+ writel(0x00000400, &misc_p->compensation_ddr_cfg);
+
+ /* wait for comzcrdy done */
+ while (!(readl(&misc_p->compensation_ddr_cfg) & 0x1))
+ ;
+ } else {
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ writel(0x00000000, &misc_p->compensation_ddr_cfg);
+ }
+}
+
+void ddr_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+#if defined(CONFIG_DDR_ECC_ENABLE)
+ u32 mpmc_cfg;
+#endif
+
+ /* Clock related settings for DDR */
+ ddr_clock_init();
+
+#if defined(CONFIG_DDR_ECC_ENABLE)
+ /*
+ * Following modifies write access as non-bufferable
+ * and read to happen word by word. Without this
+ * dependent write-read are happening out of order
+ * resulting in Linux crash.
+ */
+ mpmc_cfg = readl(&misc_p->mpmc_cfg);
+ mpmc_cfg |= SPEAR1310_AXI0_AWCOBUF | SPEAR1310_AXI2_AWCOBUF;
+ mpmc_cfg &= ~(SPEAR1310_AXI0_CMDTHRESH_MSK | \
+ SPEAR1310_AXI2_CMDTHRESH_MSK);
+ mpmc_cfg |= (SPEAR1310_AXI0_CMDTHRESH_1 | SPEAR1310_AXI2_CMDTHRESH_1);
+ writel(mpmc_cfg, &misc_p->mpmc_cfg);
+
+ /* enable MPMC ECC gasket for all AXI ports */
+ writel(0x0, &misc_p->mpmc_ctr_sts);
+
+ /* wait for turn-on */
+ while ((readl(&misc_p->mpmc_ctr_sts) & 0xFFF))
+ ;
+#endif
+
+ /* Initialize mpmc register values */
+ spear13xx_mpmc_init((u32 *)CONFIG_SYS_MPMC_BASE, CONFIG_SPEAR_MPMCREGS);
+
+ writel(SPEAR1310_PAD_VREF | SPEAR1310_DATA_PROGB | \
+ SPEAR1310_DATA_PROGA | SPEAR1310_CLK_PROGB | \
+ SPEAR1310_CLK_PROGA | SPEAR1310_CTRL_PROGB | \
+ SPEAR1310_CTRL_PROGA,
+ &misc_p->ddr_pad_cfg);
+
+ ddr_pad_compensation(0);
+ spear13xx_ddr_level();
+ ddr_pad_compensation(1);
+}
+
+void soc_init(void)
+{
+ struct spear1310_misc_regs *const misc_p =
+ (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+ /* Initialize PLLs */
+ sys_init();
+
+ /* Enable IPs (release reset) */
+ writel(SPEAR1310_PERIPH1_RST_ALL, &misc_p->perip1_sw_rst);
+ writel(SPEAR1310_PERIPH2_RST_ALL, &misc_p->perip2_sw_rst);
+ writel(SPEAR1310_RAS_RST_ALL, &misc_p->ras_sw_rst);
+}
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
index 8d8278e..0d78b05 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
@@ -22,8 +22,8 @@
* MA 02111-1307 USA
*/
-#ifndef __SPEAR1310_REVC_MISC_H
-#define __SPEAR1310_REVC_MISC_H
+#ifndef __SPEAR1310_MISC_H
+#define __SPEAR1310_MISC_H
struct spear1310_misc_regs {
u32 soc_cfg; /* 0x000 */
@@ -238,27 +238,35 @@ struct spear1310_misc_regs {
u32 misc_cfg; /* 0x1004 */
};
-/* PHERIP1_CLOCK ENABLE */
-#define SPEAR1310_C3_CLKEN 0x20000000
-#define SPEAR1310_GPT1_CLKEN 0x00200000
-#define SPEAR1310_I2C_CLKEN 0x00040000
-#define SPEAR1310_SSP_CLKEN 0x00020000
-#define SPEAR1310_UART_CLKEN 0x00008000
-#define SPEAR1310_UDC_UPD_CLKEN 0x00000800
-#define SPEAR1310_UHC1_CLKEN 0x00000200
-#define SPEAR1310_GETH_CLKEN 0x00000100
-#define SPEAR1310_SD_CLKEN 0x00000040
-#define SPEAR1310_SMI_CLKEN 0x00000020
-#define SPEAR1310_FSMC_CLKEN 0x00000010
+/* sys_clk_ctrl definitions */
+#define SPEAR1310_SYS_MODE_MASK 0x00000007
+#define SPEAR1310_SYS_MODE_REQ_DOZE 0x00000001
+#define SPEAR1310_SYS_MODE_REQ_SLOW 0x00000002
+#define SPEAR1310_SYS_MODE_REQ_NORMAL 0x00000004
+#define SPEAR1310_PLL_TIMEOUT_ENB 0x00000008
+#define SPEAR1310_XTAL_TIMEOUT_ENB 0x00000010
+#define SPEAR1310_SYS_STATE_MASK 0x000F0000
+#define SPEAR1310_SYS_STATE_NORMAL 0x000F0000
-/* perip1_sw_rst */
-#define SPEAR1310_C3_SWRST 0x20000000
-#define SPEAR1310_UDC_UPD_SWRST 0x00000800
-#define SPEAR1310_UHC1_SWRST 0x00000200
+/* sys_clk_*timer definitions */
+#define SPEAR1310_PLL_TIM 0x000007f8
+#define SPEAR1310_OSCI_TIM 0x000007f8
+
+/* pll_freq definitions in MHz */
+#define SPEAR1310_FREQ_1000 0x7D000006
+#define SPEAR1310_FREQ_533 0x6F000105
+#define SPEAR1310_FREQ_400 0x64000106
+#define SPEAR1310_FREQ_332 0x53000203
+#define SPEAR1310_FREQ_125 0x7D000306
+
+/* pll_ctr definitions */
+#define SPEAR1310_PLLLOCK 0x00000001
+#define SPEAR1310_PLLENABLE 0x00000004
/* perip_clk_cfg definitions */
-#define SPEAR1310_UART48M 0x00000000
+#define SPEAR1310_MPMCCLKPLL4 0x00000400
#define SPEAR1310_UARTCLKMSK 0x00000030
+#define SPEAR1310_UART48M 0x00000000
/* gmac_clk_cfg definitions */
#define SPEAR1310_PHYIF_MSK 0x00000070
@@ -273,10 +281,14 @@ struct spear1310_misc_regs {
/* usbphy_gen_cfg definitions */
#define SPEAR1310_USB_PLL_LOCK 0x01000000
+#define SPEAR1310_UTMI_XFER_RST2 0x00010000
+#define SPEAR1310_UTMI_XFER_RST1 0x00008000
+#define SPEAR1310_UTMI_XFER_RST0 0x00004000
#define SPEAR1310_USBUTMI_RST 0x00008000
#define SPEAR1310_USBPHY_RST 0x00002000
#define SPEAR1310_USBPHY_POR 0x00001000
-#define SPEAR1310_COMMON_PWDN 0x00000000
+#define SPEAR1310_AUTOPPD_ON_OVRCURR 0x00000020
+#define SPEAR1310_COMMON_PWDN 0x00000001
/* perip_cfg definitions */
#define SPEAR1310_MCIF_MSK 0x00000060
@@ -288,13 +300,59 @@ struct spear1310_misc_regs {
#define SPEAR1310_NANDCS0_NORCS6 0x00000004
#define SPEAR1310_NANDCS0_NORCS7 0x00000008
+/* mpmc_cfg definitions */
+#define SPEAR1310_AXI2_AWCOBUF 0x04000000
+#define SPEAR1310_AXI0_AWCOBUF 0x01000000
+#define SPEAR1310_AXI2_CMDTHRESH_MSK 0x00000F00
+#define SPEAR1310_AXI2_CMDTHRESH_1 0x00000100
+#define SPEAR1310_AXI0_CMDTHRESH_MSK 0x0000000F
+#define SPEAR1310_AXI0_CMDTHRESH_1 0x00000001
+
/* synth registers definitions */
#define SPEAR1310_SYNT_CLKENB 0x80000000
-#define SPEAR1310_SYNT_FIN_FULL 0x04000000
+#define SPEAR1310_SYNT_FINFULL 0x04000000
#define SPEAR1310_SYNT_X_1 0x00010000
#define SPEAR1310_SYNT_X_2 0x00020000
#define SPEAR1310_SYNT_Y_2 0x00000002
#define SPEAR1310_SYNT_Y_5 0x00000005
#define SPEAR1310_SYNT_Y_21 0x00000015
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1310_C3_CLKEN 0x20000000
+#define SPEAR1310_GPT1_CLKEN 0x00200000
+#define SPEAR1310_I2C_CLKEN 0x00040000
+#define SPEAR1310_SSP_CLKEN 0x00020000
+#define SPEAR1310_UART_CLKEN 0x00008000
+#define SPEAR1310_UDC_UPD_CLKEN 0x00000800
+#define SPEAR1310_UHC1_CLKEN 0x00000200
+#define SPEAR1310_GETH_CLKEN 0x00000100
+#define SPEAR1310_SD_CLKEN 0x00000040
+#define SPEAR1310_SMI_CLKEN 0x00000020
+#define SPEAR1310_FSMC_CLKEN 0x00000010
+#define SPEAR1310_DDRCORE_CLKEN 0x00000002
+#define SPEAR1310_DDRCTRL_CLKEN 0x00000001
+
+/* perip1_sw_rst */
+#define SPEAR1310_C3_SWRST 0x20000000
+#define SPEAR1310_UDC_UPD_SWRST 0x00000800
+#define SPEAR1310_UHC1_SWRST 0x00000200
+#define SPEAR1310_DDRCORE_RST 0x00000002
+#define SPEAR1310_DDRCTRL_RST 0x00000001
+#define SPEAR1310_PERIPH1_RST_ALL 0x00000000
+#define SPEAR1310_PERIPH2_RST_ALL 0x00000000
+#define SPEAR1310_RAS_RST_ALL 0x00000000
+
+
+/* ddr_pad_cfg definitions */
+#define SPEAR1310_PAD_VREF 0x00000200
+#define SPEAR1310_DATA_PROGB 0x00000100
+#define SPEAR1310_DATA_PROGA 0x00000080
+#define SPEAR1310_CLK_PROGB 0x00000040
+#define SPEAR1310_CLK_PROGA 0x00000020
+#define SPEAR1310_CTRL_PROGB 0x00000010
+#define SPEAR1310_CTRL_PROGA 0x00000008
+#define SPEAR1310_DDR3_PAD_SW_SEL 0x00000004
+#define SPEAR1310_DDR3_PAD_SEL 0x00000002
+#define SPEAR1310_DDR3_SW_SEL 0x00000001
+
#endif
diff --git a/board/st/spear13xx/config.mk b/board/st/spear13xx/config.mk
index a8f67d4..49cc280 100644
--- a/board/st/spear13xx/config.mk
+++ b/board/st/spear13xx/config.mk
@@ -23,8 +23,5 @@
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.img
-
-ifdef CONFIG_MACH_SPEAR1340EVB
ALL-y += $(obj)spl/u-boot-spl.img
endif
-endif
diff --git a/board/st/spear13xx/spl-spear1310evb.c b/board/st/spear13xx/spl-spear1310evb.c
new file mode 100644
index 0000000..fe11eb5
--- /dev/null
+++ b/board/st/spear13xx/spl-spear1310evb.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+
+void board_pre_ddrinit(void)
+{
+ /*
+ * Several provisions are present on board for Power Management wrt DDR
+ *
+ * There are 2 controls with the board that it can manipulate
+ * - PLGPIO 145: Controls DDR_CKE
+ * - PLGPIO 146: Controls DDR_nRESET
+ */
+
+ /*
+ * The selected configuration is as follows
+ * - DDR_nRESET, DDR_CKE : Force 0 in GPIO output mode
+ * (Additionally, activate pull down on both signals)
+ */
+ spear1310_configure_pin(145, PMX_GPIO);
+ spear1310_configure_pin(146, PMX_GPIO);
+ spear1310_plgpio_set(145, 0);
+ spear1310_plgpio_set(146, 0);
+
+ /* Activate PULL DOWN on both EN_DDR_CKE and EN_DDR_nRST */
+ spear1310_configure_pin(145, PMX_PULLDOWN);
+ spear1310_configure_pin(146, PMX_PULLDOWN);
+}
diff --git a/include/configs/spear1310-evb.h b/include/configs/spear1310-evb.h
index 6c21cf4..b36c644 100644
--- a/include/configs/spear1310-evb.h
+++ b/include/configs/spear1310-evb.h
@@ -81,6 +81,11 @@
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_FSMC_NAND_8BIT
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_DDR_MT41J256M8
+#define CONFIG_SPEAR_DDRFREQ533
+
/* Environment Variable configs */
#if defined(CONFIG_ENV_IS_IN_FLASH)
/* Environment is in serial NOR flash */
diff --git a/spl/Makefile b/spl/Makefile
index 78cb0a6..289758e 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -47,6 +47,7 @@ LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o
LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o
LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o
+LIBS-$(CONFIG_SPL_MISC_SUPPORT) += drivers/misc/c3.o
LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o
LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o
LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 7/9] spear6xx/spear3xx: Add support to boot via NAND device
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (4 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 6/9] spear320-hmi: Add support for hmi machine Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 8/9] spear/spl: Add support to boot from Parallel NOR device Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 9/9] spear300evb: Add SPL support Vipin Kumar
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Add support for nand boot to SPL meant for spear3xx/spear6xx based boards
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 2 +-
arch/arm/cpu/arm926ejs/spear/spl_boot.c | 44 +++++-
arch/arm/cpu/arm926ejs/spear/spl_nand.c | 121 ++++++++++++++++
arch/arm/include/asm/arch-spear/bootrom_table.h | 54 +++++++
arch/arm/include/asm/arch-spear/spl_nand.h | 181 ++++++++++++++++++++++++
include/configs/spear600-evb.h | 1 +
6 files changed, 400 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/spl_nand.c
create mode 100644 arch/arm/include/asm/arch-spear/bootrom_table.h
create mode 100644 arch/arm/include/asm/arch-spear/spl_nand.h
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 2e026ee..5ebdf65 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -38,7 +38,7 @@ COBJS-$(CONFIG_SOC_SPEAR320) += spear320.o
COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
ifdef CONFIG_SPL_BUILD
-COBJS-y += spl.o spl_boot.o
+COBJS-y += spl.o spl_boot.o spl_nand.o
COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o
endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
index 9742135..497aefc 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -30,6 +30,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
+#include <asm/arch/spl_nand.h>
uint32_t crc32(uint32_t, const unsigned char *, uint);
@@ -72,6 +73,35 @@ static int snor_image_load(u8 *load_addr, void (**image_p)(void))
return 0;
}
+static int nand_image_load(u32 blkstart, void (**image_p)(void))
+{
+ image_header_t header;
+ int ret = 0, blknum = blkstart;
+ size_t size;
+ ulong load_address;
+
+ do {
+ size = sizeof(image_header_t);
+ ret = nand_read_skip_bad(blknum, 0, &size, (u_char *)&header);
+
+ if ((ret >= 0) && image_check_header(&header)) {
+ size = image_get_data_size(&header);
+ load_address = image_get_load(&header);
+
+ ret = nand_read_skip_bad(blknum,
+ sizeof(image_header_t),
+ &size, (void *)load_address);
+ if (image_check_data(&header)) {
+ /* Jump to boot image */
+ *image_p = (void (*)(void))image_get_load(&header);
+ return 1;
+ }
+ }
+ } while (++blknum < blkstart + 4);
+
+ return 0;
+}
+
static void boot_image(void (*image)(void))
{
void (*funcp)(void) __noreturn = (void *)image;
@@ -124,8 +154,18 @@ u32 spl_boot(void)
if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
/* NAND booting */
- /* Not ported from XLoader to SPL yet */
- return 0;
+ /* NAND-FSMC initialization */
+ spl_nand_init();
+
+ /* NAND booting */
+ if (nand_image_load(CONFIG_SYS_NAND_BOOT_BLK, &image)) {
+ /* Platform related late initialasations */
+ board_lowlevel_late_init();
+
+ /* Jump to boot image */
+ boot_image(image);
+ return 1;
+ }
}
if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_nand.c b/arch/arm/cpu/arm926ejs/spear/spl_nand.c
new file mode 100644
index 0000000..e5d5288
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spl_nand.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom_table.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/spl_nand.h>
+
+static struct flashtype flashtype;
+static boot_flashdetectandinit_ptr_type boot_flashdetectandinit;
+static boot_flashread_ptr_type boot_flashread;
+static boot_nandsanitycheck_ptr_type boot_nandsanitycheck;
+static struct boot_nand_page *tmp_page_p;
+
+void spl_nand_init(void)
+{
+ struct bootrom_table *romtb_p =
+ (struct bootrom_table *)BOOTROM_TABLE_ADDRESS;
+
+ /* Global function pointers */
+ switch (get_socrev()) {
+ case SOC_SPEAR300:
+ boot_flashdetectandinit =
+ (boot_flashdetectandinit_ptr_type)0xffff1774;
+ boot_flashread = (boot_flashread_ptr_type)0xffff1050;
+ boot_nandsanitycheck =
+ (boot_nandsanitycheck_ptr_type)0xffff193C;
+ tmp_page_p = (struct boot_nand_page *)0x50030CCC;
+ break;
+ case SOC_SPEAR600_BA:
+ case SOC_SPEAR600_BB:
+ /* NAND Boot does not work for Revisions SPEAr600 BA and BB */
+ case SOC_SPEAR600_BC:
+ boot_flashdetectandinit =
+ (boot_flashdetectandinit_ptr_type)0xffff14ec;
+ boot_flashread = (boot_flashread_ptr_type)0xffff0dc4;
+ boot_nandsanitycheck =
+ (boot_nandsanitycheck_ptr_type)0xffff1628;
+ tmp_page_p = (struct boot_nand_page *)0xd2800844;
+ break;
+ case SOC_SPEAR310:
+ case SOC_SPEAR320:
+ case SOC_SPEAR600_BD:
+ boot_flashdetectandinit =
+ (romtb_p->table.table_1_0.boot_flashdetectandinit_ptr);
+ boot_flashread = (romtb_p->table.table_1_0.boot_flashread_ptr);
+ boot_nandsanitycheck =
+ (romtb_p->table.table_1_0.boot_nandsanitycheck_ptr);
+ tmp_page_p = (struct boot_nand_page *)0xd280084C;
+ break;
+ default:
+ break;
+ }
+
+ if (boot_flashdetectandinit)
+ (*boot_flashdetectandinit) (&flashtype, 1, BOTH_8_16,
+ tmp_page_p);
+}
+
+/**
+ * nand_read_skip_bad: Read image from NAND flash. Blocks that are marked bad
+ * are skipped and the next block is read instead as long as the image is short
+ * enough to fit even after skipping the bad blocks.
+ *
+ * @block: block number to start the read
+ * @offset: offset in the block number
+ * @length: buffer length, on return holds remaining bytes to read
+ * @buffer: buffer to write to
+ * @return 0 in case of success
+ */
+int nand_read_skip_bad(u32 block, size_t offset, size_t *length,
+ u_char *buffer)
+{
+ struct command_set *command = &(flashtype.comm_set);
+ u32 chip_off, readlen;
+
+ if (!boot_nandsanitycheck || !boot_flashread)
+ return -EINVAL;
+
+ while (*length) {
+ if (BOOT_OK == (*boot_nandsanitycheck) (&flashtype, block)) {
+ /* Block is OK */
+ chip_off = command->block_size * block + offset;
+ readlen = min(command->block_size - offset, *length);
+
+ if (BOOT_OK == (*boot_flashread) (&flashtype, chip_off,
+ buffer, readlen, tmp_page_p)) {
+ offset = 0;
+ *length -= readlen;
+ buffer += readlen;
+ } else
+ return -EINVAL;
+ }
+ /* Block is bad */
+ block++;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-spear/bootrom_table.h b/arch/arm/include/asm/arch-spear/bootrom_table.h
new file mode 100644
index 0000000..65bb369
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/bootrom_table.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_BOOTROM_TABLE_H
+#define ASM_ARCH_BOOTROM_TABLE_H
+
+/*
+ * BootROM Table Structures
+ */
+#define BOOTROM_TABLE_ADDRESS 0xFFFF7F00
+
+#define BOOTROM_TABLE_VERSION_1_0 1
+
+struct bootrom_table_1_0 {
+ const void *boot_flashdetectandinit_ptr;
+ const void *boot_flashread_ptr;
+ const void *boot_nandsanitycheck_ptr;
+ const void *boot_nandreadpage_ptr;
+};
+
+/*
+ * Generic bootrom table structure's union. Contains the table structure for
+ * all versions
+ */
+union bootrom_ver_table {
+ struct bootrom_table_1_0 table_1_0;
+};
+
+struct bootrom_table {
+ const unsigned int table_version;
+ union bootrom_ver_table table;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spl_nand.h b/arch/arm/include/asm/arch-spear/spl_nand.h
new file mode 100644
index 0000000..2773ea8
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spl_nand.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_SPEAR_SPL_NAND_H
+#define ASM_ARCH_SPEAR_SPL_NAND_H
+
+extern void spl_nand_init(void);
+extern int nand_read_skip_bad(u32 blk, size_t off, size_t *len, u_char *buff);
+
+/*
+ * The following definitions come from BootROM library.
+ * Please do not change the routine names as the refrences are picked from
+ * BootROM library all the versions of which are also committed along with
+ * SPL sources
+ */
+
+#define BOOT_OK 0
+
+enum {
+ BOTH_8_16 = 0,
+ EIGHT_BITS_ONLY = 1,
+ SIXTEEN_BITS_ONLY = 2
+};
+
+typedef enum {
+ NAND = 0,
+ NOR = 1,
+ ONE_NAND = 2
+} t_flash_device;
+
+typedef enum {
+ /* SMALL PAGES */
+ /* 64M */
+ NAND_64MS_1V_8 = 0x39,
+ /* 128M */
+ NAND_128MS_1V_8 = 0x33,
+ NAND_128MS_1V_16 = 0x43,
+ NAND_128MS_3V_8 = 0x73,
+ NAND_128MS_3V_16 = 0x53,
+ /* 256M */
+ NAND_256MS_1V_8 = 0x35,
+ NAND_256MS_1V_16 = 0x45,
+ NAND_256MS_3V_8 = 0x75,
+ NAND_256MS_3V_16 = 0x55,
+ /* 512M */
+ NAND_512MS_1V_8 = 0x36,
+ NAND_512MS_1V_16 = 0x46,
+ NAND_512MS_3V_8 = 0x76,
+ NAND_512MS_3V_16 = 0x56,
+ /* 1G */
+ NAND_1GS_1V_8 = 0x40,
+ NAND_1GS_1V_16 = 0x49,
+ NAND_1GS_3V_8 = 0x79,
+ NAND_1GS_3V_16 = 0x59,
+ NAND_1GS_3V_DDP_16 = 0x74,
+ NAND_1GS_1V_DDP_8 = 0x78,
+ NAND_1GS_1V_DDP_16 = 0x72,
+
+ /* LARGE PAGES */
+ /* 512M */
+ NAND_512ML_1V_8 = 0xA2,
+ NAND_512ML_1V_16 = 0xB2,
+ NAND_512ML_3V_8 = 0xF2,
+ NAND_512ML_3V_16 = 0xC2,
+ /* 1G */
+ NAND_1GL_1V_8 = 0xA1,
+ NAND_1GL_1V_16 = 0xB1,
+ NAND_1GL_3V_8 = 0xF1,
+ NAND_1GL_3V_16 = 0xC1,
+ /* 2G */
+ NAND_2GL_1V_8 = 0xAA,
+ NAND_2GL_3V_8 = 0xDA,
+ NAND_2GL_1V_16 = 0xBA,
+ NAND_2GL_3V_16 = 0xCA,
+ /* 4G */
+ NAND_4GL_1V_8 = 0xAC,
+ NAND_4GL_3V_8 = 0xDC,
+ NAND_4GL_1V_16 = 0xBC,
+ NAND_4GL_3V_16 = 0xCC,
+ /* 8G */
+ NAND_8GL_1V_8 = 0xA3,
+ NAND_8GL_3V_8 = 0xD3,
+ NAND_8GL_1V_16 = 0xB3,
+ NAND_8GL_3V_16 = 0xC3,
+ /* 8G */
+ NAND_16GL_1V_8 = 0xA5,
+ NAND_16GL_3V_8 = 0xD5,
+ NAND_16GL_1V_16 = 0xB5,
+ NAND_16GL_3V_16 = 0xC5,
+ /* NOR */
+ NOR_8 = -1,
+ NOR_16 = -2,
+ /* NAND */
+ ONE_NAND_16 = -4,
+ NO_VALID_ID = 0,
+ UNKNOWN_ID = -3
+} t_flash_command_id;
+
+typedef enum {
+ NOR_BANK_0 = 0,
+ NAND_BANK_0 = 1,
+ NAND_BANK_1 = 2,
+ NAND_BANK_2 = 3,
+ LAST_BANK
+} t_flash_FSMC_bank;
+
+struct command_set {
+ u32 pagexblock;
+ u32 page_size;
+ u32 block_size;
+ u32 spare_size;
+ u32 memory_size;
+ u32 ecc_size;
+ u32 data_width;
+ u32 pmem_command;
+ u32 pmem_address[2];
+ u32 patt_command;
+ u32 pmem_read;
+ u32 mem_command;
+ u32 att_command;
+ u32 mem_command_write;
+ u32 att_command_write;
+ u32 spare_command;
+ u8 /* t_flash_FSMC_bank */ memory_bank;
+ u8 padding[3];
+};
+
+/*
+ * There is a hack while defining this structure. The bootROM interface uses the
+ * enum types for a few elements of the structure which it optimizes using the
+ * compiler flag '-fshort-enums'. Since the bootrom is fixed it can be hacked
+ * here and not let the flag apply to all other parts of code */
+struct flashtype {
+ u8 /* t_flash_device */ device;
+ u8 padding;
+ s16 /* t_flash_command_id */ read_id;
+ struct command_set comm_set;
+};
+
+typedef enum {
+ PAGE_OK,
+ PAGE_KO
+} t_valid_flag;
+
+struct boot_nand_page {
+ u32 page_start_address;
+ u8 page[512];
+ t_valid_flag page_valid;
+ u8 padding[3];
+};
+
+typedef u32 (*boot_flashdetectandinit_ptr_type) (struct flashtype *,
+ u32, u32, struct boot_nand_page *);
+typedef u32 (*boot_flashread_ptr_type) (struct flashtype *, u32,
+ u8 *, u32, struct boot_nand_page *);
+typedef u32 (*boot_nandsanitycheck_ptr_type) (struct flashtype *,
+ u32);
+typedef u32 (*boot_nandreadpage_ptr_type) (u32, struct flashtype *,
+ struct boot_nand_page *);
+
+#endif
diff --git a/include/configs/spear600-evb.h b/include/configs/spear600-evb.h
index e7c5ee3..35761eb 100644
--- a/include/configs/spear600-evb.h
+++ b/include/configs/spear600-evb.h
@@ -85,6 +85,7 @@
#define CONFIG_DDR_MT47H32M16
#define CONFIG_SPL_TEXT_BASE 0xD2800B00
#define CONFIG_SYS_SNOR_BOOT_BASE 0xF8010000
+#define CONFIG_SYS_NAND_BOOT_BLK 4
#if defined(CONFIG_ENV_IS_IN_FLASH)
/* Environment is in serial NOR flash */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 07/11] spear: Cleanup SoC area
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (4 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 06/11] spear: Read ethaddr from I2C memory Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 08/11] spear/spl: Cleanup spear SPL Vipin Kumar
` (3 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
- Place emi init in soc area
- Move smi and emi controller initializations to arch_cpu_init
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 2 +
arch/arm/cpu/arm926ejs/spear/cpu.c | 37 +++++++++++++++-
arch/arm/cpu/arm926ejs/spear/emi.c | 80 +++++++++++++++++++++++++++++++++++
arch/arm/cpu/arm926ejs/spear/spl.c | 35 ---------------
board/st/spear/spear_common.c | 75 --------------------------------
5 files changed, 118 insertions(+), 111 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/emi.c
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index d06f03d..939f372 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -29,6 +29,8 @@ COBJS-y := cpu.o \
reset.o \
timer.o
+COBJS-$(CONFIG_ST_EMI) += emi.o
+
ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o spl_boot.o
COBJS-$(CONFIG_SPEAR600) += spear600.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 311f31b..f03b2bb 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -22,16 +22,41 @@
*/
#include <common.h>
+#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/misc.h>
+#if defined(CONFIG_ARCH_SPEAR6XX)
+static void mac_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ writel(readl(&misc_p->periph1_clken) & ~MISC_ETHENB,
+ &misc_p->periph1_clken);
+
+ writel(MISC_SYNTH23, &misc_p->gmac_synth_clk);
+ writel(0x0, &misc_p->gmac_ctr_reg);
+
+ writel(readl(&misc_p->periph1_clken) | MISC_ETHENB,
+ &misc_p->periph1_clken);
+
+ writel(readl(&misc_p->periph1_rst) | MISC_ETHENB,
+ &misc_p->periph1_rst);
+ writel(readl(&misc_p->periph1_rst) & ~MISC_ETHENB,
+ &misc_p->periph1_rst);
+}
+#endif
+
int arch_cpu_init(void)
{
struct misc_regs *const misc_p =
- (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 periph1_clken, periph_clk_cfg;
+#if defined(CONFIG_ARCH_SPEAR6XX)
+ mac_init();
+#endif
periph1_clken = readl(&misc_p->periph1_clken);
#if defined(CONFIG_ARCH_SPEAR3XX)
@@ -65,6 +90,16 @@ int arch_cpu_init(void)
#endif
writel(periph1_clken, &misc_p->periph1_clken);
+
+ /* Early driver initializations */
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+
+#ifdef CONFIG_ST_EMI
+ emi_init();
+#endif
+
return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/spear/emi.c b/arch/arm/cpu/arm926ejs/spear/emi.c
new file mode 100644
index 0000000..3a49410
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/emi.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emi.h>
+
+struct cust_emi_para {
+ unsigned int tap;
+ unsigned int tsdp;
+ unsigned int tdpw;
+ unsigned int tdpr;
+ unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+ .tap = 0x10,
+ .tsdp = 0x05,
+ .tdpw = 0x0a,
+ .tdpr = 0x0a,
+ .tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+ .tap = 0xf,
+ .tsdp = 0x0,
+ .tdpw = 0xff,
+ .tdpr = 0x111,
+ .tdcs = 0x02,
+};
+
+void emi_init(void)
+{
+ const struct cust_emi_para *p = &emi_timing_m28w640hc;
+ struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+ unsigned int cs;
+ unsigned int val, tmp;
+
+ val = readl(CONFIG_SPEAR_RASBASE);
+
+ if (val & EMI_ACKMSK)
+ tmp = 0x3f;
+ else
+ tmp = 0x0;
+
+ writel(tmp, &emi_regs_p->ack);
+
+ for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+ writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+ writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+ writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+ writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+ writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+ writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+ &emi_regs_p->bank_regs[cs].control);
+ }
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index c0e01ea..16ab82d 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -128,41 +128,6 @@ static void pll_init(void)
;
}
-static void mac_init(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
- writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
- &misc_p->periph1_clken);
-
- writel(SYNTH23, &misc_p->gmac_synth_clk);
-
- switch (get_socrev()) {
- case SOC_SPEAR600_AA:
- case SOC_SPEAR600_AB:
- case SOC_SPEAR600_BA:
- case SOC_SPEAR600_BB:
- case SOC_SPEAR600_BC:
- case SOC_SPEAR600_BD:
- writel(0x0, &misc_p->gmac_ctr_reg);
- break;
-
- case SOC_SPEAR300:
- case SOC_SPEAR310:
- case SOC_SPEAR320:
- writel(0x4, &misc_p->gmac_ctr_reg);
- break;
- }
-
- writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
- &misc_p->periph1_clken);
-
- writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
- &misc_p->periph1_rst);
- writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
- &misc_p->periph1_rst);
-}
-
static void sys_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
diff --git a/board/st/spear/spear_common.c b/board/st/spear/spear_common.c
index 71e9348..f274b6e 100644
--- a/board/st/spear/spear_common.c
+++ b/board/st/spear/spear_common.c
@@ -25,7 +25,6 @@
#include <command.h>
#include <i2c.h>
#include <net.h>
-#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
@@ -48,80 +47,6 @@ int dram_init(void)
return 0;
}
-int board_early_init_f()
-{
-#if defined(CONFIG_ST_SMI)
- smi_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_SPEAR_EMI
-struct cust_emi_para {
- unsigned int tap;
- unsigned int tsdp;
- unsigned int tdpw;
- unsigned int tdpr;
- unsigned int tdcs;
-};
-
-/* EMI timing setting of m28w640hc of linux kernel */
-const struct cust_emi_para emi_timing_m28w640hc = {
- .tap = 0x10,
- .tsdp = 0x05,
- .tdpw = 0x0a,
- .tdpr = 0x0a,
- .tdcs = 0x05,
-};
-
-/* EMI timing setting of bootrom */
-const struct cust_emi_para emi_timing_bootrom = {
- .tap = 0xf,
- .tsdp = 0x0,
- .tdpw = 0xff,
- .tdpr = 0x111,
- .tdcs = 0x02,
-};
-
-void spear_emi_init(void)
-{
- const struct cust_emi_para *p = &emi_timing_m28w640hc;
- struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
- unsigned int cs;
- unsigned int val, tmp;
-
- val = readl(CONFIG_SPEAR_RASBASE);
-
- if (val & EMI_ACKMSK)
- tmp = 0x3f;
- else
- tmp = 0x0;
-
- writel(tmp, &emi_regs_p->ack);
-
- for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
- writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
- writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
- writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
- writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
- writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
- writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
- &emi_regs_p->bank_regs[cs].control);
- }
-}
-#endif
-
-int spear_board_init(ulong mach_type)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-
-#ifdef CONFIG_SPEAR_EMI
- spear_emi_init();
-#endif
- return 0;
-}
-
#if defined(CONFIG_SPEAR_MACID_IN_I2CMEM) && defined(CONFIG_CMD_NET) && \
defined(CONFIG_CMD_I2C)
int i2c_read_mac(uchar *buffer)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 08/19] net/designware: Do not select MIIPORT for RGMII interface
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (5 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 07/19] sdhci: Add sdhci support for spear devices Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 10/19] usb/gadget/designware_otg: Add support for designware otg Vipin Kumar
` (9 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/net/designware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bf21a08..46f6601 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -113,7 +113,9 @@ static int mac_reset(struct eth_device *dev)
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST, &dma_p->busmode);
- writel(MII_PORTSELECT, &mac_p->conf);
+
+ if (priv->interface != PHY_INTERFACE_MODE_RGMII)
+ writel(MII_PORTSELECT, &mac_p->conf);
start = get_timer(0);
while (get_timer(start) < timeout) {
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 8/9] spear/spl: Add support to boot from Parallel NOR device
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (5 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 7/9] spear6xx/spear3xx: Add support to boot via NAND device Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 9/9] spear300evb: Add SPL support Vipin Kumar
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Parallel NOR boot is supported by all spear3xx devices. This patch adds the
support to the generic spear spl framework.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/spl_boot.c | 79 +++++++++++++++++++++++++++++-
arch/arm/include/asm/arch-spear/generic.h | 6 ---
arch/arm/include/asm/arch-spear/spl_pnor.h | 34 +++++++++++++
include/configs/spear600-evb.h | 1 +
4 files changed, 113 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-spear/spl_pnor.h
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
index 497aefc..7364ee0 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -31,6 +31,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
#include <asm/arch/spl_nand.h>
+#include <asm/arch/spl_pnor.h>
uint32_t crc32(uint32_t, const unsigned char *, uint);
@@ -102,6 +103,59 @@ static int nand_image_load(u32 blkstart, void (**image_p)(void))
return 0;
}
+static void pnorcopy(void *dest, const void *src, size_t len,
+ pnor_width_t width)
+{
+ const u32 *src_32 = src;
+ const u16 *src_16 = src;
+ const u8 *src_8 = src;
+ u32 *dest_32 = dest;
+ u16 *dest_16 = dest;
+ u8 *dest_8 = dest;
+ int i;
+
+ switch (width) {
+ case PNOR_WIDTH_32:
+ for (i = 0; i < len >> 2; i++)
+ *dest_32++ = *src_32++;
+ break;
+ case PNOR_WIDTH_16:
+ for (i = 0; i < len >> 1; i++)
+ *dest_16++ = *src_16++;
+ break;
+ case PNOR_WIDTH_8:
+ default:
+ for (i = 0; i < len; i++)
+ *dest_8++ = *src_8++;
+ break;
+ }
+}
+
+static int pnor_image_load(const void *load_addr, void (**image_p)(void),
+ pnor_width_t width)
+{
+ image_header_t header;
+ u32 numbytes;
+
+ pnorcopy((void *)&header, load_addr, sizeof(header), width);
+
+ if (image_check_header(&header)) {
+ numbytes = image_get_data_size(&header);
+
+ /* Copy the image to load address */
+ pnorcopy((void *)image_get_load(&header),
+ load_addr + sizeof(header), numbytes, width);
+
+ if (image_check_data(&header)) {
+ /* Jump to boot image */
+ *image_p = (void (*)(void))image_get_load(&header);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
static void boot_image(void (*image)(void))
{
void (*funcp)(void) __noreturn = (void *)image;
@@ -109,6 +163,13 @@ static void boot_image(void (*image)(void))
(*funcp)();
}
+static pnor_width_t __def_get_pnor_width(void)
+{
+ return PNOR_WIDTH_SEARCH;
+}
+pnor_width_t get_pnor_width(void)
+ __attribute__((weak, alias("__def_get_pnor_width")));
+
static void __def_board_lowlevel_late_init(void)
{
}
@@ -170,7 +231,23 @@ u32 spl_boot(void)
if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
/* PNOR booting */
- /* Not ported from XLoader to SPL yet */
+ /* PNOR initialization */
+ pnor_width_t width = get_pnor_width();
+
+ if (width == PNOR_WIDTH_SEARCH)
+ width = PNOR_WIDTH_8;
+
+ /* NAND booting */
+ if (pnor_image_load((const void *)CONFIG_SYS_PNOR_BOOT_BASE,
+ &image, width)) {
+ /* Platform related late initialasations */
+ board_lowlevel_late_init();
+
+ /* Jump to boot image */
+ boot_image(image);
+ return 1;
+ }
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-spear/generic.h b/arch/arm/include/asm/arch-spear/generic.h
index b7026e2..aa13b83 100644
--- a/arch/arm/include/asm/arch-spear/generic.h
+++ b/arch/arm/include/asm/arch-spear/generic.h
@@ -118,10 +118,4 @@ extern int get_socrev(void);
#define MAC_OFF 0x2
#define MAC_LEN 0x6
-#define PNOR_WIDTH_8 0
-#define PNOR_WIDTH_16 1
-#define PNOR_WIDTH_32 2
-#define PNOR_WIDTH_NUM 3
-#define PNOR_WIDTH_SEARCH 0xff
-
#endif
diff --git a/arch/arm/include/asm/arch-spear/spl_pnor.h b/arch/arm/include/asm/arch-spear/spl_pnor.h
new file mode 100644
index 0000000..f69efc2
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spl_pnor.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_SPEAR_SPL_PNOR_H
+#define ASM_ARCH_SPEAR_SPL_PNOR_H
+
+typedef enum {
+ PNOR_WIDTH_8,
+ PNOR_WIDTH_16,
+ PNOR_WIDTH_32,
+ PNOR_WIDTH_SEARCH
+} pnor_width_t;
+
+#endif
diff --git a/include/configs/spear600-evb.h b/include/configs/spear600-evb.h
index 35761eb..51a349e 100644
--- a/include/configs/spear600-evb.h
+++ b/include/configs/spear600-evb.h
@@ -85,6 +85,7 @@
#define CONFIG_DDR_MT47H32M16
#define CONFIG_SPL_TEXT_BASE 0xD2800B00
#define CONFIG_SYS_SNOR_BOOT_BASE 0xF8010000
+#define CONFIG_SYS_PNOR_BOOT_BASE 0x00000000
#define CONFIG_SYS_NAND_BOOT_BLK 4
#if defined(CONFIG_ENV_IS_IN_FLASH)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 08/11] spear/spl: Cleanup spear SPL
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (5 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 07/11] spear: Cleanup SoC area Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 09/11] spear: Add POST memory support Vipin Kumar
` (2 subsequent siblings)
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
This patch cleans up the spear SPL support. The modifications include
- Move mpmc register programing values to board dir
MPMC register programming values are dependent on DDR timings which in turn
depend a lot on the placement of DDR chip on the board. It makes more sense
to keep these register init values in board
- Add SPEAR to the CONFIG_DDR namespace
Add SPEAR to the CONFIG_DDR namespace to make it exclusive to SPEAr platfroms
only
- Add hardware configurations for spear600 spl support
- Avoid console operations during spl
The spl runs in the environment provided by boot code. The Boot code may or
may not initialize UART (padmux, clock etc). This mandates the SPL to initialize
UART to dump information
SPEAr SPL as a policy initializes only the system and ddr
- Do not copy the header arbitrarily
The current logic is copying the header at 64 bytes before the load address.
This can lead to unpredictable results as that memory is reserved to be
bss/rw area
Modify the logic to use a local structure for image header
- Rename spear600.c to spl-spear600.c
- Use the smi_init routine from smi driver
- Perform Data CRC check on relocated image
image_check_dcrc accepts a header pointer as an argument and performs a data
crc check based on the assumption that the image data is placed immediately
after the header. The SPEAr SPL support performs the data verification after
relocation to RAM has taken place. There are at least following two benefits
of doing so
* It is faster in Normal booting cases It also leads to a basic DDR test
* because the code gets copied to the recently
initialized DDR and it works like a read-write test for RAM before the
control is actually transfered to u-boot
- Implement independent routines for get_socrev()
- Rename register bitmask definitions
- Simplify lds file
- Use ENTRY/ENDPROC macros and clear bss
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 6 +-
arch/arm/cpu/arm926ejs/spear/spear600.c | 232 ---------------------
arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c | 35 ++++
arch/arm/cpu/arm926ejs/spear/spl-spear600.c | 98 +++++++++
arch/arm/cpu/arm926ejs/spear/spl.c | 140 ++++---------
arch/arm/cpu/arm926ejs/spear/spl_boot.c | 84 +++-----
arch/arm/cpu/arm926ejs/spear/start.S | 58 +++---
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 65 ++----
arch/arm/include/asm/arch-spear/generic.h | 88 ++++++--
arch/arm/include/asm/arch-spear/misc.h | 191 +++++------------
arch/arm/include/asm/arch-spear/spear600.h | 13 ++
arch/arm/include/asm/arch-spear/syscntl.h | 21 +-
board/st/spear/config.mk | 6 +
board/st/spear/ddr/Makefile | 57 +++++
.../ddr/spear600_mt47h128m8_3_266_cl5_async.c | 3 +-
.../spear/ddr/spear600_mt47h32m16_333_cl5_psync.c | 8 +-
.../ddr/spear600_mt47h32m16_37e_166_cl4_sync.c | 3 +-
.../ddr/spear600_mt47h64m16_3_333_cl5_psync.c | 8 +-
board/st/spear/spear600evb.c | 91 ++++++++
include/configs/spear600.h | 11 +
spl/Makefile | 4 +
21 files changed, 578 insertions(+), 644 deletions(-)
delete mode 100644 arch/arm/cpu/arm926ejs/spear/spear600.c
create mode 100644 arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
create mode 100644 arch/arm/cpu/arm926ejs/spear/spl-spear600.c
create mode 100644 board/st/spear/ddr/Makefile
rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c => board/st/spear/ddr/spear600_mt47h128m8_3_266_cl5_async.c (95%)
rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c => board/st/spear/ddr/spear600_mt47h32m16_333_cl5_psync.c (91%)
rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c => board/st/spear/ddr/spear600_mt47h32m16_37e_166_cl4_sync.c (95%)
rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c => board/st/spear/ddr/spear600_mt47h64m16_3_333_cl5_psync.c (91%)
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 939f372..3fe7e26 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -33,11 +33,7 @@ COBJS-$(CONFIG_ST_EMI) += emi.o
ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o spl_boot.o
-COBJS-$(CONFIG_SPEAR600) += spear600.o
-COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
-COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
-COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
-COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o
endif
SRCS := $(START:.o=.S) $(COBJS-y:.o=.c)
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
deleted file mode 100644
index bd8cb7a..0000000
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * (C) Copyright 2000-2009
- * Viresh Kumar, ST Microelectronics, viresh.kumar at st.com
- * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/misc.h>
-#include <asm/arch/generic.h>
-
-#define FALSE 0
-#define TRUE (!FALSE)
-
-static void sel_1v8(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 ddr1v8, ddr2v5;
-
- ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
- ddr2v5 &= 0x8080ffc0;
- ddr2v5 |= 0x78000003;
- writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
- ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
- ddr1v8 &= 0x8080ffc0;
- ddr1v8 |= 0x78000010;
- writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
- while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
- ;
-}
-
-static void sel_2v5(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 ddr1v8, ddr2v5;
-
- ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
- ddr1v8 &= 0x8080ffc0;
- ddr1v8 |= 0x78000003;
- writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
- ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
- ddr2v5 &= 0x8080ffc0;
- ddr2v5 |= 0x78000010;
- writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
- while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
- ;
-}
-
-/*
- * plat_ddr_init:
- */
-void plat_ddr_init(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 ddrpad;
- u32 core3v3, ddr1v8, ddr2v5;
-
- /* DDR pad register configurations */
- ddrpad = readl(&misc_p->ddr_pad);
- ddrpad &= ~DDR_PAD_CNF_MSK;
-
-#if (CONFIG_DDR_HCLK)
- ddrpad |= 0xEAAB;
-#elif (CONFIG_DDR_2HCLK)
- ddrpad |= 0xEAAD;
-#elif (CONFIG_DDR_PLL2)
- ddrpad |= 0xEAAD;
-#endif
- writel(ddrpad, &misc_p->ddr_pad);
-
- /* Compensation register configurations */
- core3v3 = readl(&misc_p->core_3v3_compensation);
- core3v3 &= 0x8080ffe0;
- core3v3 |= 0x78000002;
- writel(core3v3, &misc_p->core_3v3_compensation);
-
- ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
- ddr1v8 &= 0x8080ffc0;
- ddr1v8 |= 0x78000004;
- writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
- ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
- ddr2v5 &= 0x8080ffc0;
- ddr2v5 |= 0x78000004;
- writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
- if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
- /* Software memory configuration */
- if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
- sel_1v8();
- else
- sel_2v5();
- } else {
- /* Hardware memory configuration */
- if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
- sel_1v8();
- else
- sel_2v5();
- }
-}
-
-/*
- * soc_init:
- */
-void soc_init(void)
-{
- /* Nothing to be done for SPEAr600 */
-}
-
-/*
- * xxx_boot_selected:
- *
- * return TRUE if the particular booting option is selected
- * return FALSE otherwise
- */
-static u32 read_bootstrap(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
- return readl(&misc_p->auto_cfg_reg) & MISC_BOOTSTRAPMASK;
-}
-
-int snor_boot_selected(void)
-{
- u32 bootstrap = read_bootstrap();
-
- if (SNOR_BOOT_SUPPORTED) {
- /* Check whether SNOR boot is selected */
- if ((bootstrap & MISC_ONLYSNORBOOT) == MISC_ONLYSNORBOOT)
- return TRUE;
-
- if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
- return TRUE;
-
- if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
- return TRUE;
- }
-
- return FALSE;
-}
-
-int nand_boot_selected(void)
-{
- u32 bootstrap = read_bootstrap();
-
- if (NAND_BOOT_SUPPORTED) {
- /* Check whether NAND boot is selected */
- if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
- return TRUE;
-
- if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
- return TRUE;
- }
-
- return FALSE;
-}
-
-int pnor_boot_selected(void)
-{
- /* Parallel NOR boot is not selected in any SPEAr600 revision */
- return FALSE;
-}
-
-int usb_boot_selected(void)
-{
- u32 bootstrap = read_bootstrap();
-
- if (USB_BOOT_SUPPORTED) {
- /* Check whether USB boot is selected */
- if (!(bootstrap & MISC_USBBOOT))
- return TRUE;
- }
-
- return FALSE;
-}
-
-int tftp_boot_selected(void)
-{
- /* TFTP boot is not selected in any SPEAr600 revision */
- return FALSE;
-}
-
-int uart_boot_selected(void)
-{
- /* UART boot is not selected in any SPEAr600 revision */
- return FALSE;
-}
-
-int spi_boot_selected(void)
-{
- /* SPI boot is not selected in any SPEAr600 revision */
- return FALSE;
-}
-
-int i2c_boot_selected(void)
-{
- /* I2C boot is not selected in any SPEAr600 revision */
- return FALSE;
-}
-
-int mmc_boot_selected(void)
-{
- return FALSE;
-}
-
-void plat_late_init(void)
-{
- spear_late_init();
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
new file mode 100644
index 0000000..7e2bc98
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int get_socrev(void)
+{
+#if defined(CONFIG_SOC_SPEAR300)
+ return SOC_SPEAR300;
+#elif defined(CONFIG_SOC_SPEAR310)
+ return SOC_SPEAR310;
+#elif defined(CONFIG_SOC_SPEAR320)
+ return SOC_SPEAR320;
+#endif
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl-spear600.c b/arch/arm/cpu/arm926ejs/spear/spl-spear600.c
new file mode 100644
index 0000000..5813656
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spl-spear600.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar at st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/generic.h>
+
+#define FALSE 0
+#define TRUE (!FALSE)
+
+int get_socrev(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 soc_id = readl(&misc_p->soc_core_id);
+ u32 pri_socid = (soc_id >> MISC_PRISOCID_SHFT) & 0xFF;
+ u32 sec_socid = (soc_id >> MISC_SECSOCID_SHFT) & 0xFF;
+
+ if ((pri_socid == 'B') && (sec_socid == 'B'))
+ return SOC_SPEAR600_BB;
+ else if ((pri_socid == 'B') && (sec_socid == 'C'))
+ return SOC_SPEAR600_BC;
+ else if ((pri_socid == 'B') && (sec_socid == 'D'))
+ return SOC_SPEAR600_BD;
+ else if (soc_id == 0)
+ return SOC_SPEAR600_BA;
+ else
+ return SOC_SPEAR_NA;
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+ /* Nothing to be done for SPEAr600 */
+}
+
+u32 getboottype(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 bootstrap = readl(&misc_p->auto_cfg_reg) & MISC_BOOTSTRAPMASK;
+ u32 bootmask = 0;
+
+ if (SNOR_BOOT_SUPPORTED) {
+ /* Check whether SNOR boot is selected */
+ if ((bootstrap & MISC_ONLYSNORBOOT) == MISC_ONLYSNORBOOT)
+ bootmask |= BOOT_TYPE_SMI;
+
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
+ bootmask |= BOOT_TYPE_SMI;
+
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
+ bootmask |= BOOT_TYPE_SMI;
+ }
+
+ if (NAND_BOOT_SUPPORTED) {
+ /* Check whether NAND boot is selected */
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND8BOOT)
+ bootmask |= BOOT_TYPE_NAND;
+
+ if ((bootstrap & MISC_NORNANDBOOT) == MISC_NORNAND16BOOT)
+ bootmask |= BOOT_TYPE_NAND;
+ }
+
+ if (USBD_BOOT_SUPPORTED) {
+ /* Check whether USB boot is selected */
+ if (!(bootstrap & MISC_USBBOOT))
+ bootmask |= BOOT_TYPE_USBD;
+ }
+
+ if (!bootmask)
+ bootmask |= BOOT_TYPE_UNSUPPORTED;
+
+ return bootmask;
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index 16ab82d..4203150 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -33,7 +33,6 @@
inline void hang(void)
{
- serial_puts("### ERROR ### Please RESET the board ###\n");
for (;;)
;
}
@@ -44,27 +43,27 @@ static void ddr_clock_init(void)
u32 clkenb, ddrpll;
clkenb = readl(&misc_p->periph1_clken);
- clkenb &= ~PERIPH_MPMCMSK;
- clkenb |= PERIPH_MPMC_WE;
+ clkenb &= ~MISC_MPMCMSK;
+ clkenb |= MISC_MPMCWE;
/* Intentionally done twice */
writel(clkenb, &misc_p->periph1_clken);
writel(clkenb, &misc_p->periph1_clken);
ddrpll = readl(&misc_p->pll_ctr_reg);
- ddrpll &= ~MEM_CLK_SEL_MSK;
-#if (CONFIG_DDR_HCLK)
- ddrpll |= MEM_CLK_HCLK;
-#elif (CONFIG_DDR_2HCLK)
- ddrpll |= MEM_CLK_2HCLK;
-#elif (CONFIG_DDR_PLL2)
- ddrpll |= MEM_CLK_PLL2;
+ ddrpll &= ~MISC_DDRCLK_MSK;
+#if defined(CONFIG_SPEAR_DDR_HCLK)
+ ddrpll |= MISC_DDRCLK_HCLK;
+#elif defined(CONFIG_SPEAR_DDR_2HCLK)
+ ddrpll |= MISC_DDRCLK_2HCLK;
+#elif defined(CONFIG_SPEAR_DDR_PLL2)
+ ddrpll |= MISC_DDRCLK_PLL2;
#else
-#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#error "please define one of CONFIG_SPEAR_DDR_(HCLK|2HCLK|PLL2)"
#endif
writel(ddrpll, &misc_p->pll_ctr_reg);
- writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+ writel(readl(&misc_p->periph1_clken) | MISC_MPMCENB,
&misc_p->periph1_clken);
}
@@ -89,16 +88,13 @@ static void mpmc_init_values(void)
;
}
-static void mpmc_init(void)
+static void ddr_init(void)
{
/* Clock related settings for DDR */
ddr_clock_init();
- /*
- * DDR pad register bits are different for different SoCs
- * Compensation values are also handled separately
- */
- plat_ddr_init();
+ /* Borad related low level initializations */
+ board_ddr_init();
/* Initialize mpmc register values */
mpmc_init_values();
@@ -109,13 +105,13 @@ static void pll_init(void)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/* Initialize PLLs */
- writel(FREQ_332, &misc_p->pll1_frq);
+ writel(MISC_FREQ_332, &misc_p->pll1_frq);
writel(0x1C0A, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
writel(0x1C06, &misc_p->pll1_cntl);
writel(0x1C0E, &misc_p->pll1_cntl);
- writel(FREQ_332, &misc_p->pll2_frq);
+ writel(MISC_FREQ_332, &misc_p->pll2_frq);
writel(0x1C0A, &misc_p->pll2_cntl);
writel(0x1C0E, &misc_p->pll2_cntl);
writel(0x1C06, &misc_p->pll2_cntl);
@@ -135,113 +131,51 @@ static void sys_init(void)
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
/* Set system state to SLOW */
- writel(SLOW, &syscntl_p->scctrl);
- writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+ writel(SYSCNTL_REQ_SLOW, &syscntl_p->scctrl);
+ writel(SYSCNTL_PLL_TIM << 3, &syscntl_p->scpllctrl);
/* Initialize PLLs */
pll_init();
- /*
- * Ethernet configuration
- * To be done only if the tftp boot is not selected already
- * Boot code ensures the correct configuration in tftp booting
- */
- if (!tftp_boot_selected())
- mac_init();
-
- writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+ writel(MISC_RTC_DISABLE | MISC_PLLTIMEEN, &misc_p->periph_clk_cfg);
writel(0x555, &misc_p->amba_clk_cfg);
- writel(NORMAL, &syscntl_p->scctrl);
+ writel(SYSCNTL_REQ_NORMAL, &syscntl_p->scctrl);
/* Wait for system to switch to normal mode */
- while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
- != NORMAL)
+ while ((readl(&syscntl_p->scctrl) & SYSCNTL_STATE_MASK) !=
+ SYSCNTL_STATE_NORMAL)
;
}
-/*
- * get_socrev
- *
- * Get SoC Revision.
- * @return SOC_SPEARXXX
- */
-int get_socrev(void)
+static void spear_icm_init(void)
{
-#if defined(CONFIG_SOC_SPEAR600)
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 soc_id = readl(&misc_p->soc_core_id);
- u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
- u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
-
- if ((pri_socid == 'B') && (sec_socid == 'B'))
- return SOC_SPEAR600_BB;
- else if ((pri_socid == 'B') && (sec_socid == 'C'))
- return SOC_SPEAR600_BC;
- else if ((pri_socid == 'B') && (sec_socid == 'D'))
- return SOC_SPEAR600_BD;
- else if (soc_id == 0)
- return SOC_SPEAR600_BA;
- else
- return SOC_SPEAR_NA;
-#elif defined(CONFIG_SOC_SPEAR300)
- return SOC_SPEAR300;
-#elif defined(CONFIG_SOC_SPEAR310)
- return SOC_SPEAR310;
-#elif defined(CONFIG_SOC_SPEAR320)
- return SOC_SPEAR320;
-#endif
+
+ writel(0x80000007, &misc_p->arb_icm_ml1);
+ writel(0x80000007, &misc_p->arb_icm_ml2);
+ writel(0x80000007, &misc_p->arb_icm_ml3);
+ writel(0x80000007, &misc_p->arb_icm_ml4);
+ writel(0x80000007, &misc_p->arb_icm_ml5);
+ writel(0x80000007, &misc_p->arb_icm_ml6);
+ writel(0x80000007, &misc_p->arb_icm_ml7);
+ writel(0x80000007, &misc_p->arb_icm_ml8);
+ writel(0x80000007, &misc_p->arb_icm_ml9);
}
void lowlevel_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- const char *u_boot_rev = U_BOOT_VERSION;
/* Initialize PLLs */
sys_init();
- /* Initialize UART */
- serial_init();
-
- /* Print U-Boot SPL version string */
- serial_puts("\nU-Boot SPL ");
- /* Avoid a second "U-Boot" coming from this string */
- u_boot_rev = &u_boot_rev[7];
- serial_puts(u_boot_rev);
- serial_puts(" (");
- serial_puts(U_BOOT_DATE);
- serial_puts(" - ");
- serial_puts(U_BOOT_TIME);
- serial_puts(")\n");
-
-#if defined(CONFIG_OS_BOOT)
- writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
- &misc_p->periph1_clken);
-#endif
-
/* Enable IPs (release reset) */
- writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+ writel(MISC_PERIPH_RST_ALL, &misc_p->periph1_rst);
/* Initialize MPMC */
- serial_puts("Configure DDR\n");
- mpmc_init();
-
- /* SoC specific initialization */
- soc_init();
-}
-
-void spear_late_init(void)
-{
- struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ ddr_init();
- writel(0x80000007, &misc_p->arb_icm_ml1);
- writel(0x80000007, &misc_p->arb_icm_ml2);
- writel(0x80000007, &misc_p->arb_icm_ml3);
- writel(0x80000007, &misc_p->arb_icm_ml4);
- writel(0x80000007, &misc_p->arb_icm_ml5);
- writel(0x80000007, &misc_p->arb_icm_ml6);
- writel(0x80000007, &misc_p->arb_icm_ml7);
- writel(0x80000007, &misc_p->arb_icm_ml8);
- writel(0x80000007, &misc_p->arb_icm_ml9);
+ /* Initialize Interconnect Matrix */
+ spear_icm_init();
}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
index c67774d..9742135 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -31,63 +31,40 @@
#include <asm/arch/hardware.h>
#include <asm/arch/generic.h>
-static const char kernel_name[] = "Linux";
-static const char loader_name[] = "U-Boot";
+uint32_t crc32(uint32_t, const unsigned char *, uint);
-int image_check_header(image_header_t *hdr, const char *name)
+int image_check_header(image_header_t *hdr)
{
- if (image_check_magic(hdr) &&
- (!strncmp(image_get_name(hdr), name, strlen(name))) &&
- image_check_hcrc(hdr)) {
+ if (image_check_magic(hdr) && image_check_hcrc(hdr))
return 1;
- }
+
return 0;
}
int image_check_data(image_header_t *hdr)
{
- if (image_check_dcrc(hdr))
- return 1;
+ ulong data = image_get_load(hdr);
+ ulong len = image_get_data_size(hdr);
+ ulong dcrc = crc32(0, (unsigned char *)data, len);
- return 0;
+ return (dcrc == image_get_dcrc(hdr));
}
-/*
- * SNOR (Serial NOR flash) related functions
- */
-void snor_init(void)
+static int snor_image_load(u8 *load_addr, void (**image_p)(void))
{
- struct smi_regs *const smicntl =
- (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+ image_header_t header;
- /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
- writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
- &smicntl->smi_cr1);
-}
+ memcpy(&header, load_addr, sizeof(image_header_t));
-static int snor_image_load(u8 *load_addr, void (**image_p)(void),
- const char *image_name)
-{
- image_header_t *header;
+ if (image_check_header(&header)) {
+ /* Copy the image to load address */
+ memcpy((void *)image_get_load(&header),
+ load_addr + sizeof(image_header_t),
+ image_get_data_size(&header));
- /*
- * Since calculating the crc in the SNOR flash does not
- * work, we copy the image to the destination address
- * minus the header size. And point the header to this
- * new destination. This will not work for address 0
- * of course.
- */
- header = (image_header_t *)load_addr;
- memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
- (const ulong *)load_addr,
- image_get_data_size(header) + sizeof(image_header_t));
- header = (image_header_t *)(image_get_load(header) -
- sizeof(image_header_t));
-
- if (image_check_header(header, image_name)) {
- if (image_check_data(header)) {
+ if (image_check_data(&header)) {
/* Jump to boot image */
- *image_p = (void *)image_get_load(header);
+ *image_p = (void (*)(void))image_get_load(&header);
return 1;
}
}
@@ -102,6 +79,12 @@ static void boot_image(void (*image)(void))
(*funcp)();
}
+static void __def_board_lowlevel_late_init(void)
+{
+}
+void board_lowlevel_late_init(void)
+ __attribute__((weak, alias("__def_board_lowlevel_late_init")));
+
/*
* spl_boot:
*
@@ -114,7 +97,7 @@ u32 spl_boot(void)
void (*image)(void);
#ifdef CONFIG_SPEAR_USBTTY
- plat_late_init();
+ board_lowlevel_late_init();
return 1;
#endif
@@ -126,17 +109,14 @@ u32 spl_boot(void)
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
/* SNOR-SMI initialization */
- snor_init();
+ smi_init();
- serial_puts("Booting via SNOR\n");
/* Serial NOR booting */
- if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
- &image, loader_name)) {
+ if (snor_image_load((u8 *)CONFIG_SYS_SNOR_BOOT_BASE, &image)) {
/* Platform related late initialasations */
- plat_late_init();
+ board_lowlevel_late_init();
/* Jump to boot image */
- serial_puts("Jumping to U-Boot\n");
boot_image(image);
return 1;
}
@@ -178,18 +158,18 @@ u32 spl_boot(void)
* the following booting scenarios
*/
- if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
- plat_late_init();
+ if (USBD_BOOT_SUPPORTED && usbd_boot_selected()) {
+ board_lowlevel_late_init();
return 1;
}
if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
- plat_late_init();
+ board_lowlevel_late_init();
return 1;
}
if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
- plat_late_init();
+ board_lowlevel_late_init();
return 1;
}
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
index a103c0f..26368b3 100644
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -31,30 +31,12 @@
*/
+#include <asm-offsets.h>
#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
-.globl _start
-_start:
- b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction:
-_software_interrupt:
-_prefetch_abort:
-_data_abort:
-_not_used:
-_irq:
-_fiq:
- .word infinite_loop
-
-infinite_loop:
- b infinite_loop
+.syntax unified
/*
*************************************************************************
@@ -69,17 +51,28 @@ infinite_loop:
*************************************************************************
*/
-/*
- * the actual reset code
- */
-
-reset:
+.globl _start
+_start:
/*
* Xloader has to return back to BootROM in a few cases.
* eg. Ethernet boot, UART boot, USB boot
* Saving registers for returning back
*/
- stmdb sp!, {r0-r12,r14}
+ push {r0-r12, r14}
+
+ /* Relocate data if needed and Clear BSS */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:
+ cmp r0, r1 /* clear loop... */
+ bhs clbss_e /* if reached end of bss, exit */
+ str r2, [r0]
+ add r0, r0, #4
+ b clbss_l
+clbss_e:
+
bl cpu_init_crit
/*
* Clearing bss area is not done in Xloader.
@@ -87,7 +80,7 @@ reset:
* bss is assumed to be uninitialized.
*/
bl spl_boot
- ldmia sp!, {r0-r12,pc}
+ pop {r0-r12, pc}
/*
*************************************************************************
@@ -99,7 +92,7 @@ reset:
*
*************************************************************************
*/
-cpu_init_crit:
+ENTRY(cpu_init_crit)
/*
* flush v4 I/D caches
*/
@@ -117,6 +110,7 @@ cpu_init_crit:
/*
* Go setup Memory and board specific bits prior to relocation.
*/
- stmdb sp!, {lr}
+ push {lr}
bl lowlevel_init /* go setup pll,mux,memory */
- ldmia sp!, {pc}
+ pop {pc}
+ENDPROC(cpu_init_crit)
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index f3bd5e7..43af464 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, <vipin.kumar@st.com>
+ *
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
@@ -30,59 +33,21 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
-SECTIONS
+
+MEMORY
{
- . = 0x00000000;
+ xloader : ORIGIN = 0xD2800B00, LENGTH = 0x1500
+}
- . = ALIGN(4);
- .text :
+SECTIONS
+{
+ .text :
{
arch/arm/cpu/arm926ejs/spear/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- .bss : {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- _end = .;
+ *(.text); . = ALIGN(4);
+ } > xloader
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
+ .rodata : { *(.rodata*); . = ALIGN(4); } > xloader
+ .data : { *(.data*); . = ALIGN(4); } > xloader
+ .bss : { __bss_start = .; *(.bss*); . = ALIGN(4); __bss_end = .;} > xloader
}
diff --git a/arch/arm/include/asm/arch-spear/generic.h b/arch/arm/include/asm/arch-spear/generic.h
index 062571c..68a775e 100644
--- a/arch/arm/include/asm/arch-spear/generic.h
+++ b/arch/arm/include/asm/arch-spear/generic.h
@@ -27,21 +27,85 @@
/* Routines exported from baord */
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
+extern void board_ddr_init(void);
+extern void board_lowlevel_late_init(void);
-void spear_late_init(void);
-void plat_late_init(void);
+extern u32 mpmc_conf_vals[];
-int snor_boot_selected(void);
-int nand_boot_selected(void);
-int pnor_boot_selected(void);
-int usb_boot_selected(void);
-int uart_boot_selected(void);
-int tftp_boot_selected(void);
-int i2c_boot_selected(void);
-int spi_boot_selected(void);
-int mmc_boot_selected(void);
+/*
+ * All SoCs should support a generic routine getboottype() which returns a
+ * bitmask with one or more of the following bits set. This is a generic routine
+ * which can be used on any SoC
+ */
+#define BOOT_TYPE_BYPASS (1 << 1)
+#define BOOT_TYPE_SMI (1 << 2)
+#define BOOT_TYPE_NAND (1 << 3)
+#define BOOT_TYPE_RESERVED (1 << 4)
+#define BOOT_TYPE_I2C (1 << 5)
+#define BOOT_TYPE_SPI (1 << 6)
+#define BOOT_TYPE_USBD (1 << 7)
+#define BOOT_TYPE_TFTP (1 << 8)
+#define BOOT_TYPE_PCIE (1 << 9)
+#define BOOT_TYPE_UART (1 << 10)
+#define BOOT_TYPE_MMC (1 << 11)
+#define BOOT_TYPE_PNOR8 (1 << 12)
+#define BOOT_TYPE_PNOR16 (1 << 13)
+#define BOOT_TYPE_PNOR32 (1 << 14)
+#define BOOT_TYPE_UNSUPPORTED (1 << 31)
-extern u32 mpmc_conf_vals[];
+extern u32 getboottype(void);
+
+/* xxx_boot_selected */
+#define boot_bypass_selected() \
+ (getboottype() & BOOT_TYPE_BYPASS)
+#define usbd_boot_selected() \
+ (getboottype() & BOOT_TYPE_USBD)
+#define snor_boot_selected() \
+ (getboottype() & BOOT_TYPE_SMI)
+#define nand_boot_selected() \
+ (getboottype() & BOOT_TYPE_NAND)
+#define pnor8_boot_selected() \
+ (getboottype() & BOOT_TYPE_PNOR8)
+#define pnor16_boot_selected() \
+ (getboottype() & BOOT_TYPE_PNOR16)
+#define pnor32_boot_selected() \
+ (getboottype() & BOOT_TYPE_PNOR32)
+#define pnor_boot_selected() \
+ (pnor8_boot_selected() || \
+ pnor16_boot_selected() || \
+ pnor32_boot_selected())
+#define tftp_boot_selected() \
+ (getboottype() & BOOT_TYPE_TFTP)
+#define uart_boot_selected() \
+ (getboottype() & BOOT_TYPE_UART)
+#define spi_boot_selected() \
+ (getboottype() & BOOT_TYPE_SPI)
+#define i2c_boot_selected() \
+ (getboottype() & BOOT_TYPE_I2C)
+#define pcie_boot_selected() \
+ (getboottype() & BOOT_TYPE_PCIE)
+#define mmc_boot_selected() \
+ (getboottype() & BOOT_TYPE_MMC)
+
+/* Revision definitions */
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ */
+#define SOC_SPEAR_NA 0
+#define SOC_SPEAR600_AA 101
+#define SOC_SPEAR600_AB 102
+#define SOC_SPEAR600_BA 103
+#define SOC_SPEAR600_BB 104
+#define SOC_SPEAR600_BC 105
+#define SOC_SPEAR600_BD 106
+
+#define SOC_SPEAR300 201
+#define SOC_SPEAR310 202
+#define SOC_SPEAR320 203
+
+extern int get_socrev(void);
/* HW mac id in i2c memory definitions */
#define MAGIC_OFF 0x0
diff --git a/arch/arm/include/asm/arch-spear/misc.h b/arch/arm/include/asm/arch-spear/misc.h
index 2696203..bb97650 100644
--- a/arch/arm/include/asm/arch-spear/misc.h
+++ b/arch/arm/include/asm/arch-spear/misc.h
@@ -101,38 +101,7 @@ struct misc_regs {
u32 ras_gpp2_out; /* 0x800C */
};
-/* SYNTH_CLK value*/
-#define SYNTH23 0x00020003
-
-/* PLLx_FRQ value */
-#if defined(CONFIG_ARCH_SPEAR3XX)
-#define FREQ_332 0xA600010C
-#define FREQ_266 0x8500010C
-#elif defined(CONFIG_ARCH_SPEAR6XX)
-#define FREQ_332 0xA600010F
-#define FREQ_266 0x8500010F
-#endif
-
-/* PLL_CTR_REG */
-#define MEM_CLK_SEL_MSK 0x70000000
-#define MEM_CLK_HCLK 0x00000000
-#define MEM_CLK_2HCLK 0x10000000
-#define MEM_CLK_PLL2 0x30000000
-
-#define EXPI_CLK_CFG_LOW_COMPR 0x2000
-#define EXPI_CLK_CFG_CLK_EN 0x0400
-#define EXPI_CLK_CFG_RST 0x0200
-#define EXPI_CLK_SYNT_EN 0x0010
-#define EXPI_CLK_CFG_SEL_PLL2 0x0004
-#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
-
-#define PLL2_CNTL_6UA 0x1c00
-#define PLL2_CNTL_SAMPLE 0x0008
-#define PLL2_CNTL_ENABLE 0x0004
-#define PLL2_CNTL_RESETN 0x0002
-#define PLL2_CNTL_LOCK 0x0001
-
-/* AUTO_CFG_REG value */
+/* auto_cfg_reg value */
#define MISC_SOCCFGMSK 0x0000003F
#define MISC_SOCCFG30 0x0000000C
#define MISC_SOCCFG31 0x0000000D
@@ -144,26 +113,34 @@ struct misc_regs {
#define MISC_NORNAND16BOOT 0x00090000
#define MISC_USBBOOT 0x00080000
-/* PERIPH_CLK_CFG value */
+/* pllX_frq value */
+#if defined(CONFIG_ARCH_SPEAR3XX)
+#define MISC_FREQ_332 0xA600010C
+#define MISC_FREQ_266 0x8500010C
+#elif defined(CONFIG_ARCH_SPEAR6XX)
+#define MISC_FREQ_332 0xA600010F
+#define MISC_FREQ_266 0x8500010F
+#endif
+
+/* pll_ctr_reg */
+#define MISC_DDRCLK_MSK 0x70000000
+#define MISC_DDRCLK_HCLK 0x00000000
+#define MISC_DDRCLK_2HCLK 0x10000000
+#define MISC_DDRCLK_PLL2 0x30000000
+
+/* periph_clk_cfg */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
+#define MISC_RTC_DISABLE 0x00000080
#define MISC_UART48M 0x00000000
#define MISC_UARTCLKMSK 0x00000010
+#define MISC_PLLTIMEEN 0x00000002
-/* PRSC_CLK_CFG value */
-/*
- * Fout = Fin / (2^(N+1) * (M + 1))
- */
-#define MISC_PRSC_N_1 0x00001000
-#define MISC_PRSC_M_9 0x00000009
-#define MISC_PRSC_N_4 0x00004000
-#define MISC_PRSC_M_399 0x0000018F
-#define MISC_PRSC_N_6 0x00006000
-#define MISC_PRSC_M_2593 0x00000A21
-#define MISC_PRSC_M_124 0x0000007C
-#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
-
-/* PERIPH1_CLKEN, PERIPH1_RST value */
+/* periph1_clken, periph1_rst */
+#define MISC_MPMCMSK 0x60000000
+#define MISC_MPMCWE 0x40000000
+#define MISC_MPMCENB 0x20000000
+#define MISC_USBHENB 0x02000000
#define MISC_USBDENB 0x01000000
#define MISC_ETHENB 0x00800000
#define MISC_SMIENB 0x00200000
@@ -174,106 +151,38 @@ struct misc_regs {
#define MISC_I2CENB 0x00000080
#define MISC_SSP2ENB 0x00000070
#define MISC_UART0ENB 0x00000008
+#define MISC_PERIPH_RST_ALL 0x00000004
-/* PERIPH_CLK_CFG */
-#define XTALTIMEEN 0x00000001
-#define PLLTIMEEN 0x00000002
-#define CLCDCLK_SYNTH 0x00000000
-#define CLCDCLK_48MHZ 0x00000004
-#define CLCDCLK_EXT 0x00000008
-#define UARTCLK_MASK (0x1 << 4)
-#define UARTCLK_48MHZ 0x00000000
-#define UARTCLK_SYNTH 0x00000010
-#define IRDACLK_48MHZ 0x00000000
-#define IRDACLK_SYNTH 0x00000020
-#define IRDACLK_EXT 0x00000040
-#define RTC_DISABLE 0x00000080
-#define GPT1CLK_48MHZ 0x00000000
-#define GPT1CLK_SYNTH 0x00000100
-#define GPT2CLK_48MHZ 0x00000000
-#define GPT2CLK_SYNTH 0x00000200
-#define GPT3CLK_48MHZ 0x00000000
-#define GPT3CLK_SYNTH 0x00000400
-#define GPT4CLK_48MHZ 0x00000000
-#define GPT4CLK_SYNTH 0x00000800
-#define GPT5CLK_48MHZ 0x00000000
-#define GPT5CLK_SYNTH 0x00001000
-#define GPT1_FREEZE 0x00002000
-#define GPT2_FREEZE 0x00004000
-#define GPT3_FREEZE 0x00008000
-#define GPT4_FREEZE 0x00010000
-#define GPT5_FREEZE 0x00020000
-
-/* PERIPH1_CLKEN bits */
-#define PERIPH_ARM1_WE 0x00000001
-#define PERIPH_ARM1 0x00000002
-#define PERIPH_ARM2 0x00000004
-#define PERIPH_UART1 0x00000008
-#define PERIPH_UART2 0x00000010
-#define PERIPH_SSP1 0x00000020
-#define PERIPH_SSP2 0x00000040
-#define PERIPH_I2C 0x00000080
-#define PERIPH_JPEG 0x00000100
-#define PERIPH_FSMC 0x00000200
-#define PERIPH_FIRDA 0x00000400
-#define PERIPH_GPT4 0x00000800
-#define PERIPH_GPT5 0x00001000
-#define PERIPH_GPIO4 0x00002000
-#define PERIPH_SSP3 0x00004000
-#define PERIPH_ADC 0x00008000
-#define PERIPH_GPT3 0x00010000
-#define PERIPH_RTC 0x00020000
-#define PERIPH_GPIO3 0x00040000
-#define PERIPH_DMA 0x00080000
-#define PERIPH_ROM 0x00100000
-#define PERIPH_SMI 0x00200000
-#define PERIPH_CLCD 0x00400000
-#define PERIPH_GMAC 0x00800000
-#define PERIPH_USBD 0x01000000
-#define PERIPH_USBH1 0x02000000
-#define PERIPH_USBH2 0x04000000
-#define PERIPH_MPMC 0x08000000
-#define PERIPH_RAMW 0x10000000
-#define PERIPH_MPMC_EN 0x20000000
-#define PERIPH_MPMC_WE 0x40000000
-#define PERIPH_MPMCMSK 0x60000000
-
-#define PERIPH_CLK_ALL 0x0FFFFFF8
-#define PERIPH_RST_ALL 0x00000004
-
-/* DDR_PAD values */
-#define DDR_PAD_CNF_MSK 0x0000ffff
-#define DDR_PAD_SW_CONF 0x00060000
-#define DDR_PAD_SSTL_SEL 0x00000001
-#define DDR_PAD_DRAM_TYPE 0x00008000
-
-/* DDR_COMP values */
-#define DDR_COMP_ACCURATE 0x00000010
-
-/* SoC revision stuff */
-#define SOC_PRI_SHFT 16
-#define SOC_SEC_SHFT 8
+/* soc_core_id */
+#define MISC_PRISOCID_SHFT 16
+#define MISC_SECSOCID_SHFT 8
-/* Revision definitions */
-#define SOC_SPEAR_NA 0
+/* synth_clk */
+#define MISC_SYNTH23 0x00020003
+/* prsc_clk_cfg */
/*
- * The definitons have started from
- * 101 for SPEAr6xx
- * 201 for SPEAr3xx
- * 301 for SPEAr13xx
+ * Fout = Fin / (2^(N+1) * (M + 1))
*/
-#define SOC_SPEAR600_AA 101
-#define SOC_SPEAR600_AB 102
-#define SOC_SPEAR600_BA 103
-#define SOC_SPEAR600_BB 104
-#define SOC_SPEAR600_BC 105
-#define SOC_SPEAR600_BD 106
+#define MISC_PRSC_N_1 0x00001000
+#define MISC_PRSC_M_9 0x00000009
+#define MISC_PRSC_N_4 0x00004000
+#define MISC_PRSC_M_399 0x0000018F
+#define MISC_PRSC_N_6 0x00006000
+#define MISC_PRSC_M_2593 0x00000A21
+#define MISC_PRSC_M_124 0x0000007C
+#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* amem_cfg_ctrl */
+#define MISC_AMEM_CLKENB 0x00000001
-#define SOC_SPEAR300 201
-#define SOC_SPEAR310 202
-#define SOC_SPEAR320 203
+/* ddr_compensation */
+#define MISC_DDR_COMP_ACCURATE 0x00000010
-extern int get_socrev(void);
+/* ddr_pad */
+#define MISC_DDR_PAD_CNF_MSK 0x0000ffff
+#define MISC_DDR_PAD_SW_CONF 0x00060000
+#define MISC_DDR_PAD_SSTL_SEL 0x00000001
+#define MISC_DDR_PAD_DRAM_TYPE 0x00008000
#endif
diff --git a/arch/arm/include/asm/arch-spear/spear600.h b/arch/arm/include/asm/arch-spear/spear600.h
index c8b0047..dd4f531 100644
--- a/arch/arm/include/asm/arch-spear/spear600.h
+++ b/arch/arm/include/asm/arch-spear/spear600.h
@@ -32,7 +32,10 @@
#define CONFIG_SYS_PLUG_BASE 0xE1200000
#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
#define CONFIG_SYS_SMI_BASE 0xFC000000
+
#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SPEAR_MPMCREGS 100
+
#define CONFIG_SPEAR_TIMERBASE 0xFC800000
#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
#define CONFIG_SPEAR_MISCBASE 0xFCA80000
@@ -42,4 +45,14 @@
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
+#define SNOR_BOOT_SUPPORTED 1
+#define NAND_BOOT_SUPPORTED 1
+#define PNOR_BOOT_SUPPORTED 0
+#define USBD_BOOT_SUPPORTED 1
+#define TFTP_BOOT_SUPPORTED 0
+#define UART_BOOT_SUPPORTED 0
+#define MMC_BOOT_SUPPORTED 0
+#define SPI_BOOT_SUPPORTED 0
+#define I2C_BOOT_SUPPORTED 0
+
#endif
diff --git a/arch/arm/include/asm/arch-spear/syscntl.h b/arch/arm/include/asm/arch-spear/syscntl.h
index 2393d89..f55ce92 100644
--- a/arch/arm/include/asm/arch-spear/syscntl.h
+++ b/arch/arm/include/asm/arch-spear/syscntl.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef __SYSCTRL_H
-#define __SYSCTRL_H
+#ifndef ASM_ARCH_SPEAR_SYSCTRL_H
+#define ASM_ARCH_SPEAR_SYSCTRL_H
struct syscntl_regs {
u32 scctrl;
@@ -40,13 +40,16 @@ struct syscntl_regs {
const u32 scperstat;
};
-#define MODE_SHIFT 0x00000003
+#define SYSCNTL_STATE_MASK (0x07 << 3)
+#define SYSCNTL_STATE_NORMAL (0x04 << 3)
+#define SYSCNTL_STATE_SLOW (0x02 << 3)
+#define SYSCNTL_STATE_DOZE (0x01 << 3)
+#define SYSCNTL_STATE_SLEEP (0x00 << 3)
+#define SYSCNTL_REQ_NORMAL (0x04 << 0)
+#define SYSCNTL_REQ_SLOW (0x02 << 0)
+#define SYSCNTL_REQ_DOZE (0x01 << 0)
+#define SYSCNTL_REQ_SLEEP (0x00 << 0)
-#define NORMAL 0x00000004
-#define SLOW 0x00000002
-#define DOZE 0x00000001
-#define SLEEP 0x00000000
-
-#define PLL_TIM 0x01FFFFFF
+#define SYSCNTL_PLL_TIM 0x01FFFFFF
#endif
diff --git a/board/st/spear/config.mk b/board/st/spear/config.mk
index 9533c5f..971d60a 100644
--- a/board/st/spear/config.mk
+++ b/board/st/spear/config.mk
@@ -21,4 +21,10 @@
# MA 02111-1307 USA
#
+ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.img
+
+ifdef CONFIG_MACH_SPEAR600EVB
+ALL-y += $(obj)spl/u-boot-spl.img
+endif
+endif
diff --git a/board/st/spear/ddr/Makefile b/board/st/spear/ddr/Makefile
new file mode 100644
index 0000000..9f1c627
--- /dev/null
+++ b/board/st/spear/ddr/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2012
+# Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD)ddr.o
+
+SOBJS-y :=
+COBJS-y :=
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_DDR_MT47H64M16) += spear600_mt47h64m16_3_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_37e_166_cl4_sync.o
+COBJS-$(CONFIG_DDR_MT47H128M8) += spear600_mt47h128m8_3_266_cl5_async.o
+endif
+
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/board/st/spear/ddr/spear600_mt47h128m8_3_266_cl5_async.c
similarity index 95%
rename from arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
rename to board/st/spear/ddr/spear600_mt47h128m8_3_266_cl5_async.c
index 5edc115..abaa7b6 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
+++ b/board/st/spear/ddr/spear600_mt47h128m8_3_266_cl5_async.c
@@ -22,8 +22,9 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
-#if (CONFIG_DDR_PLL2)
+#if defined(CONFIG_ARCH_SPEAR6XX) && defined(CONFIG_SPEAR_DDR_PLL2)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x00000001,
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/board/st/spear/ddr/spear600_mt47h32m16_333_cl5_psync.c
similarity index 91%
rename from arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
rename to board/st/spear/ddr/spear600_mt47h32m16_333_cl5_psync.c
index 616b861..65e7371 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
+++ b/board/st/spear/ddr/spear600_mt47h32m16_333_cl5_psync.c
@@ -22,14 +22,16 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+#if defined(CONFIG_ARCH_SPEAR6XX) && \
+ (defined(CONFIG_SPEAR_DDR_PLL2) || defined(CONFIG_SPEAR_DDR_2HCLK))
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
+#if defined(CONFIG_SPEAR_DDR_PLL2)
0x00000001,
0x00000000,
-#elif (CONFIG_DDR_2HCLK)
+#elif defined(CONFIG_SPEAR_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/board/st/spear/ddr/spear600_mt47h32m16_37e_166_cl4_sync.c
similarity index 95%
rename from arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
rename to board/st/spear/ddr/spear600_mt47h32m16_37e_166_cl4_sync.c
index b89f77d..1e4e0d9 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
+++ b/board/st/spear/ddr/spear600_mt47h32m16_37e_166_cl4_sync.c
@@ -22,8 +22,9 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
-#if (CONFIG_DDR_HCLK)
+#if defined(CONFIG_ARCH_SPEAR6XX) && defined(CONFIG_SPEAR_DDR_HCLK)
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
0x03030301,
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/board/st/spear/ddr/spear600_mt47h64m16_3_333_cl5_psync.c
similarity index 91%
rename from arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
rename to board/st/spear/ddr/spear600_mt47h64m16_3_333_cl5_psync.c
index 0c39cd1..81cd706 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
+++ b/board/st/spear/ddr/spear600_mt47h64m16_3_333_cl5_psync.c
@@ -22,14 +22,16 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+#if defined(CONFIG_ARCH_SPEAR6XX) && \
+ (defined(CONFIG_SPEAR_DDR_PLL2) || defined(CONFIG_SPEAR_DDR_2HCLK))
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
+#if defined(CONFIG_SPEAR_DDR_PLL2)
0x00000001,
0x00000000,
-#elif (CONFIG_DDR_2HCLK)
+#elif defined(CONFIG_SPEAR_DDR_2HCLK)
0x02020201,
0x02020202,
#endif
diff --git a/board/st/spear/spear600evb.c b/board/st/spear/spear600evb.c
index b5901e6..17828a3 100644
--- a/board/st/spear/spear600evb.c
+++ b/board/st/spear/spear600evb.c
@@ -79,3 +79,94 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD)
+static void sel_1v8(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddr1v8, ddr2v5;
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000003;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000010;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ while (!(readl(&misc_p->ddr_1v8_compensation) & MISC_DDR_COMP_ACCURATE))
+ ;
+}
+
+static void sel_2v5(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddr1v8, ddr2v5;
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000003;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000010;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ while (!(readl(&misc_p->ddr_2v5_compensation) & MISC_DDR_COMP_ACCURATE))
+ ;
+}
+
+void board_ddr_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddrpad;
+ u32 core3v3, ddr1v8, ddr2v5;
+
+ /* DDR pad register configurations */
+ ddrpad = readl(&misc_p->ddr_pad);
+ ddrpad &= ~MISC_DDR_PAD_CNF_MSK;
+
+#if defined(CONFIG_SPEAR_DDR_HCLK)
+ ddrpad |= 0xEAAB;
+#elif defined(CONFIG_SPEAR_DDR_2HCLK)
+ ddrpad |= 0xEAAD;
+#elif defined(CONFIG_SPEAR_DDR_PLL2)
+ ddrpad |= 0xEAAD;
+#endif
+ writel(ddrpad, &misc_p->ddr_pad);
+
+ /* Compensation register configurations */
+ core3v3 = readl(&misc_p->core_3v3_compensation);
+ core3v3 &= 0x8080ffe0;
+ core3v3 |= 0x78000002;
+ writel(core3v3, &misc_p->core_3v3_compensation);
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000004;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000004;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ if ((readl(&misc_p->ddr_pad) & MISC_DDR_PAD_SW_CONF) ==
+ MISC_DDR_PAD_SW_CONF) {
+ /* Software memory configuration */
+ if (readl(&misc_p->ddr_pad) & MISC_DDR_PAD_SSTL_SEL)
+ sel_1v8();
+ else
+ sel_2v5();
+ } else {
+ /* Hardware memory configuration */
+ if (readl(&misc_p->ddr_pad) & MISC_DDR_PAD_DRAM_TYPE)
+ sel_1v8();
+ else
+ sel_2v5();
+ }
+}
+#endif
diff --git a/include/configs/spear600.h b/include/configs/spear600.h
index e64f26d..dfe8196 100644
--- a/include/configs/spear600.h
+++ b/include/configs/spear600.h
@@ -54,5 +54,16 @@
#define CONFIG_SYS_INIT_SP_ADDR (0xD2800000 + 0x2000 - \
GENERATED_GBL_DATA_SIZE)
+/* SPL configurations */
+#if defined(CONFIG_SPL)
+ #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+ #define CONFIG_SPL_MTD_SUPPORT
+ #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
+ #define CONFIG_SPL_LDSCRIPT \
+ "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+#endif
+
#include <configs/spear.h>
#endif /* __CONFIG_SPEAR600_H */
diff --git a/spl/Makefile b/spl/Makefile
index 20a943c..e38467a 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -61,6 +61,10 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
+ifeq ($(BOARD),spear)
+LIBS-y += board/$(BOARDDIR)/ddr/lib$(BOARD)ddr.o
+endif
+
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Enhancement PATCH 9/9] spear300evb: Add SPL support
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
` (6 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 8/9] spear/spl: Add support to boot from Parallel NOR device Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
7 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
This patch also adds related code for spear3xx which is later used for
spear310 and spear320 based boards
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
spear310evb: Add SPL support
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
spear320evb/spear320hmi: Add SPL support
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 1 +
arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c | 136 ++++++++++++++++++
arch/arm/include/asm/arch-spear/generic.h | 2 +
arch/arm/include/asm/arch-spear/spear300.h | 23 ++++
arch/arm/include/asm/arch-spear/spear310.h | 22 +++
arch/arm/include/asm/arch-spear/spear320.h | 25 ++++
arch/arm/include/asm/arch-spear/spear3xx.h | 2 +
board/st/spear/config.mk | 3 -
board/st/spear/ddr/Makefile | 5 +
board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c | 140 +++++++++++++++++++
.../spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c | 146 ++++++++++++++++++++
.../spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c | 146 ++++++++++++++++++++
.../spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c | 152 +++++++++++++++++++++
board/st/spear/spear300evb.c | 7 +
board/st/spear/spear310evb.c | 31 +++++
board/st/spear/spear320hmi.c | 7 +
board/st/spear/spear320plc.c | 7 +
include/configs/spear.h | 4 +
include/configs/spear300-evb.h | 5 +
include/configs/spear310-evb.h | 5 +
include/configs/spear3xx.h | 15 ++
21 files changed, 881 insertions(+), 3 deletions(-)
create mode 100644 board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c
create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c
create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c
create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 5ebdf65..fc2e136 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o spl_boot.o spl_nand.o
+COBJS-$(CONFIG_ARCH_SPEAR3XX) += spl-spear3xx.o
COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o
endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
index 7e2bc98..972768d 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
@@ -22,6 +22,10 @@
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
int get_socrev(void)
{
@@ -33,3 +37,135 @@ int get_socrev(void)
return SOC_SPEAR320;
#endif
}
+
+void spear3xx_ddr_comp_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddrpad;
+ u32 core3v3, ddr1v8;
+
+ /* DDR pad register configurations */
+ ddrpad = readl(&misc_p->ddr_pad);
+ ddrpad &= ~MISC_DDR_PAD_CNF_MSK;
+ ddrpad |= 0x3AA4;
+ writel(ddrpad, &misc_p->ddr_pad);
+
+ /* Compensation register configurations */
+ core3v3 = readl(&misc_p->core_3v3_compensation);
+ core3v3 &= 0x02fffff0;
+ core3v3 |= 0x78000008;
+ writel(core3v3, &misc_p->core_3v3_compensation);
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x02fffff0;
+ ddr1v8 |= 0x78000008;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+}
+
+/* getboottype() implementation for spear300 */
+#if defined(CONFIG_SOC_SPEAR300)
+u32 getboottype(void)
+{
+ u32 bootmask = 0;
+ u32 bootstrap = (readl(CONFIG_SYS_TELECOM_BASE) >> SPEAR300_BOOTSHFT) &
+ SPEAR300_BOOTMASK;
+
+ switch (bootstrap) {
+ case SPEAR300_USBBOOT:
+ bootmask |= BOOT_TYPE_USBD;
+ break;
+ case SPEAR300_TFTPI2CBOOT:
+ case SPEAR300_TFTPSPIBOOT:
+ bootmask |= BOOT_TYPE_TFTP;
+ break;
+ case SPEAR300_SNORBOOT:
+ bootmask |= BOOT_TYPE_SMI;
+ break;
+ case SPEAR300_PNOR8BOOT:
+ bootmask |= BOOT_TYPE_PNOR8;
+ break;
+ case SPEAR300_PNOR16BOOT:
+ bootmask |= BOOT_TYPE_PNOR16;
+ break;
+ case SPEAR300_NAND8BOOT:
+ case SPEAR300_NAND16BOOT:
+ bootmask |= BOOT_TYPE_NAND;
+ break;
+ case SPEAR300_UARTBOOT:
+ bootmask |= BOOT_TYPE_UART;
+ break;
+ default:
+ bootmask |= BOOT_TYPE_UNSUPPORTED;
+ break;
+ }
+
+ return bootmask;
+}
+#elif defined(CONFIG_SOC_SPEAR310)
+u32 getboottype(void)
+{
+ u32 bootmask = 0;
+ u32 bootstrap = (readl(SPEAR310_BOOT_REG) >> SPEAR310_BOOTSHFT) &
+ SPEAR310_BOOTMASK;
+
+ switch (bootstrap) {
+ case SPEAR310_USBBOOT:
+ bootmask |= BOOT_TYPE_USBD;
+ break;
+ case SPEAR310_SNORBOOT:
+ bootmask |= BOOT_TYPE_SMI;
+ break;
+ case SPEAR310_PNORBOOT:
+ bootmask |= BOOT_TYPE_PNOR8 | BOOT_TYPE_PNOR16;
+ break;
+ case SPEAR310_NANDBOOT:
+ bootmask |= BOOT_TYPE_NAND;
+ break;
+ default:
+ bootmask |= BOOT_TYPE_UNSUPPORTED;
+ break;
+ }
+
+ return bootmask;
+}
+#elif defined(CONFIG_SOC_SPEAR320)
+u32 getboottype(void)
+{
+ u32 bootmask = 0;
+ u32 bootstrap = (readl(SPEAR320_BOOT_REG) >> SPEAR320_BOOTSHFT) &
+ SPEAR320_BOOTMASK;
+
+ switch (bootstrap) {
+ case SPEAR320_USBBOOT:
+ bootmask |= BOOT_TYPE_USBD;
+ break;
+ case SPEAR320_TFTPI2CBOOT:
+ case SPEAR320_TFTPSPIBOOT:
+ bootmask |= BOOT_TYPE_TFTP;
+ break;
+ case SPEAR320_SNORBOOT:
+ bootmask |= BOOT_TYPE_SMI;
+ break;
+ case SPEAR320_PNOR8BOOT:
+ case SPEAR320_PNOR8NOACKBOOT:
+ bootmask |= BOOT_TYPE_PNOR8;
+ break;
+ case SPEAR320_PNOR16BOOT:
+ case SPEAR320_PNOR16NOACKBOOT:
+ bootmask |= BOOT_TYPE_PNOR16;
+ break;
+ case SPEAR320_NAND8BOOT:
+ case SPEAR320_NAND16BOOT:
+ bootmask |= BOOT_TYPE_NAND;
+ break;
+ case SPEAR320_UARTBOOT:
+ bootmask |= BOOT_TYPE_UART;
+ break;
+ default:
+ bootmask |= BOOT_TYPE_UNSUPPORTED;
+ break;
+ }
+
+ return bootmask;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-spear/generic.h b/arch/arm/include/asm/arch-spear/generic.h
index aa13b83..ffb8d4e 100644
--- a/arch/arm/include/asm/arch-spear/generic.h
+++ b/arch/arm/include/asm/arch-spear/generic.h
@@ -30,8 +30,10 @@ extern unsigned int setfreq_sz;
extern void board_ddr_init(void);
extern void board_lowlevel_late_init(void);
+/* Routines exported from SoC area */
extern void spear3xx_usbh_stop(void);
extern void spear6xx_usbh_stop(void);
+extern void spear3xx_ddr_comp_init(void);
extern u32 mpmc_conf_vals[];
diff --git a/arch/arm/include/asm/arch-spear/spear300.h b/arch/arm/include/asm/arch-spear/spear300.h
index 4bfa619..66ed612 100644
--- a/arch/arm/include/asm/arch-spear/spear300.h
+++ b/arch/arm/include/asm/arch-spear/spear300.h
@@ -26,6 +26,19 @@
#include <asm/arch/spear3xx.h>
+#define CONFIG_SYS_TELECOM_BASE 0x50000000
+ #define SPEAR300_BOOTSHFT 16
+ #define SPEAR300_BOOTMASK 0xF
+ #define SPEAR300_USBBOOT 0x0
+ #define SPEAR300_TFTPI2CBOOT 0x1
+ #define SPEAR300_TFTPSPIBOOT 0x2
+ #define SPEAR300_SNORBOOT 0x3
+ #define SPEAR300_PNOR8BOOT 0x4
+ #define SPEAR300_PNOR16BOOT 0x5
+ #define SPEAR300_NAND8BOOT 0x6
+ #define SPEAR300_NAND16BOOT 0x7
+ #define SPEAR300_UARTBOOT 0xA
+
#define CONFIG_SYS_FSMC_BASE 0x94000000
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
@@ -50,6 +63,16 @@
#define SPEAR300_MODE_CAMULCDW (0xE << 0)
#define SPEAR300_MODE_CAM1LCD (0xF << 0)
+#define SNOR_BOOT_SUPPORTED 1
+#define NAND_BOOT_SUPPORTED 1
+#define PNOR_BOOT_SUPPORTED 1
+#define USBD_BOOT_SUPPORTED 1
+#define TFTP_BOOT_SUPPORTED 1
+#define UART_BOOT_SUPPORTED 1
+#define MMC_BOOT_SUPPORTED 0
+#define SPI_BOOT_SUPPORTED 0
+#define I2C_BOOT_SUPPORTED 0
+
#define SPEAR3XX_FUNC_ENB_REG SPEAR300_RAS_REG1
/* externs related to pinmux */
diff --git a/arch/arm/include/asm/arch-spear/spear310.h b/arch/arm/include/asm/arch-spear/spear310.h
index 9d20237..91d0b53 100644
--- a/arch/arm/include/asm/arch-spear/spear310.h
+++ b/arch/arm/include/asm/arch-spear/spear310.h
@@ -38,12 +38,34 @@
#define CONFIG_SPEAR_RASBASE 0xB4000000
/* SPEAr310 RAS misc space registers and bitmasks */
+#define SPEAR310_BOOT_REG (CONFIG_SPEAR_RASBASE + 0x0)
+ #define SPEAR310_BOOTSHFT 0x0
+ #define SPEAR310_BOOTMASK 0x7
+ #define SPEAR310_USBBOOT 0x3
+ #define SPEAR310_NANDBOOT 0x2
+ #define SPEAR310_PNORBOOT 0x1
+ #define SPEAR310_SNORBOOT 0x0
+ #define SPEAR310_EMIBW_SHFT 0x3
+ #define SPEAR310_EMIBW_MASK 0x18
+ #define SPEAR310_EMIBW_8 0x0
+ #define SPEAR310_EMIBW_16 0x1
+ #define SPEAR310_EMIBW_32 0x2
#define SPEAR310_FUNCENB_REG (CONFIG_SPEAR_RASBASE + 0x8)
#define SPEAR310_SMII_REG (CONFIG_SPEAR_RASBASE + 0xC)
#define SPEAR310_SMII_PHY_SHIFT 0x0
#define SPEAR310_SMII_PHY_MASK 0x3
+#define SNOR_BOOT_SUPPORTED 1
+#define NAND_BOOT_SUPPORTED 1
+#define PNOR_BOOT_SUPPORTED 1
+#define USBD_BOOT_SUPPORTED 1
+#define TFTP_BOOT_SUPPORTED 0
+#define UART_BOOT_SUPPORTED 0
+#define MMC_BOOT_SUPPORTED 0
+#define SPI_BOOT_SUPPORTED 0
+#define I2C_BOOT_SUPPORTED 0
+
#define SPEAR3XX_FUNC_ENB_REG SPEAR310_FUNCENB_REG
/* externs related to pinmux */
diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h
index a027e10..5fe8fb0 100644
--- a/arch/arm/include/asm/arch-spear/spear320.h
+++ b/arch/arm/include/asm/arch-spear/spear320.h
@@ -44,6 +44,21 @@
#define SPEAR320_EXTENDED_MODE (1 << 4)
/* SPEAr320 RAS misc space registers and bitmasks */
+#define SPEAR320_BOOT_REG (CONFIG_SPEAR_RASBASE + 0x0)
+ #define SPEAR320_BOOTSHFT 0x0
+ #define SPEAR320_BOOTMASK 0xF
+ #define SPEAR320_USBBOOT 0x0
+ #define SPEAR320_TFTPI2CBOOT 0x1
+ #define SPEAR320_TFTPSPIBOOT 0x2
+ #define SPEAR320_SNORBOOT 0x3
+ #define SPEAR320_PNOR8BOOT 0x4
+ #define SPEAR320_PNOR16BOOT 0x5
+ #define SPEAR320_NAND8BOOT 0x6
+ #define SPEAR320_NAND16BOOT 0x7
+ #define SPEAR320_UARTBOOT 0xA
+ #define SPEAR320_PNOR8NOACKBOOT 0xC
+ #define SPEAR320_PNOR16NOACKBOOT 0xD
+
#define SPEAR320_RASSELECT_REG (CONFIG_SPEAR_RASBASE + 0x000C)
#define SPEAR320_CONTROL_REG (CONFIG_SPEAR_RASBASE + 0x0010)
@@ -452,6 +467,16 @@
#define PMX_SDHCI_CD_PORT_12_VAL 0
#define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
+#define SNOR_BOOT_SUPPORTED 1
+#define NAND_BOOT_SUPPORTED 1
+#define PNOR_BOOT_SUPPORTED 1
+#define USBD_BOOT_SUPPORTED 1
+#define TFTP_BOOT_SUPPORTED 1
+#define UART_BOOT_SUPPORTED 1
+#define MMC_BOOT_SUPPORTED 0
+#define SPI_BOOT_SUPPORTED 0
+#define I2C_BOOT_SUPPORTED 0
+
#define SPEAR3XX_FUNC_ENB_REG SPEAR320_RASSELECT_REG
/* externs related to pinmux */
diff --git a/arch/arm/include/asm/arch-spear/spear3xx.h b/arch/arm/include/asm/arch-spear/spear3xx.h
index f0df4e6..f63c21e 100644
--- a/arch/arm/include/asm/arch-spear/spear3xx.h
+++ b/arch/arm/include/asm/arch-spear/spear3xx.h
@@ -33,6 +33,8 @@
#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
#define CONFIG_SYS_SMI_BASE 0xFC000000
#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SPEAR_MPMCREGS 109
+
#define CONFIG_SPEAR_TIMERBASE 0xFC800000
#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
#define CONFIG_SPEAR_MISCBASE 0xFCA80000
diff --git a/board/st/spear/config.mk b/board/st/spear/config.mk
index 971d60a..49cc280 100644
--- a/board/st/spear/config.mk
+++ b/board/st/spear/config.mk
@@ -23,8 +23,5 @@
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.img
-
-ifdef CONFIG_MACH_SPEAR600EVB
ALL-y += $(obj)spl/u-boot-spl.img
endif
-endif
diff --git a/board/st/spear/ddr/Makefile b/board/st/spear/ddr/Makefile
index 9f1c627..b1f975f 100644
--- a/board/st/spear/ddr/Makefile
+++ b/board/st/spear/ddr/Makefile
@@ -36,6 +36,11 @@ COBJS-$(CONFIG_DDR_MT47H64M16) += spear600_mt47h64m16_3_333_cl5_psync.o
COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_333_cl5_psync.o
COBJS-$(CONFIG_DDR_MT47H32M16) += spear600_mt47h32m16_37e_166_cl4_sync.o
COBJS-$(CONFIG_DDR_MT47H128M8) += spear600_mt47h128m8_3_266_cl5_async.o
+
+COBJS-$(CONFIG_DDR_MT46H32M16) += spr3xx_mt46h32m16_6_166_cl3.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_166_cl4_async.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_266_cl5_async.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr3xx_mt47h64m16_3_333_cl5_async.o
endif
COBJS := $(sort $(COBJS-y))
diff --git a/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c b/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c
new file mode 100644
index 0000000..ea2c466
--- /dev/null
+++ b/board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000001,
+ 0x00000000,
+ 0x01000000,
+ 0x00000001,
+ 0x00000001,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+ 0x00000001,
+ 0x02000001,
+ 0x04000201,
+ 0x02020102,
+ 0x03020202,
+ 0x02040202,
+ 0x00000002,
+ 0x00000000,
+ 0x01000403,
+ 0x02020002,
+ 0x01000203,
+ 0x0505053f,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x05060a00,
+ 0x0000023f,
+ 0x00030600,
+ 0x0a000000,
+ 0x00000a02,
+ 0x00001b1b,
+ 0x7f000000,
+ 0x001a0000,
+ 0x11030700,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00000000,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000000,
+ 0x00000000,
+ 0x0000050e,
+ 0x00000000,
+ 0x2d890000,
+ 0x00140014,
+ 0x00000000,
+ 0x00008236,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x003a0000,
+ 0x00010000,
+ 0x00200000,
+ 0x003c00f4,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010001,
+ 0x01010001,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000001
+};
+#endif
diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c
new file mode 100644
index 0000000..42457b3
--- /dev/null
+++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000001,
+ 0x00000000,
+ 0x01000000,
+ 0x00000101,
+ 0x00000101,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+#if defined(CONFIG_SPEAR_DUAL_DDR)
+ 0x01020003,
+ 0x01000102,
+ 0x04000202,
+#else
+ 0x00000001,
+ 0x02000001,
+ 0x04000201,
+#endif
+ 0x03030104,
+ 0x03020202,
+ 0x01040000,
+ 0x00000001,
+ 0x00000000,
+ 0x03000404,
+ 0x02020002,
+ 0x03000203,
+ 0x0505053f,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x07080a00,
+ 0x0000023f,
+ 0x00030600,
+ 0x09000000,
+ 0x00000a02,
+ 0x00001e1e,
+ 0x7F000000,
+ 0x005F0000,
+ 0x16030700,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00000000,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000000,
+ 0x00000000,
+ 0x0000050e,
+ 0x00000000,
+ 0x2d8900c8,
+ 0x00c80017,
+ 0x00000000,
+ 0x00008236,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x003a0000,
+ 0x00010000,
+ 0x00200000,
+ 0x003c00f4,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010001,
+ 0x01000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00430000,
+ 0x00000002
+};
+#endif
diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c
new file mode 100644
index 0000000..fc8524d
--- /dev/null
+++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) && defined(CONFIG_SPEAR_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000001,
+ 0x00000000,
+ 0x01000000,
+ 0x00000101,
+ 0x00000101,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+#if defined(CONFIG_SPEAR_DUAL_DDR)
+ 0x01020003,
+ 0x01000102,
+ 0x04000202,
+#else
+ 0x00000001,
+ 0x02000001,
+ 0x04000201,
+#endif
+ 0x03030104,
+ 0x03020202,
+ 0x01040000,
+ 0x00000001,
+ 0x00000000,
+ 0x03000405,
+ 0x02030002,
+ 0x04000204,
+ 0x0505053f,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0a0b0a00,
+ 0x0000023f,
+ 0x00040800,
+ 0x0e000000,
+ 0x00000f02,
+ 0x00002020,
+ 0x7f000000,
+ 0x005f0000,
+ 0x22040b00,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00000000,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000000,
+ 0x00000000,
+ 0x0000081b,
+ 0x00000000,
+ 0x48e100c8,
+ 0x00c80025,
+ 0x00000000,
+ 0x0000d056,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00230000,
+ 0x001f0023,
+ 0x00400000,
+ 0x00250099,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010001,
+ 0x01000000,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x006b0000,
+ 0x00000002
+};
+#endif
diff --git a/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c b/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c
new file mode 100644
index 0000000..b8be8ae
--- /dev/null
+++ b/board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) && \
+ (defined(CONFIG_SPEAR_DDR_PLL2) || defined(CONFIG_SPEAR_DDR_2HCLK))
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if defined(CONFIG_SPEAR_DDR_PLL2)
+ 0x00000001,
+ 0x00000000,
+#else
+ 0x02020201,
+ 0x00000202,
+#endif
+ 0x01000000,
+ 0x00000101,
+ 0x00000101,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+#if defined(CONFIG_SPEAR_DUAL_DDR)
+ 0x01020003,
+ 0x01000102,
+ 0x04000202,
+#else
+ 0x00000001,
+ 0x02000001,
+ 0x04000201,
+#endif
+ 0x03030104,
+ 0x03020202,
+ 0x01040000,
+ 0x00000001,
+ 0x00000000,
+ 0x03000405,
+ 0x03040002,
+ 0x04000305,
+ 0x0505053f,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x00000001,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0a0c0a00,
+ 0x0000023f,
+ 0x00050a00,
+ 0x11000000,
+ 0x00001302,
+ 0x00001c1c,
+ 0x7c000000,
+ 0x005c0000,
+ 0x2b050e00,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00000000,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a24,
+ 0x00000000,
+ 0x5b1c00c8,
+ 0x00c8002e,
+ 0x00000000,
+ 0x0001046b,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x001c0000,
+ 0x0019001c,
+ 0x00100000,
+ 0x001e007a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010001,
+ 0x01000000,
+ 0x00000001,
+ 0x00400000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00860000,
+ 0x00000002
+};
+#endif
diff --git a/board/st/spear/spear300evb.c b/board/st/spear/spear300evb.c
index 2ea598a..2f092fe 100644
--- a/board/st/spear/spear300evb.c
+++ b/board/st/spear/spear300evb.c
@@ -99,3 +99,10 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD)
+void board_ddr_init(void)
+{
+ spear3xx_ddr_comp_init();
+}
+#endif
diff --git a/board/st/spear/spear310evb.c b/board/st/spear/spear310evb.c
index 7f70008..fa5f5e2 100644
--- a/board/st/spear/spear310evb.c
+++ b/board/st/spear/spear310evb.c
@@ -32,6 +32,7 @@
#include <asm/arch/generic.h>
#include <asm/arch/misc.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/spl_pnor.h>
#if defined(CONFIG_CMD_NAND)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -109,3 +110,33 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD)
+void board_ddr_init(void)
+{
+ spear3xx_ddr_comp_init();
+}
+
+/*
+void soc_init(void)
+{
+ writel(0x2f7bc210, &misc_p->plgpio3_pad_prg);
+ writel(0x017bdef6, &misc_p->plgpio4_pad_prg);
+}
+*/
+
+pnor_width_t get_pnor_width(void)
+{
+ u32 emi_buswidth = (readl(SPEAR310_BOOT_REG) & SPEAR310_EMIBW_MASK) >>
+ SPEAR310_EMIBW_SHFT;
+
+ if (SPEAR310_EMIBW_8 == emi_buswidth)
+ return PNOR_WIDTH_8;
+ else if (SPEAR310_EMIBW_16 == emi_buswidth)
+ return PNOR_WIDTH_16;
+ else if (SPEAR310_EMIBW_32 == emi_buswidth)
+ return PNOR_WIDTH_32;
+ else
+ return PNOR_WIDTH_SEARCH;
+}
+#endif
diff --git a/board/st/spear/spear320hmi.c b/board/st/spear/spear320hmi.c
index 562bdda..886a79d 100644
--- a/board/st/spear/spear320hmi.c
+++ b/board/st/spear/spear320hmi.c
@@ -118,3 +118,10 @@ int board_mmc_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD)
+void board_ddr_init(void)
+{
+ spear3xx_ddr_comp_init();
+}
+#endif
diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c
index 315fe2d..2a408df 100644
--- a/board/st/spear/spear320plc.c
+++ b/board/st/spear/spear320plc.c
@@ -135,3 +135,10 @@ int board_mmc_init(bd_t *bis)
return ret;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD)
+void board_ddr_init(void)
+{
+ spear3xx_ddr_comp_init();
+}
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 4cb551d..d960d47 100644
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -199,6 +199,10 @@
#define CONFIG_SYS_DCACHE_OFF
#endif
+#ifndef CONFIG_SYS_PNOR_BOOT_BASE
+ #define CONFIG_SYS_PNOR_BOOT_BASE 0x0
+#endif
+
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/spear300-evb.h b/include/configs/spear300-evb.h
index e3f4ab4..2a222af 100644
--- a/include/configs/spear300-evb.h
+++ b/include/configs/spear300-evb.h
@@ -78,6 +78,11 @@
/* ST SMI (Serial flash) configurations */
#define CONFIG_ST_SMI
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_SPEAR_DDR_2HCLK
+#define CONFIG_DDR_MT47H64M16
+
#if defined(CONFIG_ENV_IS_IN_FLASH)
/* Environment is in serial NOR flash */
#define CONFIG_ENV_ADDR 0xF8060000
diff --git a/include/configs/spear310-evb.h b/include/configs/spear310-evb.h
index 505c8a4..12dd5eb 100644
--- a/include/configs/spear310-evb.h
+++ b/include/configs/spear310-evb.h
@@ -95,6 +95,11 @@
#define CONFIG_ST_SMI
#endif
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_SPEAR_DDR_2HCLK
+#define CONFIG_DDR_MT47H64M16
+
/* CFI Driver configurations */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
index e89e9c2..3f53b20 100644
--- a/include/configs/spear3xx.h
+++ b/include/configs/spear3xx.h
@@ -46,5 +46,20 @@
#define CONFIG_SYS_INIT_SP_ADDR (0xD2800000 + 0x2000 - \
GENERATED_GBL_DATA_SIZE)
+/* SPL configurations */
+#if defined(CONFIG_SPL)
+ #define CONFIG_SPL_TEXT_BASE 0xD2800B00
+ #define CONFIG_SYS_SNOR_BOOT_BASE 0xF8010000
+ #define CONFIG_SYS_NAND_BOOT_BLK 4
+
+ #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_LIBGENERIC_SUPPORT
+ #define CONFIG_SPL_MTD_SUPPORT
+ #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
+ #define CONFIG_SPL_LDSCRIPT \
+ "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+#endif
+
#include <configs/spear.h>
#endif /* __CONFIG_SPEAR3XX_H */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 09/11] spear: Add POST memory support
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (6 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 08/11] spear/spl: Cleanup spear SPL Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 10/11] spear: Enable ehci support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 11/11] spear3xx: FIX: Enable access to memory for spear310 and spear320 Vipin Kumar
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The xloader had a basic pattern read/write test with in itself. With the source
upgrading to SPL, it is now more convenient to use the Power On Self Test for
memory supported by u-boot.
This patch adds the support for memory POST test.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 30 ++++++++++++++++++++++++++++++
include/configs/spear.h | 2 ++
2 files changed, 32 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index f03b2bb..d7608b2 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -120,3 +120,33 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_POST
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ /*
+ * Run the POST test on 64 MB memory starting from CONFIG_SYS_LOAD_ADDR
+ * The assumption here is that the DDR present on board is >= 128MB.
+ *
+ * The test runs before relocation (after the code copy has taken
+ * place), so it can not touch either before or after relocation areas
+ * of U-boot
+ *
+ * DDR usage
+ * <--------->|<---------------- / --------------->|<---------->
+ * U-boot Area to be used for U-boot
+ * before POST test after
+ * relocation relocation
+ */
+
+ *vstart = CONFIG_SYS_LOAD_ADDR;
+ *size = 64 << 20;
+
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ hang();
+}
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 3a73811..a8ddf54 100644
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -154,6 +154,8 @@
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY
+#define CONFIG_SYS_POST_WORD_ADDR 0x0
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 10/11] spear: Enable ehci support
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (7 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 09/11] spear: Add POST memory support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 11/11] spear3xx: FIX: Enable access to memory for spear310 and spear320 Vipin Kumar
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/Makefile | 2 ++
arch/arm/cpu/arm926ejs/spear/cpu.c | 3 +++
arch/arm/cpu/arm926ejs/spear/spear3xx.c | 43 +++++++++++++++++++++++++++++++
arch/arm/cpu/arm926ejs/spear/spear6xx.c | 43 +++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-spear/generic.h | 3 +++
drivers/usb/host/ehci-spear.c | 9 ++++++-
6 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/spear3xx.c
create mode 100644 arch/arm/cpu/arm926ejs/spear/spear6xx.c
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 3fe7e26..7d11035 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -30,6 +30,8 @@ COBJS-y := cpu.o \
timer.o
COBJS-$(CONFIG_ST_EMI) += emi.o
+COBJS-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
+COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o spl_boot.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index d7608b2..59655f5 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -88,6 +88,9 @@ int arch_cpu_init(void)
#if defined(CONFIG_NAND_FSMC)
periph1_clken |= MISC_FSMCENB;
#endif
+#if defined(CONFIG_USB_EHCI_SPEAR)
+ periph1_clken |= MISC_USBHENB;
+#endif
writel(periph1_clken, &misc_p->periph1_clken);
diff --git a/arch/arm/cpu/arm926ejs/spear/spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
new file mode 100644
index 0000000..7a85fa9
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/misc.h>
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+void spear3xx_usbh_stop(void)
+{
+ struct misc_regs *const misc_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 periph1_rst = readl(misc_p->periph1_rst);
+
+ periph1_rst |= MISC_USBHENB;
+ writel(periph1_rst, misc_p->periph1_rst);
+
+ udelay(1000);
+ periph1_rst &= ~MISC_USBHENB;
+ writel(periph1_rst, misc_p->periph1_rst);
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spear6xx.c b/arch/arm/cpu/arm926ejs/spear/spear6xx.c
new file mode 100644
index 0000000..0a798ec
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear6xx.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/misc.h>
+
+#if defined(CONFIG_USB_EHCI_SPEAR)
+void spear6xx_usbh_stop(void)
+{
+ struct misc_regs *const misc_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 periph1_rst = readl(misc_p->periph1_rst);
+
+ periph1_rst |= MISC_USBHENB;
+ writel(periph1_rst, misc_p->periph1_rst);
+
+ udelay(1000);
+ periph1_rst &= ~MISC_USBHENB;
+ writel(periph1_rst, misc_p->periph1_rst);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-spear/generic.h b/arch/arm/include/asm/arch-spear/generic.h
index 68a775e..b7026e2 100644
--- a/arch/arm/include/asm/arch-spear/generic.h
+++ b/arch/arm/include/asm/arch-spear/generic.h
@@ -30,6 +30,9 @@ extern unsigned int setfreq_sz;
extern void board_ddr_init(void);
extern void board_lowlevel_late_init(void);
+extern void spear3xx_usbh_stop(void);
+extern void spear6xx_usbh_stop(void);
+
extern u32 mpmc_conf_vals[];
/*
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index f99bd1f..71c4ea2 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -30,7 +30,7 @@
#include <usb.h>
#include "ehci.h"
#include <asm/arch/hardware.h>
-
+#include <asm/arch/generic.h>
/*
* Create the appropriate control structures to manage
@@ -55,5 +55,12 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
*/
int ehci_hcd_stop(int index)
{
+#if defined(CONFIG_ARCH_SPEAR3XX)
+ spear3xx_usbh_stop();
+#elif defined(CONFIG_ARCH_SPEAR6XX)
+ spear6xx_usbh_stop();
+#else
+#error No spear platforms defined
+#endif
return 0;
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 10/19] usb/gadget/designware_otg: Add support for designware otg
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (6 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 08/19] net/designware: Do not select MIIPORT for RGMII interface Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 11/19] usb/host/ehci: Add support for EHCI on spear Vipin Kumar
` (8 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
From: Pratyush Anand <pratyush.anand@st.com>
Driver for designware otg device only implements device functionality and is
meant to be used with usbtty interface. This driver will work mainly for Control
and Bulk endpoints. Periodic transfer has not been verified using these drivers.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/serial/usbtty.h | 2 +
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/designware_otg.c | 1063 +++++++++++++++++++++++++++++++++++
include/usb/designware_otg.h | 500 ++++++++++++++++
4 files changed, 1566 insertions(+)
create mode 100644 drivers/usb/gadget/designware_otg.c
create mode 100644 include/usb/designware_otg.h
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index eb670da..bd3bcbc 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -35,6 +35,8 @@
#include <usb/pxa27x_udc.h>
#elif defined(CONFIG_DW_UDC)
#include <usb/designware_udc.h>
+#elif defined(CONFIG_DW_OTG)
+#include <usb/designware_otg.h>
#endif
#include <version.h>
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 040eaba..30ab931 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -43,6 +43,7 @@ ifdef CONFIG_USB_DEVICE
COBJS-y += core.o
COBJS-y += ep0.o
COBJS-$(CONFIG_DW_UDC) += designware_udc.o
+COBJS-$(CONFIG_DW_OTG) += designware_otg.o
COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o
COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o
COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
diff --git a/drivers/usb/gadget/designware_otg.c b/drivers/usb/gadget/designware_otg.c
new file mode 100644
index 0000000..57f6f15
--- /dev/null
+++ b/drivers/usb/gadget/designware_otg.c
@@ -0,0 +1,1063 @@
+/*
+ * Based on drivers/usb/gadget/designware_otg.c
+ * Synopsys DW OTG Device bus interface driver
+ *
+ * (C) Copyright 2011
+ * Pratyush Anand, ST Micoelectronics, pratyush.anand at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <usbdevice.h>
+#include "ep0.h"
+#include <usb/designware_otg.h>
+#include <asm/arch/hardware.h>
+
+#define UDC_INIT_MDELAY 80 /* Device settle delay */
+
+/* Some kind of debugging output... */
+#ifndef DEBUG_DWUSBTTY
+#define UDCDBG(str)
+#define UDCDBGA(fmt, args...)
+#else
+#define UDCDBG(str) serial_printf(str "\n")
+#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
+#endif
+
+static struct urb *ep0_urb;
+static struct usb_device_instance *udc_device;
+
+static struct device_if device_if_mem;
+static struct device_if *dev_if = &device_if_mem;
+#if defined(CONFIG_USBD_HS)
+#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_HS_PACKET_SIZE
+#endif
+
+static void udc_set_addr_ctrl(u32 address);
+static void udc_set_cfg_ctrl(u32 config);
+
+static struct usb_endpoint_instance *dw_find_ep(int ep)
+{
+ int i;
+
+ for (i = 0; i < udc_device->bus->max_endpoints; i++) {
+ if ((udc_device->bus->endpoint_array[i].endpoint_address &
+ USB_ENDPOINT_NUMBER_MASK) == ep)
+ return &udc_device->bus->endpoint_array[i];
+ }
+ return NULL;
+}
+
+/*
+ * This function reads a packet from the Rx FIFO into the destination buffer.
+ * To read SETUP data use dwc_otg_read_setup_packet.
+ */
+void dwc_otg_read_packet(struct dwc_ep *ep, u16 _bytes)
+{
+ u32 i;
+ int word_count = (_bytes + 3) / 4;
+ u32 *fifo = dev_if->data_fifo[0];
+ u32 *data_buff = (u32 *) ep->xfer_buff;
+ u32 unaligned;
+ /*
+ * This requires reading data from the FIFO into a u32 temp buffer,
+ * then moving it into the data buffer.
+ */
+ if ((_bytes < 4) && (_bytes > 0)) {
+ unaligned = readl(fifo);
+ memcpy(data_buff, &unaligned, _bytes);
+ } else {
+ for (i = 0; i < word_count; i++, data_buff++)
+ *data_buff = readl(fifo);
+ }
+}
+
+/* Handle RX transaction on non-ISO endpoint. */
+static void dw_udc_epn_rx(struct dwc_ep *ep, int bcnt)
+{
+ struct urb *urb;
+ struct usb_endpoint_instance *endpoint = dw_find_ep(ep->num);
+
+ if (endpoint) {
+ urb = endpoint->rcv_urb;
+
+ if (urb) {
+ ep->xfer_buff = urb->buffer + urb->actual_length;
+ dwc_otg_read_packet(ep, bcnt);
+ usbd_rcv_complete(endpoint, bcnt, 0);
+ }
+ }
+}
+
+/*
+ * This function writes a packet into the Tx FIFO associated with the EP.
+ * The buffer is padded to DWORD on a per packet basis in
+ * slave/dma mode if the MPS is not DWORD aligned. The last packet, if
+ * short, is also padded to a multiple of DWORD.
+ *
+ * ep->xfer_buff always starts DWORD aligned in memory and is a
+ * multiple of DWORD in length
+ *
+ * ep->xfer_len can be any number of bytes
+ *
+ * FIFO access is DWORD
+ */
+static void dwc_otg_ep_write_packet(struct dwc_ep *ep)
+{
+ u32 i;
+ u32 dword_count;
+ u32 *fifo;
+ u32 *data_buff = (u32 *) ep->xfer_buff;
+ u32 temp, unaligned;
+ struct device_in_ep_regs *in_ep_regs = dev_if->in_ep_regs[ep->num];
+ struct core_global_regs *core_global_regs = dev_if->core_global_regs;
+
+ /*
+ * Find the DWORD length, padded by extra bytes as neccessary if MPS
+ * is not a multiple of DWORD
+ */
+ dword_count = (ep->xfer_len + 3) / 4;
+ fifo = dev_if->data_fifo[ep->num];
+
+ /* program pkt count */
+ temp = ep->xfer_len;
+ temp |= (1 << PKTCNT_SHIFT);
+ writel(temp, &in_ep_regs->dieptsiz);
+
+ /* enable EP*/
+ temp = readl(&in_ep_regs->diepctl);
+ temp |= (EPENA | CNAK);
+ writel(temp, &in_ep_regs->diepctl);
+
+ /* clear TX Fifo Empty intr*/
+ writel(NPTXFEMPTY, &core_global_regs->gintsts);
+
+ temp = readl(&core_global_regs->gintmsk);
+ temp |= NPTXFEMPTY;
+ writel(temp, &core_global_regs->gintmsk);
+
+ while (!(readl(&core_global_regs->gintsts) & NPTXFEMPTY))
+ ;
+
+ /* write to fifo */
+ if ((ep->xfer_len < 4) && (ep->xfer_len > 0)) {
+ memcpy(&unaligned, data_buff, ep->xfer_len);
+ *fifo = unaligned;
+ } else {
+ for (i = 0; i < dword_count; i++, data_buff++)
+ *fifo = *data_buff;
+ }
+
+ writel(NPTXFEMPTY, &core_global_regs->gintsts);
+
+ /* check for transfer completion*/
+ while (!(readl(&in_ep_regs->diepint) & XFERCOMPL))
+ ;
+
+ writel(XFERCOMPL, &in_ep_regs->diepint);
+
+ temp = readl(&core_global_regs->gintmsk);
+ temp &= ~NPTXFEMPTY;
+ writel(temp, &core_global_regs->gintmsk);
+}
+
+/* Handle TX transaction on non-ISO endpoint. */
+static void dw_udc_epn_tx(struct dwc_ep *ep)
+{
+ struct usb_endpoint_instance *endpoint = dw_find_ep(ep->num);
+ struct urb *urb = endpoint->tx_urb;
+ int align;
+
+ if (!endpoint)
+ return;
+
+ /*
+ * We need to transmit a terminating zero-length packet now if
+ * we have sent all of the data in this URB and the transfer
+ * size was an exact multiple of the packet size.
+ */
+ if (urb && (endpoint->last == endpoint->tx_packetSize) &&
+ (urb->actual_length - endpoint->sent -
+ endpoint->last == 0)) {
+ /* handle zero length packet here */
+ ep->xfer_len = 0;
+ dwc_otg_ep_write_packet(ep);
+ }
+
+ if (urb && urb->actual_length) {
+ /* retire the data that was just sent */
+ usbd_tx_complete(endpoint);
+ /*
+ * Check to see if we have more data ready to transmit
+ * now.
+ */
+ if (urb && urb->actual_length) {
+ /* write data to FIFO */
+ ep->xfer_len = MIN(urb->actual_length - endpoint->sent,
+ endpoint->tx_packetSize);
+
+ if (ep->xfer_len) {
+ ep->xfer_buff = urb->buffer + endpoint->sent;
+
+ /*
+ * This ensures that USBD packet fifo is
+ * accessed through word aligned pointer or
+ * through non word aligned pointer but only
+ * with a max length to make the next packet
+ * word aligned
+ */
+
+ align = ((ulong)ep->xfer_buff % sizeof(int));
+ if (align)
+ ep->xfer_len = MIN(ep->xfer_len,
+ sizeof(int) - align);
+
+ dwc_otg_ep_write_packet(ep);
+ }
+ endpoint->last = ep->xfer_len;
+
+ } else if (urb && (urb->actual_length == 0)) {
+ /* udc_set_nak(ep); */
+ }
+ }
+}
+
+/* This function returns pointer to out ep struct with number num */
+struct dwc_ep *get_out_ep(u32 num)
+{
+ u32 i;
+ int num_out_eps = MAX_EPS_CHANNELS;
+ struct dwc_pcd *pcd = &dev_if->pcd;
+
+ if (num == 0) {
+ return &pcd->ep0;
+ } else {
+ for (i = 0; i < num_out_eps; ++i) {
+ if (pcd->out_ep[i].num == num)
+ return &pcd->out_ep[i];
+ }
+ }
+ return 0;
+}
+
+/* This function returns pointer to in ep struct with number num */
+struct dwc_ep *get_in_ep(u32 num)
+{
+ u32 i;
+ int num_out_eps = MAX_EPS_CHANNELS;
+ struct dwc_pcd *pcd = &dev_if->pcd;
+
+ if (num == 0) {
+ return &pcd->ep0;
+ } else {
+ for (i = 0; i < num_out_eps; ++i) {
+ if (pcd->in_ep[i].num == num)
+ return &pcd->in_ep[i];
+ }
+ }
+ return 0;
+}
+
+/*
+ * This function reads the 8 bytes of the setup packet from the Rx FIFO into the
+ * destination buffer. It is called from the Rx Status Queue Level (RxStsQLvl)
+ * interrupt routine when a SETUP packet has been received in Slave mode.
+ */
+static void dwc_otg_read_setup_packet(u32 *dest)
+{
+ dest[0] = readl(dev_if->data_fifo[0]);
+ dest[1] = readl(dev_if->data_fifo[0]);
+}
+
+/*
+ * This function handles the Rx Status Queue Level Interrupt, which
+ * indicates that there is a least one packet in the Rx FIFO. The
+ * packets are moved from the FIFO to memory, where they will be
+ * processed when the Endpoint Interrupt Register indicates Transfer
+ * Complete or SETUP Phase Done.
+ *
+ * Repeat the following until the Rx Status Queue is empty:
+ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
+ * info
+ * -# If Receive FIFO is empty then skip to step Clear the interrupt
+ * and exit
+ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
+ * SETUP data to the buffer
+ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
+ * to the destination buffer
+ */
+static int dwc_otg_pcd_handle_rx_status_q_level_intr(void)
+{
+ struct core_global_regs *global_regs = dev_if->core_global_regs;
+ struct dwc_pcd *pcd = &dev_if->pcd;
+ u32 gintmsk;
+ u32 status;
+ struct dwc_ep *ep;
+ u32 bcnt;
+
+ /* Disable the Rx Status Queue Level interrupt */
+ gintmsk = readl(&global_regs->gintmsk);
+ gintmsk &= ~RXSTSQLVL;
+ writel(gintmsk, &global_regs->gintmsk);
+
+ /* Get the Status from the top of the FIFO */
+ status = readl(&global_regs->grxstsp);
+ /* Get pointer to EP structure */
+ ep = get_out_ep((status & EPNUMMSK) >> EPNUM_SHIFT);
+ bcnt = (status & BCNTMSK) >> BCNT_SHIFT;
+
+ switch ((status & PKTSTSMSK) >> PKTSTS_SHIFT) {
+ case DWC_DSTS_GOUT_NAK:
+ break;
+ case DWC_STS_DATA_UPDT:
+ if (bcnt)
+ dw_udc_epn_rx(ep, bcnt);
+ break;
+ case DWC_STS_XFER_COMP:
+ break;
+ case DWC_DSTS_SETUP_COMP:
+ break;
+ case DWC_DSTS_SETUP_UPDT:
+ dwc_otg_read_setup_packet((u32 *)pcd->req);
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the Rx Status Queue Level interrupt */
+ gintmsk = readl(&global_regs->gintmsk);
+ gintmsk |= RXSTSQLVL;
+ writel(gintmsk, &global_regs->gintmsk);
+
+ /* Clear interrupt */
+ writel(RXSTSQLVL, &global_regs->gintsts);
+
+ return 1;
+}
+
+/*
+ * This function starts the Zero-Length Packet for the IN status phase
+ * of a 2 stage control transfer.
+ */
+static void do_setup_in_status_phase(struct device_if *dev_if)
+{
+ struct device_out_ep_regs *out_regs =
+ dev_if->out_ep_regs[0];
+ u32 doepctl, doeptsiz;
+ doeptsiz = 0;
+ doeptsiz |= (1 << PKTCNT_SHIFT);
+ writel(doeptsiz, &out_regs->doeptsiz);
+ doepctl = readl(&out_regs->doepctl);
+ doepctl |= (CNAK | EPENA);
+ writel(doepctl, &out_regs->doepctl);
+}
+
+static void udc_set_stall(int epid, int dir)
+{
+ if (dir)
+ writel(readl(&dev_if->in_ep_regs[epid]->diepctl) | SSTALL,
+ &dev_if->in_ep_regs[epid]->diepctl);
+ else
+ writel(readl(&dev_if->out_ep_regs[epid]->doepctl) | SSTALL,
+ &dev_if->out_ep_regs[epid]->doepctl);
+}
+
+/*
+ * This function handles EP0 Control transfers.
+ *
+ * The state of the control tranfers are tracked in ep0state
+ *
+ * A flag set indicates that it is not the first packet, so do not
+ * process setup data now. it has alreday been processed, just send the
+ * next data packet
+ */
+void handle_ep0(int in_flag)
+{
+ struct dwc_pcd *pcd = &dev_if->pcd;
+ struct dwc_ep *ep0 = &pcd->ep0;
+ struct usb_device_request *ctrl = pcd->req;
+
+ /* handle inepint, only when more than 64 bytes to transfer*/
+ if (in_flag & !ep0_urb->actual_length)
+ return;
+
+ if (!ep0_urb->actual_length) {
+ if (ep0_recv_setup(ep0_urb)) {
+ udc_set_stall(0, ctrl->bmRequestType & USB_DIR_IN);
+ return;
+ }
+ if (ep0_urb->device->address)
+ udc_set_addr_ctrl(ep0_urb->device->address);
+
+ if (ep0_urb->device->configuration)
+ udc_set_cfg_ctrl(ep0_urb->device->configuration);
+
+ ep0->xfer_buff = (u8 *)ep0_urb->buffer;
+ } else
+ ep0->xfer_buff += EP0_MAX_PACKET_SIZE;
+
+ if (ep0_urb->actual_length <= EP0_MAX_PACKET_SIZE) {
+ ep0->xfer_len = ep0_urb->actual_length;
+ ep0_urb->actual_length = 0;
+ } else {
+ ep0->xfer_len = EP0_MAX_PACKET_SIZE;
+ ep0_urb->actual_length -= EP0_MAX_PACKET_SIZE;
+ }
+
+ if (ctrl->bmRequestType & USB_DIR_IN) {
+ dwc_otg_ep_write_packet(ep0);
+ if (!ep0_urb->actual_length)
+ do_setup_in_status_phase(dev_if);
+ } else {
+ if (!ctrl->wLength)
+ dwc_otg_ep_write_packet(ep0);
+ else
+ udc_set_stall(0, ctrl->bmRequestType & USB_DIR_OUT);
+ }
+}
+
+/*
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the OUT endpoint interrupt bits.
+ */
+static u32 dwc_otg_read_dev_all_out_ep_intr(void)
+{
+ u32 v;
+
+ v = readl(&dev_if->dev_global_regs->daint) &
+ readl(&dev_if->dev_global_regs->daintmsk);
+ return v >> 16;
+}
+
+/*
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the IN endpoint interrupt bits.
+ */
+static u32 dwc_otg_read_dev_all_in_ep_intr(void)
+{
+ u32 v;
+
+ v = readl(&dev_if->dev_global_regs->daint) &
+ readl(&dev_if->dev_global_regs->daintmsk);
+ return v & 0xffff;
+}
+
+/* This function returns the Device OUT EP Interrupt register */
+static u32 dwc_otg_read_doep_intr(struct dwc_ep *ep)
+{
+ u32 v;
+
+ v = readl(&dev_if->out_ep_regs[ep->num]->doepint) &
+ readl(&dev_if->dev_global_regs->doepmsk);
+ return v;
+}
+
+/*This function returns the Device IN EP Interrupt register */
+static u32 dwc_otg_read_diep_intr(struct dwc_ep *ep)
+{
+ u32 v;
+
+ v = readl(&dev_if->in_ep_regs[ep->num]->diepint) &
+ readl(&dev_if->dev_global_regs->diepmsk);
+ return v;
+}
+
+/*
+ * This function configures EPO to receive SETUP packets.
+ *
+ * Program the following fields in the endpoint specific registers for Control
+ * OUT EP 0, in order to receive a setup packet:
+ *
+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
+ *
+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup
+ * packets)
+ *
+ * In DMA mode, DOEPDMA0 Register with a memory address to store any setup
+ * packets received
+ */
+static void ep0_out_start(void)
+{
+ u32 temp;
+
+ /* program transfer size*/
+ temp = 8 * 3;
+ /* program packet count*/
+ temp |= PKTCNT;
+ /* program setup packet count */
+ temp |= (3 << SUPCNT_SHIFT);
+ writel(temp, &dev_if->out_ep_regs[0]->doeptsiz);
+}
+
+/* should be called after set address is received */
+static void udc_set_addr_ctrl(u32 address)
+{
+ u32 dcfg;
+
+ dcfg = readl(&dev_if->dev_global_regs->dcfg);
+ dcfg &= ~DEVADDRMSK;
+ dcfg |= address << DEVADDR_SHIFT;
+ writel(dcfg, &dev_if->dev_global_regs->dcfg);
+
+ usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0);
+}
+
+/* should be called after set configuration is received */
+static void dwc_otg_bulk_out_activate(void)
+{
+ struct device_out_ep_regs *out_regs =
+ dev_if->out_ep_regs[UDC_OUT_ENDPOINT];
+ struct device_global_regs *dev_global_regs
+ = dev_if->dev_global_regs;
+ u32 doepctl, doeptsiz, daint;
+
+ daint = readl(&dev_global_regs->daintmsk);
+ daint |= 1 << (UDC_OUT_ENDPOINT + DAINTMASK_OUT_SHIFT);
+ writel(daint, &dev_global_regs->daintmsk);
+ doeptsiz = CONFIG_USBD_SERIAL_BULK_PKTSIZE;
+ doeptsiz |= (1 << PKTCNT_SHIFT);
+ writel(doeptsiz, &out_regs->doeptsiz);
+ doepctl = readl(&out_regs->doepctl);
+ doepctl &= ~DOEPCTL_MPSMSK;
+ doepctl &= ~EPTYPEMSK;
+ doepctl |= (CONFIG_USBD_SERIAL_BULK_PKTSIZE |
+ CNAK | EPENA | USBACTEP | DATA0PID
+ | (EPTYPE_BULK << EPTYPE_SHIFT));
+ writel(doepctl, &out_regs->doepctl);
+}
+
+/* should be called after set configuration is received */
+static void dwc_otg_bulk_in_activate(void)
+{
+ struct device_in_ep_regs *in_regs =
+ dev_if->in_ep_regs[UDC_IN_ENDPOINT];
+ struct device_global_regs *dev_global_regs
+ = dev_if->dev_global_regs;
+ u32 diepctl, daint;
+
+ daint = readl(&dev_global_regs->daintmsk);
+ daint |= 1 << (UDC_IN_ENDPOINT + DAINTMASK_IN_SHIFT);
+ writel(daint, &dev_global_regs->daintmsk);
+
+ diepctl = readl(&in_regs->diepctl);
+ diepctl &= ~DIEPCTL_MPSMSK;
+ diepctl &= ~EPTYPEMSK;
+ diepctl |= (CONFIG_USBD_SERIAL_BULK_PKTSIZE
+ | USBACTEP | DATA0PID
+ | (EPTYPE_BULK << EPTYPE_SHIFT));
+ writel(diepctl, &in_regs->diepctl);
+}
+
+static void dwc_otg_int_in_activate(void)
+{
+ struct device_in_ep_regs *in_regs =
+ dev_if->in_ep_regs[UDC_INT_ENDPOINT];
+ struct device_global_regs *dev_global_regs
+ = dev_if->dev_global_regs;
+ u32 diepctl, daint;
+
+ daint = readl(&dev_global_regs->daintmsk);
+ daint |= 1 << (UDC_INT_ENDPOINT + DAINTMASK_IN_SHIFT);
+ writel(daint, &dev_global_regs->daintmsk);
+
+ diepctl = readl(&in_regs->diepctl);
+ diepctl &= ~DIEPCTL_MPSMSK;
+ diepctl &= ~EPTYPEMSK;
+ diepctl |= (UDC_INT_PACKET_SIZE
+ | USBACTEP | DATA0PID
+ | (EPTYPE_INT << EPTYPE_SHIFT));
+ writel(diepctl, &in_regs->diepctl);
+}
+
+/* should be called after set configuration is received */
+static void udc_set_cfg_ctrl(u32 config)
+{
+ dwc_otg_bulk_out_activate();
+ dwc_otg_bulk_in_activate();
+ dwc_otg_int_in_activate();
+ usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
+}
+
+/* should be called to receive next packet */
+static void dwc_otg_bulk_out_enable(void)
+{
+ struct device_out_ep_regs *out_regs =
+ dev_if->out_ep_regs[UDC_OUT_ENDPOINT];
+ u32 doepctl, doeptsiz;
+
+ doeptsiz = CONFIG_USBD_SERIAL_BULK_PKTSIZE;
+ doeptsiz |= (1 << PKTCNT_SHIFT);
+ writel(doeptsiz, &out_regs->doeptsiz);
+ doepctl = readl(&out_regs->doepctl);
+ doepctl |= CNAK | EPENA;
+ writel(doepctl, &out_regs->doepctl);
+}
+
+/* This interrupt indicates that an OUT EP has a pending Interrupt. */
+
+static int dwc_otg_pcd_handle_out_ep_intr(void)
+{
+ u32 ep_intr;
+ u32 doepint;
+ u32 epnum = 0;
+ struct dwc_ep *dwc_ep;
+ struct device_out_ep_regs **out_ep_regs
+ = dev_if->out_ep_regs;
+
+ /* Read in the device interrupt bits */
+ ep_intr = dwc_otg_read_dev_all_out_ep_intr();
+ while (ep_intr) {
+ if (ep_intr & 0x1) {
+ dwc_ep = get_out_ep(epnum);
+ doepint = dwc_otg_read_doep_intr(dwc_ep);
+
+ /* Transfer complete */
+ if (doepint & XFERCOMPL) {
+ /* Clear xfercompl */
+ writel(XFERCOMPL, &out_ep_regs[epnum]->doepint);
+ if (!epnum)
+ ep0_out_start();
+ else if (epnum == UDC_OUT_ENDPOINT)
+ dwc_otg_bulk_out_enable();
+ }
+ /* Setup Phase Done (control EPs) */
+ if (doepint & SETUP) {
+ writel(SETUP, &out_ep_regs[epnum]->doepint);
+ handle_ep0(0);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1;
+ }
+ return 1;
+}
+
+/* This interrupt indicates that an IN EP has a pending Interrupt. */
+
+static int dwc_otg_pcd_handle_in_ep_intr(void)
+{
+ u32 ep_intr;
+ u32 diepint;
+ u32 epnum = 0;
+ struct dwc_ep *dwc_ep;
+ struct device_in_ep_regs **in_ep_regs
+ = dev_if->in_ep_regs;
+
+ /* Read in the device interrupt bits */
+ ep_intr = dwc_otg_read_dev_all_in_ep_intr();
+ while (ep_intr) {
+ if (ep_intr & 0x1) {
+ dwc_ep = get_in_ep(epnum);
+ diepint = dwc_otg_read_diep_intr(dwc_ep);
+
+ /* IN token received when txfifo empty */
+ if (diepint & INTKNTXFEMP) {
+ /* Clear xfercompl */
+ writel(INTKNTXFEMP,
+ &in_ep_regs[epnum]->diepint);
+ if (!epnum)
+ handle_ep0(1);
+ else if (epnum == UDC_IN_ENDPOINT)
+ dw_udc_epn_tx(dwc_ep);
+ }
+ }
+ epnum++;
+ ep_intr >>= 1;
+ }
+ return 1;
+}
+
+static void dwc_otg_flush_tx_fifo(const int num)
+{
+ struct core_global_regs *global_regs = dev_if->core_global_regs;
+ u32 val = 0;
+ int count = 0;
+
+ val = readl(&global_regs->grstctl);
+ val |= TXFFLSH;
+ val &= ~TXFNUM;
+ val |= (num << TXFNUM_SHIFT);
+ writel(val, &global_regs->grstctl);
+
+ do {
+ val = readl(&global_regs->grstctl);
+ if (++count > 10000)
+ break;
+ udelay(1);
+ } while (val & TXFFLSH);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+static void dwc_otg_flush_rx_fifo(void)
+{
+ struct core_global_regs *global_regs = dev_if->core_global_regs;
+ int count = 0;
+ u32 val = 0;
+
+ val = readl(&global_regs->grstctl);
+ val |= RXFFLSH;
+ writel(val, &global_regs->grstctl);
+
+ do {
+ val = readl(&global_regs->grstctl);
+ if (++count > 10000)
+ break;
+ udelay(1);
+ } while (val & RXFFLSH);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+/*
+ * This interrupt occurs when a USB Reset is detected. When the USB Reset
+ * Interrupt occurs the device state is set to DEFAULT and the EP0 state is set
+ * to IDLE.
+ *
+ */
+static int dwc_otg_pcd_handle_usb_reset_intr(void)
+{
+ u32 temp;
+ u32 i;
+ u32 gintmsk;
+ struct device_out_ep_regs **out_ep_regs
+ = dev_if->out_ep_regs;
+ struct device_global_regs *dev_global_regs
+ = dev_if->dev_global_regs;
+ struct core_global_regs *core_global_regs
+ = dev_if->core_global_regs;
+ /* Set NAK for all OUT EPs */
+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+ temp = readl(&out_ep_regs[i]->doepctl);
+ temp |= SNAK;
+ writel(temp, &out_ep_regs[i]->doepctl);
+ }
+
+ /* Flush the NP Tx FIFO */
+ dwc_otg_flush_tx_fifo(DWC_GRSTCTL_TXFNUM_ALL);
+ dwc_otg_flush_rx_fifo();
+ writel((1 << (DAINTMASK_IN_SHIFT + 0))
+ | (1 << (DAINTMASK_OUT_SHIFT + 0)),
+ &dev_global_regs->daintmsk);
+
+ writel(SETUPMSK | XFERCOMPLMSK | AHBERRMSK | EPDISABLEDMSK,
+ &dev_global_regs->doepmsk);
+
+ writel(INTKNTXFEMP, &dev_global_regs->diepmsk);
+
+ gintmsk = readl(&core_global_regs->gintmsk);
+ gintmsk |= GOUTNAKEFF;
+ writel(gintmsk, &core_global_regs->gintmsk);
+
+ /* program fifo size for ep0 */
+
+ writel(0x200, &core_global_regs->grxfsiz);
+
+ temp = readl(&dev_if->in_ep_regs[0]->diepctl);
+ temp &= 0xFFC3FFFF; /* TxFNumBF = 0, bits 25:22 */
+ writel(temp, &dev_if->in_ep_regs[0]->diepctl);
+
+ temp = readl(&core_global_regs->gnptxfsiz);
+
+ writel(0x2000000, &core_global_regs->gnptxfsiz);
+
+ /* Reset Device Address */
+ temp = readl(&dev_global_regs->dcfg);
+ temp &= ~DEVADDRMSK;
+ writel(temp, &dev_global_regs->dcfg);
+
+ /* setup EP0 to receive SETUP packets */
+ ep0_out_start();
+
+ /* Clear interrupt */
+ writel(USBRESET, &core_global_regs->gintsts);
+
+ UDCDBG("device reset in progess");
+ usbd_device_event_irq(udc_device, DEVICE_HUB_CONFIGURED, 0);
+ usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
+
+ return 1;
+}
+
+/*
+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
+ * IN for transmitting packets. It is normally called when the "Enumeration
+ * Done" interrupt occurs.
+ */
+static void dwc_otg_ep0_activate(void)
+{
+ u32 temp;
+ struct device_in_ep_regs *in_ep_regs = dev_if->in_ep_regs[0];
+ struct device_out_ep_regs *out_ep_regs = dev_if->out_ep_regs[0];
+
+ /* Read the Device Status and Endpoint 0 Control registers */
+ temp = readl(&in_ep_regs->diepctl);
+ temp &= ~MPSMSK0;
+ temp |= DWC_DEP0CTL_MPS_64;
+ writel(temp, &in_ep_regs->diepctl);
+
+ temp = readl(&out_ep_regs->doepctl);
+ /* Enable OUT EP for receive */
+ temp |= EPENA;
+ writel(temp, &out_ep_regs->doepctl);
+}
+
+/*
+ * Read the device status register and set the device speed in the
+ * data structure.
+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
+ */
+static int dwc_otg_pcd_handle_enum_done_intr(void)
+{
+ u32 gusbcfg;
+ struct core_global_regs *global_regs = dev_if->core_global_regs;
+ dwc_otg_ep0_activate();
+
+ gusbcfg = readl(&global_regs->gusbcfg);
+ gusbcfg &= ~USBTRDTIMMSK;
+ gusbcfg |= PHYIF_16BIT;
+ gusbcfg |= (9 << USBTRDTIM_SHIFT);
+ writel(gusbcfg, &global_regs->gusbcfg);
+ /* Clear interrupt */
+ writel(ENUMDONE, &global_regs->gintsts);
+
+ return 1;
+}
+
+static u32 dwc_otg_read_core_intr(void)
+{
+ return readl(&dev_if->core_global_regs->gintsts) &
+ readl(&dev_if->core_global_regs->gintmsk);
+}
+
+static void dwc_otg_init(const void *reg_base)
+{
+ struct dwc_pcd *pcd = &dev_if->pcd;
+ u32 offset;
+ u32 i;
+
+ dev_if->core_global_regs = (struct core_global_regs *) reg_base;
+ dev_if->dev_global_regs = (struct device_global_regs *) ((u32)reg_base +
+ DWC_DEV_GLOBAL_REG_OFFSET);
+
+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+ offset = i * DWC_EP_REG_OFFSET;
+
+ dev_if->in_ep_regs[i] = (struct device_in_ep_regs *)
+ ((u32)reg_base + DWC_DEV_IN_EP_REG_OFFSET + offset);
+
+ dev_if->out_ep_regs[i] = (struct device_out_ep_regs *)
+ ((u32)reg_base + DWC_DEV_OUT_EP_REG_OFFSET + offset);
+ }
+
+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+ dev_if->data_fifo[i] =
+ (u32 *) ((u32)reg_base + DWC_OTG_DATA_FIFO_OFFSET +
+ (i * DWC_OTG_DATA_FIFO_SIZE));
+ }
+
+ dev_if->speed = 0; /* unknown */
+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+ pcd->in_ep[i].num = i;
+ pcd->out_ep[i].num = i;
+ }
+}
+
+/*
+ * This function initializes the DWC_otg controller registers and prepares the
+ * core for device mode
+ */
+static void dwc_otg_core_init(void)
+{
+ struct core_global_regs *global_regs = dev_if->core_global_regs;
+ u32 ahbcfg, gintmsk, usbcfg;
+ /* Step 1: Program the GAHBCFG Register. */
+ ahbcfg = DWC_NPTXEMPTYLVL_EMPTY | DWC_PTXEMPTYLVL_EMPTY;
+ writel(ahbcfg, &global_regs->gahbcfg);
+
+ /* Step 2: write usbcfg regs*/
+ usbcfg = readl(&global_regs->gusbcfg);
+ usbcfg |= SRPCAP | HNPCAP;
+ writel(usbcfg, &global_regs->gusbcfg);
+
+ /* step3: write int_msk reg*/
+ gintmsk = USBRESET | ENUMDONE | RXSTSQLVL | OUTEPINTR | INEPINTR;
+ writel(gintmsk, &global_regs->gintmsk);
+}
+
+/* Switch on the UDC */
+static void usbotg_init(void)
+{
+ udc_device = NULL;
+ dwc_otg_init((void *)CONFIG_SYS_USBD_BASE);
+
+ /* Initialize the DWC_otg core. */
+ dwc_otg_core_init();
+
+}
+
+void udc_irq(void)
+{
+ u32 status;
+
+ status = dwc_otg_read_core_intr();
+ while (status) {
+ if (status & USBRESET)
+ dwc_otg_pcd_handle_usb_reset_intr();
+ if (status & ENUMDONE)
+ dwc_otg_pcd_handle_enum_done_intr();
+ if (status & RXSTSQLVL)
+ dwc_otg_pcd_handle_rx_status_q_level_intr();
+ if (status & OUTEPINTR)
+ dwc_otg_pcd_handle_out_ep_intr();
+ if (status & INEPINTR)
+ dwc_otg_pcd_handle_in_ep_intr();
+ status = dwc_otg_read_core_intr();
+ }
+
+}
+
+void udc_set_nak(int epid)
+{
+ writel(readl(&dev_if->out_ep_regs[epid]->doepctl) | SNAK,
+ &dev_if->out_ep_regs[epid]->doepctl);
+ writel(readl(&dev_if->in_ep_regs[epid]->diepctl) | SNAK,
+ &dev_if->in_ep_regs[epid]->diepctl);
+}
+
+void udc_unset_nak(int epid)
+{
+ writel(readl(&dev_if->out_ep_regs[epid]->doepctl) | CNAK,
+ &dev_if->out_ep_regs[epid]->doepctl);
+ writel(readl(&dev_if->in_ep_regs[epid]->diepctl) | CNAK,
+ &dev_if->in_ep_regs[epid]->diepctl);
+}
+
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
+{
+ udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
+ return 0;
+}
+
+static void udc_enable(struct usb_device_instance *device)
+{
+ struct dwc_pcd *pcd = &dev_if->pcd;
+
+ UDCDBGA("enable device %p, status %d", device, device->status);
+
+ /* Save the device structure pointer */
+ udc_device = device;
+
+ /* Setup ep0 urb */
+ if (!ep0_urb) {
+ ep0_urb =
+ usbd_alloc_urb(udc_device,
+ udc_device->bus->endpoint_array);
+ pcd->req =
+ (struct usb_device_request *)&ep0_urb->device_request;
+ pcd->ep0.xfer_buff = (u8 *)ep0_urb->buffer;
+ } else {
+ serial_printf("udc_enable: ep0_urb already allocated %p\n",
+ ep0_urb);
+ }
+}
+
+void udc_connect(void)
+{
+ struct device_global_regs *dev_regs = dev_if->dev_global_regs;
+ u32 dcfg;
+
+ /* remove soft disconnect */
+ dcfg = readl(&dev_regs->dctl);
+ dcfg &= ~SFTDISCON;
+ writel(dcfg, &dev_regs->dctl);
+}
+
+void udc_disconnect(void)
+{
+ struct device_global_regs *dev_regs = dev_if->dev_global_regs;
+ u32 dcfg;
+
+ /* soft disconnect */
+ dcfg = readl(&dev_regs->dctl);
+ dcfg |= SFTDISCON;
+ writel(dcfg, &dev_regs->dctl);
+ udelay(150);
+}
+
+void udc_startup_events(struct usb_device_instance *device)
+{
+ /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
+ usbd_device_event_irq(device, DEVICE_INIT, 0);
+
+ /*
+ * The DEVICE_CREATE event puts the USB device in the state
+ * STATE_ATTACHED.
+ */
+ usbd_device_event_irq(device, DEVICE_CREATE, 0);
+
+ /*
+ * Some USB controller driver implementations signal
+ * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
+ * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
+ * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
+ * The DW USB client controller has the capability to detect when the
+ * USB cable is connected to a powered USB bus, so we will defer the
+ * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
+ */
+
+ udc_enable(device);
+
+}
+
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *endpoint)
+{
+ /*
+ * Nothing to do here. Hob of this function has laready been
+ * done during init.
+ */
+}
+
+int is_usbd_high_speed(void)
+{
+ struct device_global_regs *dev_regs = dev_if->dev_global_regs;
+ u32 dsts;
+
+ dsts = readl(&dev_regs->dsts);
+ dsts &= ENUMSPDMSK;
+ if (dsts == DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+ return 1;
+ else
+ return 0;
+}
+
+int udc_init(void)
+{
+#if defined(CONFIG_DW_OTG_PHYINIT)
+ udc_phy_init();
+#endif
+ udc_disconnect();
+ usbotg_init();
+ return 0;
+}
diff --git a/include/usb/designware_otg.h b/include/usb/designware_otg.h
new file mode 100644
index 0000000..98d016e
--- /dev/null
+++ b/include/usb/designware_otg.h
@@ -0,0 +1,500 @@
+/*
+ * (C) Copyright 2011
+ * Pratyush Anand, ST Micoelectronics, pratyush.anand at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DW_OTG_H
+#define __DW_OTG_H
+
+#include "usbdevice.h"
+
+/* USBTTY definitions */
+#define EP0_MAX_PACKET_SIZE 64
+#define UDC_INT_ENDPOINT 1
+#define UDC_INT_PACKET_SIZE 64
+#define UDC_OUT_ENDPOINT 2
+#define UDC_BULK_PACKET_SIZE 512
+#if defined(CONFIG_USBD_HS)
+#define UDC_BULK_HS_PACKET_SIZE 512
+#endif
+#define UDC_IN_ENDPOINT 3
+#define UDC_OUT_PACKET_SIZE 64
+#define UDC_IN_PACKET_SIZE 64
+
+/* UDC endpoint definitions */
+#define UDC_EP0 0
+#define UDC_EP1 1
+#define UDC_EP2 2
+#define UDC_EP3 3
+
+/* OTG Register Definitions */
+
+/*
+ * The application interfaces with the HS OTG core by reading from and
+ * writing to the Control and Status Register (CSR) space through the
+ * AHB Slave interface. These registers are 32 bits wide, and the
+ * addresses are 32-bit-block aligned.
+ * CSRs are classified as follows:
+ * - Core Global Registers
+ * - Device Mode Registers
+ * - Device Global Registers
+ * - Device Endpoint Specific Registers
+ * - Host Mode Registers
+ * - Host Global Registers
+ * - Host Port CSRs
+ * - Host Channel Specific Registers
+ *
+ * Only the Core Global registers can be accessed in both Device and
+ * Host modes. When the HS OTG core is operating in one mode, either
+ * Device or Host, the application must not access registers from the
+ * other mode. When the core switches from one mode to another, the
+ * registers in the new mode of operation must be reprogrammed as they
+ * would be after a power-on reset.
+ */
+
+/*
+ * DWC_otg Core registers. The core_global_regs structure defines the
+ * size and relative field offsets for the Core Global registers.
+ */
+struct core_global_regs {
+ /* OTG Control and Status Register. Offset: 000h */
+ u32 gotgctl;
+ /* OTG Interrupt Register. Offset: 004h */
+ u32 gotgint;
+ /* Core AHB Configuration Register. Offset: 008h */
+ u32 gahbcfg;
+
+#define DWC_GLBINTRMASK 0x0001
+#define DWC_DMAENABLE 0x0020
+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
+#define DWC_PTXEMPTYLVL_EMPTY 0x0100
+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
+
+ /* Core USB Configuration Register. Offset: 00Ch */
+ u32 gusbcfg;
+#define PHYIF_16BIT (1 << 3)
+#define SRPCAP (1 << 8)
+#define HNPCAP (1 << 9)
+#define TERM_SEL_DL_PULSE (1 << 22)
+#define USBTRDTIM_SHIFT 10
+#define USBTRDTIMMSK (0xF << USBTRDTIM_SHIFT)
+ /* Core Reset Register. Offset: 010h */
+ u32 grstctl;
+#define DWC_GRSTCTL_TXFNUM_ALL 0x10
+#define CSFTRST (1 << 0)
+#define INTKNQFLSH (1 << 3)
+#define RXFFLSH (1 << 4)
+#define TXFFLSH (1 << 5)
+#define TXFNUM_SHIFT 6
+#define TXFNUM (0x1F << TXFNUM_SHIFT)
+#define AHBIDLE ((u32)1 << 31)
+ /* Core Interrupt Register. Offset: 014h */
+ u32 gintsts;
+#define RXSTSQLVL (1 << 4)
+#define NPTXFEMPTY (1 << 5)
+#define GOUTNAKEFF (1 << 7)
+#define USBRESET (1 << 12)
+#define ENUMDONE (1 << 13)
+#define INEPINTR (1 << 18)
+#define OUTEPINTR (1 << 19)
+ /* Core Interrupt Mask Register. Offset: 018h */
+ u32 gintmsk;
+ /*
+ * Receive Status Queue Read Register
+ * (Read Only) Offset: 01Ch
+ */
+ u32 grxstsr;
+ /*
+ * Receive Status Queue Read & POP Register
+ * (Read Only) Offset: 020h
+ */
+ u32 grxstsp;
+#define DWC_STS_DATA_UPDT 0x2 /* OUT Data Packet */
+#define DWC_STS_XFER_COMP 0x3 /* OUT Data Transfer Complete */
+#define DWC_DSTS_GOUT_NAK 0x1 /* Global OUT NAK */
+#define DWC_DSTS_SETUP_COMP 0x4 /* Setup Phase Complete */
+#define DWC_DSTS_SETUP_UPDT 0x6 /* SETUP Packet */
+#define EPNUM_SHIFT 0
+#define EPNUMMSK (0xF << EPNUM_SHIFT)
+#define BCNT_SHIFT 4
+#define BCNTMSK (0x7FF << BCNT_SHIFT)
+#define PKTSTS_SHIFT 17
+#define PKTSTSMSK (0xF << PKTSTS_SHIFT)
+ /* Receive FIFO Size Register. Offset: 024h */
+ u32 grxfsiz;
+#define dwc_param_dev_rx_fifo_size_default 1064
+ /* Non Periodic Transmit FIFO Size Register. Offset: 028h */
+ u32 gnptxfsiz;
+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
+ /*
+ * Non Periodic Transmit FIFO/Queue Status Register
+ * (Read Only). Offset: 02Ch
+ */
+ u32 gnptxsts;
+#define NPTXQSPCAVAIL_SHIFT 16
+#define NPTXQSPCAVAILMSK (0xFF << NPTXQSPCAVAIL_SHIFT)
+#define NPTXFSPCAVAIL_SHIFT 0
+#define NPTXFSPCAVAILMSK (0xFFFF << NPTXFSPCAVAIL_SHIFT)
+ /* I2C Access Register. Offset: 030h */
+ u32 gi2cctl;
+ /* PHY Vendor Control Register. Offset: 034h */
+ u32 gpvndctl;
+ /* General Purpose Input/Output Register. Offset: 038h */
+ u32 ggpio;
+ /* User ID Register. Offset: 03Ch */
+ u32 guid;
+ /* Synopsys ID Register (Read Only). Offset: 040h */
+ u32 gsnpsid;
+ /* User HW Config1 Register (Read Only). Offset: 044h */
+ u32 ghwcfg1;
+ /* User HW Config2 Register (Read Only). Offset: 048h */
+
+ u32 ghwcfg2;
+#define DWC_SLAVE_ONLY_ARCH 0
+#define DWC_EXT_DMA_ARCH 1
+#define DWC_INT_DMA_ARCH 2
+
+#define DWC_MODE_HNP_SRP_CAPABLE 0
+#define DWC_MODE_SRP_ONLY_CAPABLE 1
+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
+#define DWC_MODE_SRP_CAPABLE_DEVICE 3
+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
+#define DWC_MODE_SRP_CAPABLE_HOST 5
+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
+#define DYNAMIC_FIFO (1 << 19)
+#define NUM_DEV_EP_SHIFT 10
+#define NUM_DEV_EP (0xF << NUM_DEV_EP_SHIFT)
+#define HSPHYTYPE_SHIFT 6
+#define HSPHYTYPEMSK (3 << HSPHYTYPE_SHIFT)
+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
+#define TKNQDEPTH_SHIFT 26
+#define TKNQDEPTHMSK (0x1F << TKNQDEPTH_SHIFT)
+
+ /* User HW Config3 Register (Read Only). Offset: 04Ch */
+ u32 ghwcfg3;
+#define DFIFO_DEPTH_SHIFT 16
+#define DFIFO_DEPTH ((u32)0xFFFF << DFIFO_DEPTH_SHIFT)
+ /* User HW Config4 Register (Read Only). Offset: 050h */
+ u32 ghwcfg4;
+#define NUM_DEV_PERIO_IN_EP_SHIFT 0
+#define NUM_DEV_PERIO_IN_EP (0xF << NUM_DEV_PERIO_IN_EP_SHIFT)
+#define DED_FIFO_EN (1 << 25)
+#define NUM_IN_EPS_SHIFT 26
+#define NUM_IN_EPS (0xF << NUM_IN_EPS_SHIFT)
+#define UTMI_PHY_DATA_WIDTH_SHIFT 14
+#define UTMI_PHY_DATA_WIDTH (0x3 << UTMI_PHY_DATA_WIDTH_SHIFT)
+ /* Reserved Offset: 054h-0FFh */
+ u32 reserved[43];
+ /* Host Periodic Transmit FIFO Size Register. Offset: 100h */
+ u32 hptxfsiz;
+
+ /*
+ * Device Periodic Transmit FIFO#n Register, if dedicated fifos are
+ * disabled. Otherwise Device Transmit FIFO#n Register.
+ *
+ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15)
+ */
+ u32 dptxfsiz_dieptxf[15];
+#define dwc_param_dev_tx_fifo_size_default 256
+#define dwc_param_dev_perio_tx_fifo_size_default 256
+};
+
+/*
+ * Device Global Registers. Offsets 800h-BFFh
+ *
+ * The following structures define the size and relative field offsets for the
+ * Device Mode Registers.
+ *
+ * These registers are visible only in Device mode and must not be accessed in
+ * Host mode, as the results are unknown.
+ */
+struct device_global_regs { /* CONFIG_DWC_OTG_REG_LE */
+ /* Device Configuration Register. Offset: 800h */
+ u32 dcfg;
+#define DWC_DCFG_FRAME_INTERVAL_80 0
+#define DWC_DCFG_FRAME_INTERVAL_85 1
+#define DWC_DCFG_FRAME_INTERVAL_90 2
+#define DWC_DCFG_FRAME_INTERVAL_95 3
+#define DWC_DCFG_FRAME_INTERVAL_MASK 3
+#define PERFRINT_SHIFT 11
+#define DEVSPDMSK (0x3 << 0)
+#define DEVADDR_SHIFT 4
+#define DEVADDRMSK (0x7F << DEVADDR_SHIFT)
+#define NZSTSOUTHSHK (1 << 2)
+ /* Device Control Register. Offset: 804h */
+ u32 dctl;
+#define RMTWKUPSIG (1 << 0)
+#define SFTDISCON (1 << 1)
+#define CGNPINNAK (1 << 7)
+ /* Device Status Register (Read Only). Offset: 808h */
+ u32 dsts;
+#define ENUMSPD_SHIFT 1
+#define ENUMSPDMSK (3 << ENUMSPD_SHIFT)
+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
+ /* Reserved. Offset: 80Ch */
+ u32 unused;
+ /* Device IN Endpoint Common Interrupt Mask Register. Offset: 810h */
+ u32 diepmsk;
+#define TIMEOUTMSK (1 << 3)
+#define INTKNTXFEMP (1 << 4)
+#define INTKNEPMISMSK (1 << 5)
+#define INEPNAKEFFMSK (1 << 6)
+#define TXFIFOUNDRN (1 << 8)
+ /* Device OUT Endpoint Common Interrupt Mask Register. Offset: 814h */
+ u32 doepmsk;
+#define XFERCOMPLMSK (1 << 0)
+#define EPDISABLEDMSK (1 << 1)
+#define AHBERRMSK (1 << 2)
+#define SETUPMSK (1 << 3)
+#define INTKNTXFEMPMSK (1 << 4)
+ /* Device All Endpoints Interrupt Register. Offset: 818h */
+ u32 daint;
+ /* Device All Endpoints Interrupt Mask Register. Offset: 81Ch */
+ u32 daintmsk;
+#define DAINTMASK_IN_SHIFT 0
+#define DAINTMASK_OUT_SHIFT 16
+ /* Device IN Token Queue Read Register-1 (Read Only). Offset: 820h */
+ u32 dtknqr1;
+#define EPTK0_5_SHIFT 8
+#define EPTK0_5MSK ((u32)0xFFFFFF << EPTK0_5_SHIFT)
+#define INTKNWPTR_SHIFT 0
+#define INTKNWPTRMSK ((u32)0x1F << INTKNWPTR_SHIFT)
+ /* Device IN Token Queue Read Register-2 (Read Only). Offset: 824h */
+ u32 dtknqr2;
+ /* Device VBUS discharge Register. Offset: 828h */
+ u32 dvbusdis;
+ /* Device VBUS Pulse Register. Offset: 82Ch */
+ u32 dvbuspulse;
+ /* Device IN Token Queue Read Register-3 (Read Only). Offset: 830h */
+ u32 dtknqr3_dthrctl;
+ /* Device IN Token Queue Read Register-4 (Read Only). Offset: 834h */
+ u32 dtknqr4_fifoemptymsk;
+};
+/*
+ * Device Logical IN Endpoint-Specific Registers. Offsets 900h-AFCh
+ *
+ * There will be one set of endpoint registers per logical endpoint implemented.
+ *
+ * These registers are visible only in Device mode and must not be accessed in
+ * Host mode, as the results are unknown.
+ */
+struct device_in_ep_regs {
+ /*
+ * Device IN Endpoint Control Register.
+ * Offset:900h + (ep_num * 20h) + 00h
+ */
+ u32 diepctl;
+#define EPENA ((u32)1 << 31)
+#define EPDIS (1 << 30)
+#define SNAK (1 << 27)
+#define CNAK (1 << 26)
+#define SSTALL (1 << 21)
+#define MPS_SHIFT 0
+#define MPSMSK0 (3 << MPS_SHIFT)
+#define DWC_DEP0CTL_MPS_64 0
+#define DWC_DEP0CTL_MPS_32 1
+#define DWC_DEP0CTL_MPS_16 2
+#define DWC_DEP0CTL_MPS_8 3
+#define DIEPCTL_MPSMSK (0x7FF << MPS_SHIFT)
+ /* Reserved. Offset:900h + (ep_num * 20h) + 04h */
+ u32 reserved04;
+ /*
+ * Device IN Endpoint Interrupt Register.
+ * Offset:900h + (ep_num * 20h) + 08h
+ */
+ u32 diepint;
+#define TXFEMP (1 << 7)
+#define INTKNTXFEMP (1 << 4)
+#define XFERCOMPL (1 << 0)
+ /* Reserved. Offset:900h + (ep_num * 20h) + 0Ch */
+ u32 reserved0C;
+ /* Device IN Endpoint Transfer Size Register.
+ * Offset:900h + (ep_num * 20h) + 10h
+ */
+ u32 dieptsiz;
+#define PKTCNT_SHIFT 19
+ /*
+ * Device IN Endpoint DMA Address Register.
+ * Offset:900h + (ep_num * 20h) + 14h
+ */
+ u32 diepdma;
+ /* Reserved.
+ * Offset:900h + (ep_num * 20h) + 18h - 900h + (ep_num * 20h) + 1Ch
+ */
+ u32 dtxfsts;
+ /*
+ * Reserved.
+ * Offset:900h + (ep_num * 20h) + 1Ch - 900h + (ep_num * 20h) + 1Ch
+ */
+ u32 reserved18;
+};
+
+/*
+ * Device Logical OUT Endpoint-Specific Registers. Offsets: B00h-CFCh
+ *
+ * There will be one set of endpoint registers per logical endpoint implemented.
+ *
+ * These registers are visible only in Device mode and must not be accessed in
+ * Host mode, as the results are unknown.
+ */
+struct device_out_ep_regs {
+ /*
+ * Device OUT Endpoint Control Register.
+ * Offset:B00h + (ep_num * 20h) + 00h
+ */
+ u32 doepctl;
+#define DOEPCTL_MPSMSK 0x7FF
+#define USBACTEP (1 << 15)
+#define EPTYPE_SHIFT 18
+#define EPTYPEMSK (0x3 << EPTYPE_SHIFT)
+#define EPTYPE_BULK 0x2
+#define EPTYPE_INT 0x3
+#define DATA0PID (1 << 28)
+#define DATA1PID (1 << 29)
+#define DPIDMSK (1 << 16)
+ /*
+ * Device OUT Endpoint Frame number Register.
+ * Offset: B00h + (ep_num * 20h) + 04h
+ */
+ u32 doepfn;
+ /*
+ * Device OUT Endpoint Interrupt Register.
+ * Offset:B00h + (ep_num * 20h) + 08h
+ */
+ u32 doepint;
+#define XFERCOMPL (1 << 0)
+#define EPDISBLD (1 << 1)
+#define AHBERR (1 << 2)
+#define SETUP (1 << 3)
+ /* Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */
+ u32 reserved0C;
+ /*
+ * Device OUT Endpoint Transfer Size Register.
+ * Offset: B00h + (ep_num * 20h) + 10h
+ */
+ u32 doeptsiz;
+#define XFERSIZE_SHIFT 0
+#define XFERSIZEMSK 0x3F
+#define PKTCNT_SHIFT 19
+#define PKTCNT (3 << 19)
+#define SUPCNT_SHIFT 29
+#define SUPCNTMSK (3 << SUPCNT_SHIFT)
+ /*
+ * Device OUT Endpoint DMA Address Register.
+ * Offset:B00h + (ep_num * 20h) + 14h
+ */
+ u32 doepdma;
+ /*
+ * Reserved.
+ * Offset:B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch
+ */
+ u32 unused[2];
+};
+#define MAX_EPS_CHANNELS 4
+
+/*
+ * The dwc_ep structure represents the state of a single endpoint when acting in
+ * device mode. It contains the data items needed for an endpoint to be
+ * activated and transfer packets.
+ */
+struct dwc_ep {
+ /* EP number used for register address lookup */
+ u8 num;
+ /* pointer to the transfer buffer */
+ u8 *xfer_buff;
+ /* Number of bytes to transfer */
+ u32 xfer_len;
+};
+
+/*
+ * DWC_otg PCD Structure.
+ * This structure encapsulates the data for the dwc_otg PCD.
+ */
+struct dwc_pcd {
+ struct usb_device_request *req;
+ /* Array of EPs. */
+ struct dwc_ep ep0;
+ /* Array of IN EPs. */
+ struct dwc_ep in_ep[MAX_EPS_CHANNELS];
+ /* Array of OUT EPs. */
+ struct dwc_ep out_ep[MAX_EPS_CHANNELS];
+};
+
+/*
+ * The device_if structure contains information needed to manage the DWC_otg
+ * controller acting in device mode. It represents the programming view of the
+ * device-specific aspects of the controller.
+ */
+struct device_if {
+ struct core_global_regs *core_global_regs;
+ /* Common configuration information */
+
+ /* Device Global Registers starting@offset 800h */
+ struct device_global_regs *dev_global_regs;
+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
+
+ /* Device Logical IN Endpoint-Specific Registers 900h-AFCh */
+ struct device_in_ep_regs *in_ep_regs[MAX_EPS_CHANNELS];
+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
+#define DWC_EP_REG_OFFSET 0x20
+
+ /* Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
+ struct device_out_ep_regs *out_ep_regs[MAX_EPS_CHANNELS];
+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
+
+ /* Push/pop addresses for endpoints or host channels.*/
+ u32 *data_fifo[MAX_EPS_CHANNELS];
+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
+
+ struct dwc_pcd pcd;
+ int speed;
+};
+
+
+/* Function declarations */
+
+void phy_init(void);
+void udc_irq(void);
+
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+int udc_init(void);
+/* void udc_enable(struct usb_device_instance *device);*/
+void udc_disable(void);
+void udc_connect(void);
+void udc_disconnect(void);
+#if defined(CONFIG_DW_OTG_PHYINIT)
+void udc_phy_init(void);
+#endif
+void udc_startup_events(struct usb_device_instance *device);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *endpoint);
+
+#endif /* __DW_OTG_H */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [SPEAr Fixes PATCH 11/11] spear3xx: FIX: Enable access to memory for spear310 and spear320
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
` (8 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 10/11] spear: Enable ehci support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
9 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
The memory access to RAS is necessary for the operation of the peripherals
instantiated inside RAS. Enable this clock to make macb work
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 5 +++++
arch/arm/include/asm/arch-spear/misc.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 59655f5..8d3472b 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -94,6 +94,11 @@ int arch_cpu_init(void)
writel(periph1_clken, &misc_p->periph1_clken);
+#if defined(CONFIG_SOC_SPEAR310) || defined(CONFIG_SOC_SPEAR320)
+ writel(readl(&misc_p->amem_cfg_ctrl) | MISC_AMEM_CLKENB,
+ &misc_p->amem_cfg_ctrl);
+#endif
+
/* Early driver initializations */
#if defined(CONFIG_ST_SMI)
smi_init();
diff --git a/arch/arm/include/asm/arch-spear/misc.h b/arch/arm/include/asm/arch-spear/misc.h
index bb97650..266897e 100644
--- a/arch/arm/include/asm/arch-spear/misc.h
+++ b/arch/arm/include/asm/arch-spear/misc.h
@@ -157,6 +157,9 @@ struct misc_regs {
#define MISC_PRISOCID_SHFT 16
#define MISC_SECSOCID_SHFT 8
+/* amem_cfg_ctrl */
+#define MISC_AMEM_CLKENB 0x00000001
+
/* synth_clk */
#define MISC_SYNTH23 0x00020003
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 11/19] usb/host/ehci: Add support for EHCI on spear
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (7 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 10/19] usb/gadget/designware_otg: Add support for designware otg Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 12/19] usbtty: adapt buffers for large packet support Vipin Kumar
` (7 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
Add EHCI support for spear boards
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-spear.c | 59 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100644 drivers/usb/host/ehci-spear.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6c94794..9a6f982 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
new file mode 100644
index 0000000..f99bd1f
--- /dev/null
+++ b/drivers/usb/host/ehci-spear.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2010
+ * Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>.
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <usb.h>
+#include "ehci.h"
+#include <asm/arch/hardware.h>
+
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ *hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(int index)
+{
+ return 0;
+}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 12/19] usbtty: adapt buffers for large packet support
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (8 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 11/19] usb/host/ehci: Add support for EHCI on spear Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 13/19] net/macb: Add arch specific routine to get mdio control Vipin Kumar
` (6 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
From: Shiraz Hashim <shiraz.hashim@st.com>
Increase buffer sizes at driver and tty level to accommodate kermit
large packet support.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
drivers/serial/usbtty.c | 2 +-
include/usbdevice.h | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index e47cb9a..148d1a6 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -63,7 +63,7 @@
/*
* Buffers to hold input and output data
*/
-#define USBTTY_BUFFER_SIZE 256
+#define USBTTY_BUFFER_SIZE 2048
static circbuf_t usbtty_input;
static circbuf_t usbtty_output;
diff --git a/include/usbdevice.h b/include/usbdevice.h
index 3edaf8b..7037efd 100644
--- a/include/usbdevice.h
+++ b/include/usbdevice.h
@@ -475,7 +475,9 @@ typedef struct urb_link {
* function driver to inform it that data has arrived.
*/
-#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
+/* in linux we'd malloc this, but in u-boot we prefer static data */
+#define URB_BUF_SIZE 512
+
struct urb {
struct usb_endpoint_instance *endpoint;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 13/19] net/macb: Add arch specific routine to get mdio control
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (9 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 12/19] usbtty: adapt buffers for large packet support Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue Vipin Kumar
` (5 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
From: Shiraz Hashim <shiraz.hashim@st.com>
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently their is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
drivers/net/macb.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0e1ced7..ac25b52 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -165,6 +165,13 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
return MACB_BFEXT(DATA, frame);
}
+static void __def_arch_get_mdio_control(const char *name)
+{
+ return;
+}
+int arch_get_mdio_control(const char *name)
+ __attribute__((weak, alias("__def_arch_get_mdio_control")));
+
#if defined(CONFIG_CMD_MII)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
@@ -175,6 +182,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
if ( macb->phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
*value = macb_mdio_read(macb, reg);
return 0;
@@ -188,6 +196,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
if ( macb->phy_addr != phy_adr )
return -1;
+ arch_get_mdio_control(devname);
macb_mdio_write(macb, reg, value);
return 0;
@@ -379,6 +388,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
+ arch_get_mdio_control(netdev->name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb)) {
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (10 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 13/19] net/macb: Add arch specific routine to get mdio control Vipin Kumar
@ 2012-11-02 17:39 ` Vipin Kumar
2013-02-03 11:19 ` Albert ARIBAUD
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 15/19] misc/crypto: Add support for C3 Vipin Kumar
` (4 subsequent siblings)
16 siblings, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:39 UTC (permalink / raw)
To: u-boot
From: Shiraz Hashim <shiraz.hashim@st.com>
It is observed on SPEAr320S RMII#1 interface that on transmitting
packets the MAC dma hangs randomly and constantly showing busy tx-go
state.
It comes out if this situation only when Transmission is disabled and
enabled again.
Since it happens randomly and u-boot doesn't require high performance we
disable TE and re-enable it on each transmission. We also change number
of transmit descriptor to 1 as we would not require more than it, further
it would not alter GMAC notion of transmit descriptor start queue as it
always point to same descriptor.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index ac25b52..17bad33 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -55,7 +55,7 @@
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
-#define CONFIG_SYS_MACB_TX_RING_SIZE 16
+#define CONFIG_SYS_MACB_TX_RING_SIZE 1
#define CONFIG_SYS_MACB_TX_TIMEOUT 1000
#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
@@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
barrier();
- macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
+ /*
+ * Due to issues on SPEAr320 RMII, disable TE first so that
+ * controller can come out if it is hanged during transmission
+ */
+ macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
+ macb_writel(macb, NCR, macb_readl(macb, NCR) |
+ MACB_BIT(TE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
@@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
}
}
+static void macb_reset_hw(struct macb_device *bp)
+{
+ /* Make sure we have the write buffer for ourselves */
+ barrier();
+ /*
+ * Disable RX and TX (XXX: Should we halt the transmission
+ * more gracefully?) and we should not close the mdio port
+ */
+ macb_writel(bp, NCR, 0);
+
+ /* Clear the stats registers (XXX: Update stats first?) */
+ macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
+
+ /* keep the mdio port , otherwise other eth will not work */
+ macb_writel(bp, NCR, MACB_BIT(MPE));
+
+ /* Clear all status flags */
+ macb_writel(bp, TSR, ~0UL);
+ macb_writel(bp, RSR, ~0UL);
+
+ /* Disable all interrupts */
+ macb_writel(bp, IDR, ~0UL);
+ macb_readl(bp, ISR);
+}
+
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
@@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
tsr = macb_readl(macb, TSR);
} while (tsr & MACB_BIT(TGO));
- /* Disable TX and RX, and clear statistics */
- macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
+ macb_reset_hw(macb);
}
static int macb_write_hwaddr(struct eth_device *dev)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 15/19] misc/crypto: Add support for C3
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (11 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue Vipin Kumar
@ 2012-11-02 17:40 ` Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 16/19] armv7/ltimer: Add support for local timer on armv7 cpus Vipin Kumar
` (3 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:40 UTC (permalink / raw)
To: u-boot
C3 is a cryptographic controller which is used by the SPL when DDR ECC support
is enabled.
Basically, the DDR ECC feature requires the initialization of ECC values before
the DDR can actually be used. To accomplish this, the complete on board DDR is
initialized with zeroes. This initialization can be done using
* CPU
* CPU (with Dcache enabled)
* C3
The current SPL code uses C3 because the initialization using the CPU is slow
and we do not have enough memory in SPL to initialize page tables required to
enable MMU and Dcache
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/include/asm/arch-spear13xx/c3.h | 63 ++++++++++++++++
drivers/misc/Makefile | 1 +
drivers/misc/c3.c | 122 +++++++++++++++++++++++++++++++
3 files changed, 186 insertions(+)
create mode 100644 arch/arm/include/asm/arch-spear13xx/c3.h
create mode 100644 drivers/misc/c3.c
diff --git a/arch/arm/include/asm/arch-spear13xx/c3.h b/arch/arm/include/asm/arch-spear13xx/c3.h
new file mode 100644
index 0000000..541d702
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/c3.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2012
+ * ST Micoelectronics Pvt. Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MISC_C3_
+#define _MISC_C3_
+
+#include <asm/arch/hardware.h>
+
+#define C3_HIF_OFF 0x400 /* master interface registers */
+
+#define C3_INT_MEM_BASE_ADDR (CONFIG_SYS_C3_BASE + 0x400)
+#define C3_HIF_MBAR (C3_INT_MEM_BASE_ADDR + 0x304)
+ #define C3_LOCAL_MEM_ADDR 0xF0000000
+#define C3_HIF_MCR (C3_INT_MEM_BASE_ADDR + 0x308)
+ #define C3_HIF_MCR_ENB_INT_MEM 0x01
+#define C3_HIF_MAAR (C3_INT_MEM_BASE_ADDR + 0x310)
+#define C3_HIF_MADR (C3_INT_MEM_BASE_ADDR + 0x314)
+
+/* ID0 Registers definition */
+#define C3_ID0_SCR (CONFIG_SYS_C3_BASE + 0x1000)
+ #define C3_ID0_SCR_RST (1 << 16)
+#define C3_ID0_IP (CONFIG_SYS_C3_BASE + 0x1000 + 0x10)
+ #define C3_ID0_DEF_RDY_VAL 0x80002AAA
+ #define C3_ID0_STATE_MASK 0xC0000000
+ #define C3_ID0_STATE_RUN 0xC0000000
+ #define C3_ID0_STATE_IDLE 0x80000000
+
+/* C3 Register Offsets */
+#define C3_MOVE_CHANNEL_ID (CONFIG_SYS_C3_BASE + 0x2000 + 0x3FC)
+ #define C3_MOVE_CHANNEL_ID_VAL 0x00000102
+
+#define C3_INT_MEM_SIZE 0x4000
+#define C3_MOVE_AND (1 << 21)
+
+/* Some Commands */
+#define C3_CMD_MOVE_INIT 0x06000000
+#define C3_CMD_MOVE_DATA 0x0A800000
+#define C3_CMD_STOP 0x00000000
+
+void *c3_memset(void *s, int c, size_t count);
+int c3_init(void);
+
+#endif
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 271463c..209291f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
+COBJS-$(CONFIG_C3) += c3.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
diff --git a/drivers/misc/c3.c b/drivers/misc/c3.c
new file mode 100644
index 0000000..20dc8aa
--- /dev/null
+++ b/drivers/misc/c3.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2012
+ * ST Micoelectronics Pvt. Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/c3.h>
+#include <asm/arch/hardware.h>
+
+static unsigned long c3_mem_xlate(void *addr)
+{
+
+ if (((ulong)addr < C3_INT_MEM_BASE_ADDR) || \
+ ((ulong)addr >= (C3_INT_MEM_BASE_ADDR + C3_INT_MEM_SIZE)))
+ return (ulong)addr;
+
+ return (unsigned long)addr - C3_INT_MEM_BASE_ADDR +
+ C3_LOCAL_MEM_ADDR;
+}
+
+int c3_init(void)
+{
+ if (readl(C3_ID0_SCR) != C3_ID0_DEF_RDY_VAL)
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
+
+ if (readl(C3_MOVE_CHANNEL_ID) == C3_MOVE_CHANNEL_ID_VAL)
+ return -EINVAL;
+
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+ writel(C3_LOCAL_MEM_ADDR, C3_HIF_MBAR);
+
+ return 0;
+}
+
+static int c3_run(void *prog_start)
+{
+ writel(c3_mem_xlate(prog_start), C3_ID0_IP);
+
+ while ((readl(C3_ID0_SCR) & C3_ID0_STATE_MASK) == C3_ID0_STATE_RUN)
+ ;
+
+ if ((readl(C3_ID0_SCR) & C3_ID0_STATE_MASK) != C3_ID0_STATE_IDLE) {
+ /* If not back to idle an error occured */
+ writel(C3_ID0_SCR_RST, C3_ID0_SCR);
+
+ /* Set internal access to run c3 programs */
+ writel(C3_HIF_MCR_ENB_INT_MEM, C3_HIF_MCR);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int c3_move(void *dest, void *src, int cnt, int optype, int opdata)
+{
+ unsigned long *c3_prog;
+ int ret = 0;
+
+ /* 3.b Prepare program */
+ c3_prog = (unsigned long *)C3_INT_MEM_BASE_ADDR;
+
+ /* 3.b.i. Mov init */
+ c3_prog[0] = C3_CMD_MOVE_INIT;
+ c3_prog[1] = opdata;
+
+ /* 3.b.ii. Mov data */
+ c3_prog[2] = C3_CMD_MOVE_DATA + cnt + optype;
+ c3_prog[3] = c3_mem_xlate(src);
+ c3_prog[4] = c3_mem_xlate(dest);
+
+ /* 3.b.iii. Stop */
+ c3_prog[5] = C3_CMD_STOP;
+
+ /* 4. Execute and wait */
+ ret = c3_run(c3_prog);
+
+ return ret;
+}
+
+void *c3_memset(void *s, int c, size_t count)
+{
+#define DATA_SIZE (1024*4)
+ u32 data = C3_INT_MEM_BASE_ADDR + 0x100;
+ u32 size;
+ size_t cur = 0;
+
+ writel(0x100, C3_HIF_MAAR);
+ writel(c, C3_HIF_MADR);
+
+ for (size = 4; size < DATA_SIZE; size <<= 1)
+ c3_move((void *)(data + size), (void *)data, size,
+ C3_MOVE_AND, 0xffffffff);
+
+ while (cur < count) {
+ c3_move(s + cur, (void *)data, DATA_SIZE,
+ C3_MOVE_AND, 0xffffffff);
+ cur += DATA_SIZE;
+ }
+
+ return s;
+}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 16/19] armv7/ltimer: Add support for local timer on armv7 cpus
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (12 preceding siblings ...)
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 15/19] misc/crypto: Add support for C3 Vipin Kumar
@ 2012-11-02 17:40 ` Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device Vipin Kumar
` (2 subsequent siblings)
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:40 UTC (permalink / raw)
To: u-boot
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 154 ++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/ca9_ltimer.h | 40 ++++++++++
3 files changed, 201 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
create mode 100644 arch/arm/include/asm/ca9_ltimer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..3ef01f6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o
START := start.o
-COBJS += cache_v7.o
+COBJS-y += cache_v7.o
-COBJS += cpu.o
-COBJS += syslib.o
+COBJS-y += cpu.o
+COBJS-y += syslib.o
+COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
-SOBJS += lowlevel_init.o
+SOBJS-y += lowlevel_init.o
endif
+COBJS := $(sort $(COBJS-y))
+SOBJS := $(sort $(SOBJS-y))
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c
new file mode 100644
index 0000000..be04b6a
--- /dev/null
+++ b/arch/arm/cpu/armv7/ca9_ltimer.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/ca9_ltimer.h>
+#include <asm/arch/hardware.h>
+
+#define READ_TIMER() readl(&ca9_timer_p->count)
+
+static struct ca9_timer_regs *const ca9_timer_p =
+ (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
+#define tickshz gd->timer_rate_hz
+#define ticksper10usec gd->tbu
+
+int timer_init(void)
+{
+ u32 prescaler, timertickshz;
+ /*
+ * Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which
+ * means that CA9 local timer clock would be in the range of 250 MHz to
+ * 750MHz.
+ * Try to find a prescaler which can perfectly divide the local timer
+ * clock. Take prescaler as 200 if nothing is found
+ */
+ for (prescaler = 255; prescaler > 1; prescaler--) {
+ if (CONFIG_ARMV7_LTMR_CLK ==
+ (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler)
+ break;
+ }
+
+ if (prescaler == 1)
+ prescaler = 200;
+ timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler;
+ ticksper10usec = timertickshz / (100 * 1000);
+ tickshz = timertickshz / CONFIG_SYS_HZ;
+
+ /* disable timers */
+ writel(((prescaler - 1) << 8) | AUTO_RELOAD, &ca9_timer_p->control);
+
+ /* load value for free running */
+ writel(FREE_RUNNING, &ca9_timer_p->load);
+
+ /* auto reload, start timer */
+ writel(readl(&ca9_timer_p->control) | TIMER_ENABLE,
+ &ca9_timer_p->control);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_masked() / tickshz) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer_masked();
+ ulong rndoff;
+
+ rndoff = (usec % 10) ? 1 : 0;
+ tmo = ((usec / 10) + rndoff) * ticksper10usec;
+
+ while ((ulong) (get_timer_masked() - start) < tmo)
+ ;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER();
+
+ if (now <= lastdec) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + FREE_RUNNING - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/ca9_ltimer.h b/arch/arm/include/asm/ca9_ltimer.h
new file mode 100644
index 0000000..8833853
--- /dev/null
+++ b/arch/arm/include/asm/ca9_ltimer.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_CA9TIMER_H
+#define __ARCH_ARM_CA9TIMER_H
+
+struct ca9_timer_regs {
+ u32 load;
+ u32 count;
+ u32 control;
+};
+
+/* control related definitions */
+#define AUTO_RELOAD (1 << 1)
+#define TIMER_ENABLE (1 << 0)
+
+/* load related definitions */
+#define FREE_RUNNING (0xFFFFFFFF)
+
+#endif
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (13 preceding siblings ...)
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 16/19] armv7/ltimer: Add support for local timer on armv7 cpus Vipin Kumar
@ 2012-11-02 17:40 ` Vipin Kumar
2012-11-06 23:30 ` Scott Wood
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 18/19] u-boot/spl: Add u-boot-spl.img to u-boot targets Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 19/19] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P Vipin Kumar
16 siblings, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:40 UTC (permalink / raw)
To: u-boot
imls does not list the images in NAND devices. This patch implements this
support for legacy type images.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
common/cmd_bootm.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 83fa5d7..ca3c430 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -62,6 +62,11 @@
#include <linux/lzo.h>
#endif /* CONFIG_LZO */
+#if defined(CONFIG_CMD_NAND)
+#include <linux/err.h>
+#include <nand.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_BOOTM_LEN
@@ -1221,6 +1226,99 @@ next_sector: ;
next_bank: ;
}
+#if defined(CONFIG_CMD_NAND)
+ printf("\n");
+ nand_info_t *nand;
+ image_header_t image_header;
+ image_header_t *header = &image_header;
+ int nand_dev = nand_curr_device;
+ unsigned long img_size;
+ size_t hdr_size, read_len;
+ loff_t off;
+ unsigned int crc;
+ u_char *data;
+
+ /* the following commands operate on the current device */
+ if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts("\nNo NAND devices available\n");
+ return 0;
+ }
+
+ for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+
+ nand = &nand_info[nand_dev];
+ if ((!nand->name) || (!nand->size))
+ continue;
+
+ data = malloc(nand->writesize);
+ if (!data) {
+ puts("No memory available to list NAND images\n");
+ return 0;
+ }
+
+ for (off = 0; off < nand->size; off += nand->erasesize) {
+ int ret;
+
+ if (nand_block_isbad(nand, off))
+ continue;
+
+ hdr_size = sizeof(image_header_t);
+ ret = nand_read(nand, off, &hdr_size, (u_char *)header);
+ if (ret < 0 && ret != -EUCLEAN)
+ continue;
+
+ if (!image_check_hcrc(header))
+ continue;
+
+ printf("Legacy Image@NAND device %d offset %08lX:\n",
+ nand_dev, (ulong)off);
+ image_print_contents(header);
+
+ puts(" Verifying Checksum ... ");
+ crc = 0;
+ img_size = ntohl(header->ih_size);
+ img_size += hdr_size;
+
+ while (img_size > 0) {
+ int blockoff = 0;
+
+ while (nand_block_isbad(nand, off)) {
+ off += nand->erasesize;
+ if (off >= nand->size)
+ goto out;
+ }
+
+ do {
+ read_len = min(img_size,
+ nand->writesize);
+ ret = nand_read(nand, off + blockoff,
+ &read_len, data);
+ if (ret < 0 && ret != -EUCLEAN)
+ break;
+
+ crc = crc32(crc, data + hdr_size,
+ read_len - hdr_size);
+ img_size -= read_len;
+ blockoff += read_len;
+ hdr_size = 0;
+ } while (img_size &&
+ (blockoff < nand->erasesize));
+
+ off += nand->erasesize;
+ if (off >= nand->size)
+ goto out;
+ }
+ off -= nand->erasesize;
+out:
+ if (crc != ntohl(header->ih_dcrc))
+ puts(" Bad Data CRC\n");
+ else
+ puts("OK\n");
+ }
+ free(data);
+ }
+
+#endif
return (0);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 18/19] u-boot/spl: Add u-boot-spl.img to u-boot targets
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (14 preceding siblings ...)
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device Vipin Kumar
@ 2012-11-02 17:40 ` Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 19/19] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P Vipin Kumar
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:40 UTC (permalink / raw)
To: u-boot
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
Makefile | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Makefile b/Makefile
index 328347d..5d8d430 100644
--- a/Makefile
+++ b/Makefile
@@ -497,6 +497,13 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
+$(obj)spl/u-boot-spl.img: $(obj)spl/u-boot-spl.bin
+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n $(shell sed -n -e 's/.*U_BOOT_SPL_VERSION//p' $(VERSION_FILE) | \
+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
+ -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
+
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
# bootloader can check its integrity. Padding needs to be done to the
@@ -704,6 +711,9 @@ $(VERSION_FILE):
"$(U_BOOT_VERSION)" "$${localvers}" ; \
printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
"$(U_BOOT_VERSION)" "$${localvers}" ; \
+ printf '#define U_BOOT_SPL_VERSION "%s %s%s"\n' \
+ $(if $(CONFIG_SPL_IMAGENAME),$(CONFIG_SPL_IMAGENAME),"U-Boot SPL") \
+ "$(U_BOOT_VERSION)" "$${localvers}" ; \
) > $@.tmp
@( printf '#define CC_VERSION_STRING "%s"\n' \
'$(shell $(CC) --version | head -n 1)' )>> $@.tmp
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 19/19] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
` (15 preceding siblings ...)
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 18/19] u-boot/spl: Add u-boot-spl.img to u-boot targets Vipin Kumar
@ 2012-11-02 17:40 ` Vipin Kumar
16 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-02 17:40 UTC (permalink / raw)
To: u-boot
A lot of ARM boards are using board_init routine just to initialize boot_params
variable in the global data structure.
This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
which is assigned to gd->bd->bi_boot_params automatically
Consequently, many board_init routines would not be required in the respective
board directories and a weak definition becomes necessary before their removal
from the code.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
README | 6 ++++++
arch/arm/lib/board.c | 12 ++++++++++++
2 files changed, 18 insertions(+)
diff --git a/README b/README
index 69da2b8..444663d 100644
--- a/README
+++ b/README
@@ -550,6 +550,12 @@ The following options need to be configured:
in a single configuration file and the machine type is
runtime discoverable, do not have to use this setting.
+ CONFIG_BOOT_PARAMS_P [relevant for ARM only]
+
+ This config option can provide a way to initialize
+ bi_boot_params from the u-boot infrastructure itself. The
+ board still has the option to override it in board_init routine
+
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 92cad9a..fa161b8 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -399,6 +399,11 @@ void board_init_f(ulong bootflag)
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
+#ifdef CONFIG_BOOT_PARAMS_P
+ /* Boot params passed to Linux */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_P;
+#endif
+
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
@@ -468,6 +473,13 @@ void board_init_f(ulong bootflag)
static char *failed = "*** failed ***\n";
#endif
+static int __def_board_init(bd_t *bis)
+{
+ return -1;
+}
+
+int board_init(void) __attribute__((weak, alias("__def_board_init")));
+
/*
************************************************************************
*
--
1.7.11.4
^ permalink raw reply related [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device Vipin Kumar
@ 2012-11-06 23:30 ` Scott Wood
2012-11-07 5:15 ` Vipin Kumar
0 siblings, 1 reply; 72+ messages in thread
From: Scott Wood @ 2012-11-06 23:30 UTC (permalink / raw)
To: u-boot
On 11/02/2012 12:40:02 PM, Vipin Kumar wrote:
> imls does not list the images in NAND devices. This patch implements
> this
> support for legacy type images.
>
> Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
> ---
> common/cmd_bootm.c | 98
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
> index 83fa5d7..ca3c430 100644
> --- a/common/cmd_bootm.c
> +++ b/common/cmd_bootm.c
> @@ -62,6 +62,11 @@
> #include <linux/lzo.h>
> #endif /* CONFIG_LZO */
>
> +#if defined(CONFIG_CMD_NAND)
> +#include <linux/err.h>
> +#include <nand.h>
> +#endif
You shouldn't need to ifdef-protect header files.
> DECLARE_GLOBAL_DATA_PTR;
>
> #ifndef CONFIG_SYS_BOOTM_LEN
> @@ -1221,6 +1226,99 @@ next_sector: ;
> next_bank: ;
> }
>
> +#if defined(CONFIG_CMD_NAND)
> + printf("\n");
> + nand_info_t *nand;
> + image_header_t image_header;
> + image_header_t *header = &image_header;
> + int nand_dev = nand_curr_device;
> + unsigned long img_size;
> + size_t hdr_size, read_len;
> + loff_t off;
> + unsigned int crc;
> + u_char *data;
> +
> + /* the following commands operate on the current device */
> + if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
> + puts("\nNo NAND devices available\n");
> + return 0;
> + }
Please move the NAND and NOR code into their own functions.
> +
> + for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE;
> nand_dev++) {
> +
> + nand = &nand_info[nand_dev];
> + if ((!nand->name) || (!nand->size))
> + continue;
Redundant parentheses.
> + data = malloc(nand->writesize);
> + if (!data) {
> + puts("No memory available to list NAND
> images\n");
> + return 0;
> + }
> +
> + for (off = 0; off < nand->size; off += nand->erasesize)
> {
> + int ret;
> +
> + if (nand_block_isbad(nand, off))
> + continue;
> +
> + hdr_size = sizeof(image_header_t);
> + ret = nand_read(nand, off, &hdr_size, (u_char
> *)header);
> + if (ret < 0 && ret != -EUCLEAN)
> + continue;
I guess you don't use nand_read_skip_bad() because you don't want to
allocate a buffer for the whole image... How about moving this code to
nand_util.c? That would at least allow some refactoring rather than
duplication.
> + if (!image_check_hcrc(header))
> + continue;
> +
> + printf("Legacy Image at NAND device %d offset
> %08lX:\n",
> + nand_dev, (ulong)off);
> + image_print_contents(header);
Shouldn't you check for FIT images as well?
> + puts(" Verifying Checksum ... ");
> + crc = 0;
> + img_size = ntohl(header->ih_size);
> + img_size += hdr_size;
> +
> + while (img_size > 0) {
> + int blockoff = 0;
> +
> + while (nand_block_isbad(nand, off)) {
> + off += nand->erasesize;
> + if (off >= nand->size)
> + goto out;
> + }
> +
> + do {
> + read_len = min(img_size,
> +
> nand->writesize);
> + ret = nand_read(nand, off +
> blockoff,
> + &read_len,
> data);
> + if (ret < 0 && ret != -EUCLEAN)
> + break;
> +
> + crc = crc32(crc, data +
> hdr_size,
> + read_len -
> hdr_size);
> + img_size -= read_len;
> + blockoff += read_len;
> + hdr_size = 0;
> + } while (img_size &&
> + (blockoff <
> nand->erasesize));
> +
> + off += nand->erasesize;
> + if (off >= nand->size)
> + goto out;
> + }
> + off -= nand->erasesize;
> +out:
> + if (crc != ntohl(header->ih_dcrc))
> + puts(" Bad Data CRC\n");
> + else
> + puts("OK\n");
> + }
Please refactor this into separate functions to improve readability.
Maybe put a nand_crc_skip_bad() function into nand_util.c?
-Scott
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device
2012-11-06 23:30 ` Scott Wood
@ 2012-11-07 5:15 ` Vipin Kumar
2012-11-07 20:49 ` Scott Wood
0 siblings, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2012-11-07 5:15 UTC (permalink / raw)
To: u-boot
On 11/7/2012 5:00 AM, Scott Wood wrote:
> On 11/02/2012 12:40:02 PM, Vipin Kumar wrote:
>> imls does not list the images in NAND devices. This patch implements this
>> support for legacy type images.
>>
>> Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
>> ---
>> common/cmd_bootm.c | 98
>> ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 98 insertions(+)
>>
>> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
>> index 83fa5d7..ca3c430 100644
>> --- a/common/cmd_bootm.c
>> +++ b/common/cmd_bootm.c
>> @@ -62,6 +62,11 @@
>> #include <linux/lzo.h>
>> #endif /* CONFIG_LZO */
>>
>> +#if defined(CONFIG_CMD_NAND)
>> +#include <linux/err.h>
>> +#include <nand.h>
>> +#endif
>
> You shouldn't need to ifdef-protect header files.
>
OK. I would correct this in v2
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> #ifndef CONFIG_SYS_BOOTM_LEN
>> @@ -1221,6 +1226,99 @@ next_sector: ;
>> next_bank: ;
>> }
>>
>> +#if defined(CONFIG_CMD_NAND)
>> + printf("\n");
>> + nand_info_t *nand;
>> + image_header_t image_header;
>> + image_header_t *header = &image_header;
>> + int nand_dev = nand_curr_device;
>> + unsigned long img_size;
>> + size_t hdr_size, read_len;
>> + loff_t off;
>> + unsigned int crc;
>> + u_char *data;
>> +
>> + /* the following commands operate on the current device */
>> + if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
>> + puts("\nNo NAND devices available\n");
>> + return 0;
>> + }
>
> Please move the NAND and NOR code into their own functions.
>
You mean I can separate the NOR list images code in one routine and NAND
in another?
>> +
>> + for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
>> +
>> + nand = &nand_info[nand_dev];
>> + if ((!nand->name) || (!nand->size))
>> + continue;
>
> Redundant parentheses.
>
Accepted
>> + data = malloc(nand->writesize);
>> + if (!data) {
>> + puts("No memory available to list NAND images\n");
>> + return 0;
>> + }
>> +
>> + for (off = 0; off < nand->size; off += nand->erasesize) {
>> + int ret;
>> +
>> + if (nand_block_isbad(nand, off))
>> + continue;
>> +
>> + hdr_size = sizeof(image_header_t);
>> + ret = nand_read(nand, off, &hdr_size, (u_char *)header);
>> + if (ret < 0 && ret != -EUCLEAN)
>> + continue;
>
> I guess you don't use nand_read_skip_bad() because you don't want to
> allocate a buffer for the whole image... How about moving this code to
> nand_util.c? That would at least allow some refactoring rather than
> duplication.
>
>> + if (!image_check_hcrc(header))
>> + continue;
>> +
>> + printf("Legacy Image at NAND device %d offset %08lX:\n",
>> + nand_dev, (ulong)off);
>> + image_print_contents(header);
>
> Shouldn't you check for FIT images as well?
>
Yes. I was a bit reluctant because I don't know about that format.
OK, I would try to add it in v2
>> + puts(" Verifying Checksum ... ");
>> + crc = 0;
>> + img_size = ntohl(header->ih_size);
>> + img_size += hdr_size;
>> +
>> + while (img_size > 0) {
>> + int blockoff = 0;
>> +
>> + while (nand_block_isbad(nand, off)) {
>> + off += nand->erasesize;
>> + if (off >= nand->size)
>> + goto out;
>> + }
>> +
>> + do {
>> + read_len = min(img_size,
>> + nand->writesize);
>> + ret = nand_read(nand, off + blockoff,
>> + &read_len, data);
>> + if (ret < 0 && ret != -EUCLEAN)
>> + break;
>> +
>> + crc = crc32(crc, data + hdr_size,
>> + read_len - hdr_size);
>> + img_size -= read_len;
>> + blockoff += read_len;
>> + hdr_size = 0;
>> + } while (img_size &&
>> + (blockoff < nand->erasesize));
>> +
>> + off += nand->erasesize;
>> + if (off >= nand->size)
>> + goto out;
>> + }
>> + off -= nand->erasesize;
>> +out:
>> + if (crc != ntohl(header->ih_dcrc))
>> + puts(" Bad Data CRC\n");
>> + else
>> + puts("OK\n");
>> + }
>
> Please refactor this into separate functions to improve readability.
> Maybe put a nand_crc_skip_bad() function into nand_util.c?
>
OK, I would give it a try. Please wait for v2
> -Scott
>
btw, thanks for the review
How about other patches, Albert, Wolfgang ?
Regards
Vipin
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
[not found] <cover.1351876757.git.vipin.kumar@st.com>
` (3 preceding siblings ...)
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
@ 2012-11-07 14:10 ` Stefan Roese
2012-11-08 4:58 ` Vipin Kumar
2012-11-08 4:58 ` Vipin Kumar
2012-11-20 9:46 ` Vipin Kumar
5 siblings, 2 replies; 72+ messages in thread
From: Stefan Roese @ 2012-11-07 14:10 UTC (permalink / raw)
To: u-boot
Hi Vipin,
On 11/02/2012 06:39 PM, Vipin Kumar wrote:
> This patchset is split in several pieces
> - Drivers: This is essentially a few new drivers and fixes in already exiasting
> drivers
> - Enhancement: This series enhances the already existing spear support
> - spear13xx: This is a totally new suppoort for spear13xx architecture
Thanks for all these patches. This is a massive patch-set. I'll try to
review at least some of them later this week. Please be patient.
But this amount of patches does raise a question that I discussed a time
ago. If you continue to work on upstream U-Boot, which we greatly
appreciate, then its perhaps better to create/add an SPEAr U-Boot
custodian responsible for the SPEAr related patches. Reviewing,
collecting patches and pushing them to Alberts ARM repository. This
would take a bit of work from Albert, since without such an custodian
all those SPEAr patches would fall into his area.
What do you guys think?
Albert, what are your thoughts on this?
Vipin, would you "volunteer" to eventually become this SPEAr U-Boot
custodian? Or someone else?
Just my thought, comments welcome!
Thanks,
Stefan
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: office at denx.de
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device
2012-11-07 5:15 ` Vipin Kumar
@ 2012-11-07 20:49 ` Scott Wood
0 siblings, 0 replies; 72+ messages in thread
From: Scott Wood @ 2012-11-07 20:49 UTC (permalink / raw)
To: u-boot
On 11/06/2012 11:15:42 PM, Vipin Kumar wrote:
> On 11/7/2012 5:00 AM, Scott Wood wrote:
>> On 11/02/2012 12:40:02 PM, Vipin Kumar wrote:
>>> +#if defined(CONFIG_CMD_NAND)
>>> + printf("\n");
>>> + nand_info_t *nand;
>>> + image_header_t image_header;
>>> + image_header_t *header = &image_header;
>>> + int nand_dev = nand_curr_device;
>>> + unsigned long img_size;
>>> + size_t hdr_size, read_len;
>>> + loff_t off;
>>> + unsigned int crc;
>>> + u_char *data;
>>> +
>>> + /* the following commands operate on the current device */
>>> + if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
>>> + puts("\nNo NAND devices available\n");
>>> + return 0;
>>> + }
>>
>> Please move the NAND and NOR code into their own functions.
>>
>
> You mean I can separate the NOR list images code in one routine and
> NAND in another?
Yes.
-Scott
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-07 14:10 ` [U-Boot] [PATCH 00/46] Enhance spear support Stefan Roese
@ 2012-11-08 4:58 ` Vipin Kumar
2012-11-08 4:58 ` Vipin Kumar
1 sibling, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-08 4:58 UTC (permalink / raw)
To: u-boot
On 11/7/2012 7:40 PM, Stefan Roese wrote:
> Hi Vipin,
>
> On 11/02/2012 06:39 PM, Vipin Kumar wrote:
>> This patchset is split in several pieces
>> - Drivers: This is essentially a few new drivers and fixes in already exiasting
>> drivers
>> - Enhancement: This series enhances the already existing spear support
>> - spear13xx: This is a totally new suppoort for spear13xx architecture
>
> Thanks for all these patches. This is a massive patch-set. I'll try to
> review at least some of them later this week. Please be patient.
>
> But this amount of patches does raise a question that I discussed a time
> ago. If you continue to work on upstream U-Boot, which we greatly
> appreciate, then its perhaps better to create/add an SPEAr U-Boot
> custodian responsible for the SPEAr related patches. Reviewing,
> collecting patches and pushing them to Alberts ARM repository. This
> would take a bit of work from Albert, since without such an custodian
> all those SPEAr patches would fall into his area.
>
> What do you guys think?
>
> Albert, what are your thoughts on this?
>
> Vipin, would you "volunteer" to eventually become this SPEAr U-Boot
> custodian? Or someone else?
>
Yes, I can volunteer to be the SPEAr U-Boot custodian..
Regards
Vipin
> Just my thought, comments welcome!
>
> Thanks,
> Stefan
>
> DENX Software Engineering GmbH, MD: Wolfgang Denk& Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: office at denx.de
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-07 14:10 ` [U-Boot] [PATCH 00/46] Enhance spear support Stefan Roese
2012-11-08 4:58 ` Vipin Kumar
@ 2012-11-08 4:58 ` Vipin Kumar
[not found] ` <509CD19A.2060903@st.com>
1 sibling, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2012-11-08 4:58 UTC (permalink / raw)
To: u-boot
On 11/7/2012 7:40 PM, Stefan Roese wrote:
> Hi Vipin,
>
> On 11/02/2012 06:39 PM, Vipin Kumar wrote:
>> This patchset is split in several pieces
>> - Drivers: This is essentially a few new drivers and fixes in already exiasting
>> drivers
>> - Enhancement: This series enhances the already existing spear support
>> - spear13xx: This is a totally new suppoort for spear13xx architecture
>
> Thanks for all these patches. This is a massive patch-set. I'll try to
> review at least some of them later this week. Please be patient.
>
> But this amount of patches does raise a question that I discussed a time
> ago. If you continue to work on upstream U-Boot, which we greatly
> appreciate, then its perhaps better to create/add an SPEAr U-Boot
> custodian responsible for the SPEAr related patches. Reviewing,
> collecting patches and pushing them to Alberts ARM repository. This
> would take a bit of work from Albert, since without such an custodian
> all those SPEAr patches would fall into his area.
>
> What do you guys think?
>
> Albert, what are your thoughts on this?
>
> Vipin, would you "volunteer" to eventually become this SPEAr U-Boot
> custodian? Or someone else?
>
Yes, I volunteer to be the SPEAr U-Boot custodian..
Regards
Vipin
> Just my thought, comments welcome!
>
> Thanks,
> Stefan
>
> DENX Software Engineering GmbH, MD: Wolfgang Denk& Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: office at denx.de
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
[not found] ` <509CD19A.2060903@st.com>
@ 2012-11-09 11:56 ` Stefan Roese
2012-11-10 8:48 ` Albert ARIBAUD
0 siblings, 1 reply; 72+ messages in thread
From: Stefan Roese @ 2012-11-09 11:56 UTC (permalink / raw)
To: u-boot
On 11/09/2012 10:49 AM, Armando Visconti wrote:
> Ciao Stefan, Vipin,
>
>>>
>>> Vipin, would you "volunteer" to eventually become this SPEAr U-Boot
>>> custodian? Or someone else?
>>>
>>
>> Yes, I volunteer to be the SPEAr U-Boot custodian..
>>
>
> I think that no one else could to this custodian job
> better than Vipin...
>
> Guaranteed!
I'm all for it. Lets see what Albert has to say here.
Albert, whats your opinion here? Would you also like to see an SPEAr
custodian to offload your patch-queue a but? Or would you prefer to
handle SPEAr related patches yourself in the future?
Thanks,
Stefan
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-09 11:56 ` Stefan Roese
@ 2012-11-10 8:48 ` Albert ARIBAUD
2012-11-11 6:11 ` Stefan Roese
0 siblings, 1 reply; 72+ messages in thread
From: Albert ARIBAUD @ 2012-11-10 8:48 UTC (permalink / raw)
To: u-boot
Hi Stefan,
On Fri, 09 Nov 2012 12:56:42 +0100, Stefan Roese <sr@denx.de> wrote:
> On 11/09/2012 10:49 AM, Armando Visconti wrote:
> > Ciao Stefan, Vipin,
> >
> >>>
> >>> Vipin, would you "volunteer" to eventually become this SPEAr U-Boot
> >>> custodian? Or someone else?
> >>>
> >>
> >> Yes, I volunteer to be the SPEAr U-Boot custodian..
> >>
> >
> > I think that no one else could to this custodian job
> > better than Vipin...
> >
> > Guaranteed!
>
> I'm all for it. Lets see what Albert has to say here.
>
> Albert, whats your opinion here? Would you also like to see an SPEAr
> custodian to offload your patch-queue a but? Or would you prefer to
> handle SPEAr related patches yourself in the future?
I heartily welcome specialized ARM repositories and custodians. :)
> Thanks,
> Stefan
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-10 8:48 ` Albert ARIBAUD
@ 2012-11-11 6:11 ` Stefan Roese
2012-11-11 7:50 ` Wolfgang Denk
0 siblings, 1 reply; 72+ messages in thread
From: Stefan Roese @ 2012-11-11 6:11 UTC (permalink / raw)
To: u-boot
On 11/10/2012 09:48 AM, Albert ARIBAUD wrote:
>>>> Yes, I volunteer to be the SPEAr U-Boot custodian..
>>>>
>>>
>>> I think that no one else could to this custodian job
>>> better than Vipin...
>>>
>>> Guaranteed!
>>
>> I'm all for it. Lets see what Albert has to say here.
>>
>> Albert, whats your opinion here? Would you also like to see an SPEAr
>> custodian to offload your patch-queue a but? Or would you prefer to
>> handle SPEAr related patches yourself in the future?
>
> I heartily welcome specialized ARM repositories and custodians. :)
Okay, its decided then. :)
Vipin, please send your public ssh key to Wolfgang so that we can create
the new "spear" U-Boot git repository for you.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-11 6:11 ` Stefan Roese
@ 2012-11-11 7:50 ` Wolfgang Denk
2012-11-11 17:49 ` Albert ARIBAUD
2012-11-12 10:35 ` Vipin Kumar
0 siblings, 2 replies; 72+ messages in thread
From: Wolfgang Denk @ 2012-11-11 7:50 UTC (permalink / raw)
To: u-boot
Dear Stefan,
In message <509F4194.9070202@denx.de> you wrote:
>
> Vipin, please send your public ssh key to Wolfgang so that we can create
> the new "spear" U-Boot git repository for you.
Will this be only SPEAr, or should we expect other chips fromSTM to go
though it, too (so a more generic name like u-boot-stm would be
better) ?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You said you didn't want to use CGI.pm, but methinks you are
needlessly reinventing the wheel, one spoke at a time. Either you are
masochistic, or you just haven't seen enough of what CGI.pm can do
for you. -- Randal L. Schwartz in <8cyb81rg81.fsf@gadget.cscaper.com>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-11 7:50 ` Wolfgang Denk
@ 2012-11-11 17:49 ` Albert ARIBAUD
2012-11-12 9:34 ` Armando Visconti
2012-11-12 10:35 ` Vipin Kumar
1 sibling, 1 reply; 72+ messages in thread
From: Albert ARIBAUD @ 2012-11-11 17:49 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Sun, 11 Nov 2012 08:50:46 +0100, Wolfgang Denk <wd@denx.de> wrote:
> Dear Stefan,
>
> In message <509F4194.9070202@denx.de> you wrote:
> >
> > Vipin, please send your public ssh key to Wolfgang so that we can create
> > the new "spear" U-Boot git repository for you.
>
> Will this be only SPEAr, or should we expect other chips fromSTM to go
> though it, too (so a more generic name like u-boot-stm would be
> better) ?
Even if it's only SPEAr for now, I 'vote' for u-boot-stm.
> Best regards,
>
> Wolfgang Denk
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-11 17:49 ` Albert ARIBAUD
@ 2012-11-12 9:34 ` Armando Visconti
0 siblings, 0 replies; 72+ messages in thread
From: Armando Visconti @ 2012-11-12 9:34 UTC (permalink / raw)
To: u-boot
On 11/11/2012 06:49 PM, Albert ARIBAUD wrote:
> Hi Wolfgang,
>
> On Sun, 11 Nov 2012 08:50:46 +0100, Wolfgang Denk<wd@denx.de> wrote:
>
>> Dear Stefan,
>>
>> In message<509F4194.9070202@denx.de> you wrote:
>>>
>>> Vipin, please send your public ssh key to Wolfgang so that we can create
>>> the new "spear" U-Boot git repository for you.
>>
>> Will this be only SPEAr, or should we expect other chips fromSTM to go
>> though it, too (so a more generic name like u-boot-stm would be
>> better) ?
>
> Even if it's only SPEAr for now, I 'vote' for u-boot-stm.
>
It is only SPEAr for the moment, but I think that Vipin can be the
custodian also for other stm devices...
Vipin, do you agree with that?
Rgds,
Arm
--
-- "Every step appears to be the unavoidable consequence of the
-- preceding one." (A. Einstein)
--
Armando Visconti Mobile: (+39) 346 8879146
Senior SW Engineer Fax: (+39) 02 93519290
CPG Work: (+39) 02 93519683
Computer System Division e-mail: armando.visconti at st.com
ST Microelectronics TINA: 051 4683
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-11 7:50 ` Wolfgang Denk
2012-11-11 17:49 ` Albert ARIBAUD
@ 2012-11-12 10:35 ` Vipin Kumar
2012-11-21 9:24 ` Wolfgang Denk
1 sibling, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2012-11-12 10:35 UTC (permalink / raw)
To: u-boot
On 11/11/2012 1:20 PM, Wolfgang Denk wrote:
> Dear Stefan,
>
> In message<509F4194.9070202@denx.de> you wrote:
>>
>> Vipin, please send your public ssh key to Wolfgang so that we can create
>> the new "spear" U-Boot git repository for you.
>
Hello Wolfgang
> Will this be only SPEAr, or should we expect other chips fromSTM to go
Yes, it will only be for spear as of now
> though it, too (so a more generic name like u-boot-stm would be
> better) ?
>
The ssh key is as below
ssh-rsa
AAAAB3NzaC1yc2EAAAABIwAAAQEA4FSMngFagc4TFNX5JoxxTmLe9oqUZcaILgs6OH8T2kOpxykq4tL30xzKPdTW5w++UT+N7GYJLaYvv0gaGg9d/GbunhBrHexBar8aYwz71uHQzOJ1Gpx4otbE1vZ5TOlOqecBGMTYXzHBRDdCCDWwwKgkLm6Q2ZlEXeo64q2RZ7iOCoWAUjHoXcNnNKtKI4D+JIVeONxCYYehbktPGznajpzXMHuOBS7wEXBj4U1ekv2YUI316b485KjYoufALeICoGQq3OCqxVH8FxgV1HfzVer1fimHYPjaHSAPRyDiNqxLj/s/ToBKuW+3UX+gM2ef9x0TXXGhoeXozXTxlyQyaw==
vipink at DLH10018
Best Regards
Vipin
> Best regards,
>
> Wolfgang Denk
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
[not found] <cover.1351876757.git.vipin.kumar@st.com>
` (4 preceding siblings ...)
2012-11-07 14:10 ` [U-Boot] [PATCH 00/46] Enhance spear support Stefan Roese
@ 2012-11-20 9:46 ` Vipin Kumar
5 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-11-20 9:46 UTC (permalink / raw)
To: u-boot
Hello u-boot team,
Can you please provide some comments on this patch-set
Please consider this for inclusion
Regards
Vipin
On 11/2/2012 11:09 PM, Vipin KUMAR wrote:
> This patchset is split in several pieces
> - Drivers: This is essentially a few new drivers and fixes in already exiasting
> drivers
> - Enhancement: This series enhances the already existing spear support
> - spear13xx: This is a totally new suppoort for spear13xx architecture
>
> Armando Visconti (2):
> mtd/st_smi: Add support for Micron N25Q128 Flash
> spi/arm-pl022: Add support for ARM PL022 spi controller
>
> Pratyush Anand (1):
> usb/gadget/designware_otg: Add support for designware otg
>
> Shiraz Hashim (3):
> usbtty: adapt buffers for large packet support
> net/macb: Add arch specific routine to get mdio control
> net/macb: workaround for transmission hang issue
>
> Vipin Kumar (40):
> mtd/st_smi: Clear error flags while initiating a fresh write
> mtd/st_smi: Avoid issuing multiple WE commands
> mtd/st_smi: Write to flash in a tight loop
> mtd/st_smi: Use page sizes respective to flash
> usbh/ehci: Increase timeout for enumeration
> sdhci: Add sdhci support for spear devices
> net/designware: Do not select MIIPORT for RGMII interface
> usb/host/ehci: Add support for EHCI on spear
> misc/crypto: Add support for C3
> armv7/ltimer: Add support for local timer on armv7 cpus
> imls: Add support to list images in NAND device
> u-boot/spl: Add u-boot-spl.img to u-boot targets
> arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P
> SPEAr: Remove extra spear board configurations
> spear/configs: Split config files hierarchically into plat, arch, soc
> and board
> spear/include: Clean up the spear include files
> spear/board: Cleanup spear related board files
> spear: Append MISC_ as prefix to misc register bitmasks
> spear: Read ethaddr from I2C memory
> spear: Cleanup SoC area
> spear/spl: Cleanup spear SPL
> spear: Add POST memory support
> spear: Enable ehci support
> spear3xx: FIX: Enable access to memory for spear310 and spear320
> spear: Add cache support
> spear3xx: Add pinmux support
> spear320plc: Correct the MACB interface
> spear/configs: Modify several configurations
> spear320: Add support for SD/MMC
> spear320-hmi: Add support for hmi machine
> spear6xx/spear3xx: Add support to boot via NAND device
> spear/spl: Add support to boot from Parallel NOR device
> spear300evb: Add SPL support
> spear1340: Add support for spear1340 SoC
> spear1310: Add support for spear1310 SoC
> spear1340evb: Add support for evb machine
> spear1310evb: Add support for evb machine
> spear1340lcad: Add support for LCAD machine
> spear1340evb: Add SPL support
> spear1310evb: Add SPL support
>
> MAINTAINERS | 4 +
> Makefile | 10 +
> README | 6 +
> arch/arm/cpu/arm926ejs/spear/Makefile | 26 +-
> arch/arm/cpu/arm926ejs/spear/cache.c | 32 +
> arch/arm/cpu/arm926ejs/spear/cpu.c | 93 +-
> arch/arm/cpu/arm926ejs/spear/emi.c | 80 ++
> arch/arm/cpu/arm926ejs/spear/reset.c | 2 +-
> arch/arm/cpu/arm926ejs/spear/spear300.c | 140 +++
> arch/arm/cpu/arm926ejs/spear/spear310.c | 162 +++
> arch/arm/cpu/arm926ejs/spear/spear320.c | 860 ++++++++++++++++
> arch/arm/cpu/arm926ejs/spear/spear3xx.c | 130 +++
> arch/arm/cpu/arm926ejs/spear/spear600.c | 236 -----
> arch/arm/cpu/arm926ejs/spear/spear6xx.c | 43 +
> arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c | 171 ++++
> arch/arm/cpu/arm926ejs/spear/spl-spear600.c | 98 ++
> arch/arm/cpu/arm926ejs/spear/spl.c | 181 +---
> arch/arm/cpu/arm926ejs/spear/spl_boot.c | 206 +++-
> arch/arm/cpu/arm926ejs/spear/spl_nand.c | 121 +++
> arch/arm/cpu/arm926ejs/spear/start.S | 58 +-
> arch/arm/cpu/arm926ejs/spear/timer.c | 8 +-
> arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 65 +-
> arch/arm/cpu/armv7/Makefile | 17 +-
> arch/arm/cpu/armv7/ca9_ltimer.c | 154 +++
> arch/arm/cpu/armv7/spear13xx/Makefile | 71 ++
> arch/arm/cpu/armv7/spear13xx/reset.c | 47 +
> arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c | 860 ++++++++++++++++
> arch/arm/cpu/armv7/spear13xx/spear1310.c | 205 ++++
> arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c | 439 ++++++++
> arch/arm/cpu/armv7/spear13xx/spear1340.c | 270 +++++
> arch/arm/cpu/armv7/spear13xx/spear13xx.c | 62 ++
> arch/arm/cpu/armv7/spear13xx/spl-boot.c | 76 ++
> arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c | 239 +++++
> arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c | 229 +++++
> arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c | 608 +++++++++++
> arch/arm/cpu/armv7/spear13xx/spl-spear1310.c | 230 +++++
> arch/arm/cpu/armv7/spear13xx/spl-spear1340.c | 210 ++++
> arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c | 162 +++
> arch/arm/cpu/armv7/spear13xx/spl-swlvl.c | 93 ++
> arch/arm/cpu/armv7/spear13xx/start.S | 137 +++
> arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds | 45 +
> arch/arm/cpu/armv7/spear13xx/wakeup.S | 60 ++
> arch/arm/include/asm/arch-spear/bootrom_table.h | 54 +
> arch/arm/include/asm/arch-spear/clk.h | 5 +
> .../include/asm/arch-spear/{spr_emi.h => emi.h} | 8 +-
> arch/arm/include/asm/arch-spear/generic.h | 123 +++
> .../include/asm/arch-spear/{spr_gpt.h => gpt.h} | 4 +-
> arch/arm/include/asm/arch-spear/hardware.h | 78 +-
> .../include/asm/arch-spear/{spr_misc.h => misc.h} | 208 ++--
> .../include/asm/arch-spear/{spr_ssp.h => mmc.h} | 26 +-
> arch/arm/include/asm/arch-spear/pinmux.h | 133 +++
> arch/arm/include/asm/arch-spear/spear300.h | 83 ++
> arch/arm/include/asm/arch-spear/spear310.h | 75 ++
> arch/arm/include/asm/arch-spear/spear320.h | 490 +++++++++
> arch/arm/include/asm/arch-spear/spear3xx.h | 64 ++
> arch/arm/include/asm/arch-spear/spear600.h | 58 ++
> arch/arm/include/asm/arch-spear/spl_nand.h | 181 ++++
> arch/arm/include/asm/arch-spear/spl_pnor.h | 34 +
> arch/arm/include/asm/arch-spear/spr_defs.h | 69 --
> .../asm/arch-spear/{spr_syscntl.h => syscntl.h} | 21 +-
> arch/arm/include/asm/arch-spear13xx/boot.h | 106 ++
> arch/arm/include/asm/arch-spear13xx/c3.h | 63 ++
> arch/arm/include/asm/arch-spear13xx/generic.h | 41 +
> arch/arm/include/asm/arch-spear13xx/gpio.h | 42 +
> arch/arm/include/asm/arch-spear13xx/hardware.h | 33 +
> arch/arm/include/asm/arch-spear13xx/misc.h | 34 +
> arch/arm/include/asm/arch-spear13xx/mmc.h | 29 +
> arch/arm/include/asm/arch-spear13xx/mpmc.h | 332 ++++++
> arch/arm/include/asm/arch-spear13xx/pinmux.h | 114 +++
> arch/arm/include/asm/arch-spear13xx/spear1310.h | 244 +++++
> .../include/asm/arch-spear13xx/spear1310_misc.h | 358 +++++++
> arch/arm/include/asm/arch-spear13xx/spear1340.h | 159 +++
> .../include/asm/arch-spear13xx/spear1340_misc.h | 357 +++++++
> arch/arm/include/asm/arch-spear13xx/spear13xx.h | 50 +
> arch/arm/include/asm/ca9_ltimer.h | 40 +
> arch/arm/lib/board.c | 12 +
> board/spear/common/Makefile | 50 -
> board/spear/spear310/Makefile | 45 -
> board/{spear/spear600 => st/spear}/Makefile | 17 +-
> board/st/spear/config.mk | 27 +
> board/{spear/spear320 => st/spear/ddr}/Makefile | 23 +-
> .../ddr/spear600_mt47h128m8_3_266_cl5_async.c | 3 +-
> .../spear/ddr/spear600_mt47h32m16_333_cl5_psync.c | 8 +-
> .../ddr/spear600_mt47h32m16_37e_166_cl4_sync.c | 3 +-
> .../ddr/spear600_mt47h64m16_3_333_cl5_psync.c | 8 +-
> board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c | 140 +++
> .../spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c | 146 +++
> .../spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c | 146 +++
> .../spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c | 152 +++
> .../spear320/spear320.c => st/spear/spear300evb.c} | 56 +-
> .../spear310/spear310.c => st/spear/spear310evb.c} | 57 +-
> .../spear300/spear300.c => st/spear/spear320hmi.c} | 66 +-
> board/st/spear/spear320plc.c | 144 +++
> board/st/spear/spear600evb.c | 179 ++++
> .../common/spr_misc.c => st/spear/spear_common.c} | 175 +---
> .../spear/spear_lowlevel_init.S} | 14 -
> board/{spear/x600 => st/spear}/x600.c | 0
> board/{spear/x600/fpga.c => st/spear/x600fpga.c} | 0
> board/{spear/x600/fpga.h => st/spear/x600fpga.h} | 0
> board/{spear/x600 => st/spear13xx}/Makefile | 16 +-
> board/st/spear13xx/config.mk | 27 +
> .../{spear/spear300 => st/spear13xx/ddr}/Makefile | 25 +-
> board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c | 238 +++++
> board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c | 238 +++++
> board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c | 238 +++++
> board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c | 238 +++++
> .../ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c | 238 +++++
> .../ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c | 246 +++++
> .../ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c | 246 +++++
> .../ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c | 238 +++++
> .../ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c | 238 +++++
> .../spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c | 239 +++++
> .../spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c | 239 +++++
> board/st/spear13xx/spear1310evb.c | 93 ++
> board/st/spear13xx/spear1340evb.c | 94 ++
> .../spear600.c => st/spear13xx/spear1340lcad.c} | 60 +-
> board/st/spear13xx/spear13xx_common.c | 53 +
> board/st/spear13xx/spl-spear1310evb.c | 50 +
> board/st/spear13xx/spl-spear1340evb.c | 57 ++
> boards.cfg | 45 +-
> common/cmd_bootm.c | 98 ++
> common/usb_hub.c | 27 +-
> drivers/misc/Makefile | 1 +
> drivers/misc/c3.c | 122 +++
> drivers/mmc/Makefile | 1 +
> drivers/mmc/spear_sdhci.c | 44 +
> drivers/mtd/st_smi.c | 73 +-
> drivers/net/designware.c | 4 +-
> drivers/net/macb.c | 48 +-
> drivers/serial/usbtty.c | 2 +-
> drivers/serial/usbtty.h | 2 +
> drivers/spi/Makefile | 1 +
> drivers/spi/pl022_spi.c | 308 ++++++
> drivers/usb/gadget/Makefile | 1 +
> drivers/usb/gadget/designware_otg.c | 1063 ++++++++++++++++++++
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ehci-spear.c | 70 ++
> include/configs/spear-common.h | 251 -----
> include/configs/spear.h | 242 +++++
> include/configs/spear1310-evb.h | 118 +++
> include/configs/spear1310.h | 35 +
> include/configs/spear1340-evb.h | 124 +++
> include/configs/spear1340-lcad.h | 91 ++
> include/configs/spear1340.h | 30 +
> include/configs/spear13xx.h | 121 +++
> include/configs/spear300-evb.h | 114 +++
> include/configs/{spear6xx_evb.h => spear300.h} | 45 +-
> include/configs/spear310-evb.h | 145 +++
> include/configs/spear310.h | 76 ++
> include/configs/spear320-evb.h | 109 ++
> include/configs/spear320-hmi.h | 117 +++
> include/configs/spear320.h | 66 ++
> include/configs/spear3xx.h | 65 ++
> include/configs/spear3xx_evb.h | 173 ----
> include/configs/spear600-evb.h | 119 +++
> include/configs/spear600.h | 69 ++
> include/configs/x600.h | 2 +-
> include/linux/bitops.h | 12 +
> include/linux/mtd/st_smi.h | 1 -
> include/usb/designware_otg.h | 500 +++++++++
> include/usbdevice.h | 4 +-
> spl/Makefile | 11 +
> 162 files changed, 18111 insertions(+), 1684 deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/spear/cache.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/emi.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spear300.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spear310.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spear320.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spear3xx.c
> delete mode 100644 arch/arm/cpu/arm926ejs/spear/spear600.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spear6xx.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spl-spear3xx.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spl-spear600.c
> create mode 100644 arch/arm/cpu/arm926ejs/spear/spl_nand.c
> create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/Makefile
> create mode 100644 arch/arm/cpu/armv7/spear13xx/reset.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spear13xx.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-boot.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
> create mode 100644 arch/arm/cpu/armv7/spear13xx/start.S
> create mode 100644 arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
> create mode 100644 arch/arm/cpu/armv7/spear13xx/wakeup.S
> create mode 100644 arch/arm/include/asm/arch-spear/bootrom_table.h
> rename arch/arm/include/asm/arch-spear/{spr_emi.h => emi.h} (94%)
> create mode 100644 arch/arm/include/asm/arch-spear/generic.h
> rename arch/arm/include/asm/arch-spear/{spr_gpt.h => gpt.h} (97%)
> rename arch/arm/include/asm/arch-spear/{spr_misc.h => misc.h} (52%)
> rename arch/arm/include/asm/arch-spear/{spr_ssp.h => mmc.h} (69%)
> create mode 100644 arch/arm/include/asm/arch-spear/pinmux.h
> create mode 100644 arch/arm/include/asm/arch-spear/spear300.h
> create mode 100644 arch/arm/include/asm/arch-spear/spear310.h
> create mode 100644 arch/arm/include/asm/arch-spear/spear320.h
> create mode 100644 arch/arm/include/asm/arch-spear/spear3xx.h
> create mode 100644 arch/arm/include/asm/arch-spear/spear600.h
> create mode 100644 arch/arm/include/asm/arch-spear/spl_nand.h
> create mode 100644 arch/arm/include/asm/arch-spear/spl_pnor.h
> delete mode 100644 arch/arm/include/asm/arch-spear/spr_defs.h
> rename arch/arm/include/asm/arch-spear/{spr_syscntl.h => syscntl.h} (71%)
> create mode 100644 arch/arm/include/asm/arch-spear13xx/boot.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/c3.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/generic.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/gpio.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/misc.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/mmc.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/mpmc.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/pinmux.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
> create mode 100644 arch/arm/include/asm/arch-spear13xx/spear13xx.h
> create mode 100644 arch/arm/include/asm/ca9_ltimer.h
> delete mode 100644 board/spear/common/Makefile
> delete mode 100644 board/spear/spear310/Makefile
> rename board/{spear/spear600 => st/spear}/Makefile (74%)
> create mode 100644 board/st/spear/config.mk
> rename board/{spear/spear320 => st/spear/ddr}/Makefile (63%)
> rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c => board/st/spear/ddr/spear600_mt47h128m8_3_266_cl5_async.c (95%)
> rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c => board/st/spear/ddr/spear600_mt47h32m16_333_cl5_psync.c (91%)
> rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c => board/st/spear/ddr/spear600_mt47h32m16_37e_166_cl4_sync.c (95%)
> rename arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c => board/st/spear/ddr/spear600_mt47h64m16_3_333_cl5_psync.c (91%)
> create mode 100644 board/st/spear/ddr/spr3xx_mt46h32m16_6_166_cl3.c
> create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_166_cl4_async.c
> create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_266_cl5_async.c
> create mode 100644 board/st/spear/ddr/spr3xx_mt47h64m16_3_333_cl5_async.c
> rename board/{spear/spear320/spear320.c => st/spear/spear300evb.c} (69%)
> rename board/{spear/spear310/spear310.c => st/spear/spear310evb.c} (68%)
> rename board/{spear/spear300/spear300.c => st/spear/spear320hmi.c} (58%)
> create mode 100644 board/st/spear/spear320plc.c
> create mode 100644 board/st/spear/spear600evb.c
> rename board/{spear/common/spr_misc.c => st/spear/spear_common.c} (52%)
> rename board/{spear/common/spr_lowlevel_init.S => st/spear/spear_lowlevel_init.S} (88%)
> rename board/{spear/x600 => st/spear}/x600.c (100%)
> rename board/{spear/x600/fpga.c => st/spear/x600fpga.c} (100%)
> rename board/{spear/x600/fpga.h => st/spear/x600fpga.h} (100%)
> rename board/{spear/x600 => st/spear13xx}/Makefile (76%)
> create mode 100644 board/st/spear13xx/config.mk
> rename board/{spear/spear300 => st/spear13xx/ddr}/Makefile (57%)
> create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
> create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
> create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
> create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
> create mode 100644 board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
> create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
> create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
> create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
> create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
> create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
> create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
> create mode 100644 board/st/spear13xx/spear1310evb.c
> create mode 100644 board/st/spear13xx/spear1340evb.c
> rename board/{spear/spear600/spear600.c => st/spear13xx/spear1340lcad.c} (60%)
> create mode 100644 board/st/spear13xx/spear13xx_common.c
> create mode 100644 board/st/spear13xx/spl-spear1310evb.c
> create mode 100644 board/st/spear13xx/spl-spear1340evb.c
> create mode 100644 drivers/misc/c3.c
> create mode 100644 drivers/mmc/spear_sdhci.c
> create mode 100644 drivers/spi/pl022_spi.c
> create mode 100644 drivers/usb/gadget/designware_otg.c
> create mode 100644 drivers/usb/host/ehci-spear.c
> delete mode 100644 include/configs/spear-common.h
> create mode 100644 include/configs/spear.h
> create mode 100644 include/configs/spear1310-evb.h
> create mode 100644 include/configs/spear1310.h
> create mode 100644 include/configs/spear1340-evb.h
> create mode 100644 include/configs/spear1340-lcad.h
> create mode 100644 include/configs/spear1340.h
> create mode 100644 include/configs/spear13xx.h
> create mode 100644 include/configs/spear300-evb.h
> rename include/configs/{spear6xx_evb.h => spear300.h} (54%)
> create mode 100644 include/configs/spear310-evb.h
> create mode 100644 include/configs/spear310.h
> create mode 100644 include/configs/spear320-evb.h
> create mode 100644 include/configs/spear320-hmi.h
> create mode 100644 include/configs/spear320.h
> create mode 100644 include/configs/spear3xx.h
> delete mode 100644 include/configs/spear3xx_evb.h
> create mode 100644 include/configs/spear600-evb.h
> create mode 100644 include/configs/spear600.h
> create mode 100644 include/usb/designware_otg.h
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-12 10:35 ` Vipin Kumar
@ 2012-11-21 9:24 ` Wolfgang Denk
2012-11-30 11:15 ` Armando Visconti
0 siblings, 1 reply; 72+ messages in thread
From: Wolfgang Denk @ 2012-11-21 9:24 UTC (permalink / raw)
To: u-boot
Dear Vipin,
In message <50A0D0EB.4080403@st.com> you wrote:
>
> The ssh key is as below
THnaks a lot. The repository should be ready for your use now. Sorry
it took so long.
Please feel free to contact me directly if there should be any
problems.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I will also, for an appropriate fee, certify that your keyboard is
object-oriented, and that the bits on your hard disk are template-
compatible. - Jeffrey S. Haemer in <411akr$3ga@cygnus.com>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-21 9:24 ` Wolfgang Denk
@ 2012-11-30 11:15 ` Armando Visconti
2012-11-30 12:34 ` Wolfgang Denk
0 siblings, 1 reply; 72+ messages in thread
From: Armando Visconti @ 2012-11-30 11:15 UTC (permalink / raw)
To: u-boot
On 11/21/2012 10:24 AM, Wolfgang Denk wrote:
> Dear Vipin,
>
> In message<50A0D0EB.4080403@st.com> you wrote:
>>
>> The ssh key is as below
>
> THnaks a lot. The repository should be ready for your use now. Sorry
> it took so long.
>
> Please feel free to contact me directly if there should be any
> problems.
>
Wolfgang, Vipin,
Not sure what are next steps for this patchset.
Is someone going to review it, or part of it?
Or is Vipin expected to do something on the repository
assigned to him (maybe he already did)?
Thx for clarifying it...
Rgds,
Arm
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-30 11:15 ` Armando Visconti
@ 2012-11-30 12:34 ` Wolfgang Denk
2012-11-30 14:10 ` Armando Visconti
2012-12-03 5:51 ` Vipin Kumar
0 siblings, 2 replies; 72+ messages in thread
From: Wolfgang Denk @ 2012-11-30 12:34 UTC (permalink / raw)
To: u-boot
Dear Armando Visconti,
In message <50B89534.6040106@st.com> you wrote:
>
> Not sure what are next steps for this patchset.
> Is someone going to review it, or part of it?
>
> Or is Vipin expected to do something on the repository
> assigned to him (maybe he already did)?
Vipin volunteered as custodian, so the next step should be that he
performs a final review, applies the patches to his repo, and sends a
pullr equest to Albert.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The philosophy exam was a piece of cake - which was a bit of a
surprise, actually, because I was expecting some questions on a sheet
of paper.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-30 12:34 ` Wolfgang Denk
@ 2012-11-30 14:10 ` Armando Visconti
2012-12-03 5:51 ` Vipin Kumar
1 sibling, 0 replies; 72+ messages in thread
From: Armando Visconti @ 2012-11-30 14:10 UTC (permalink / raw)
To: u-boot
On 11/30/2012 01:34 PM, Wolfgang Denk wrote:
> Dear Armando Visconti,
>
> In message<50B89534.6040106@st.com> you wrote:
>>
>> Not sure what are next steps for this patchset.
>> Is someone going to review it, or part of it?
>>
>> Or is Vipin expected to do something on the repository
>> assigned to him (maybe he already did)?
>
> Vipin volunteered as custodian, so the next step should be that he
> performs a final review, applies the patches to his repo, and sends a
> pullr equest to Albert.
>
Clear.
Ciao,
Arm
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [PATCH 00/46] Enhance spear support
2012-11-30 12:34 ` Wolfgang Denk
2012-11-30 14:10 ` Armando Visconti
@ 2012-12-03 5:51 ` Vipin Kumar
1 sibling, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2012-12-03 5:51 UTC (permalink / raw)
To: u-boot
On 11/30/2012 6:04 PM, Wolfgang Denk wrote:
> Dear Armando Visconti,
>
> In message<50B89534.6040106@st.com> you wrote:
>>
>> Not sure what are next steps for this patchset.
>> Is someone going to review it, or part of it?
>>
>> Or is Vipin expected to do something on the repository
>> assigned to him (maybe he already did)?
>
> Vipin volunteered as custodian, so the next step should be that he
> performs a final review, applies the patches to his repo, and sends a
> pullr equest to Albert.
>
Yes, I am preparing the repository and I am going to send a pull request
very soon
Thanks
Vipin
> Best regards,
>
> Wolfgang Denk
>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue Vipin Kumar
@ 2013-02-03 11:19 ` Albert ARIBAUD
2013-02-28 12:59 ` Albert ARIBAUD
0 siblings, 1 reply; 72+ messages in thread
From: Albert ARIBAUD @ 2013-02-03 11:19 UTC (permalink / raw)
To: u-boot
Hi Vipin,
On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar <vipin.kumar@st.com>
wrote:
> From: Shiraz Hashim <shiraz.hashim@st.com>
>
> It is observed on SPEAr320S RMII#1 interface that on transmitting
> packets the MAC dma hangs randomly and constantly showing busy tx-go
> state.
>
> It comes out if this situation only when Transmission is disabled and
> enabled again.
>
> Since it happens randomly and u-boot doesn't require high performance we
> disable TE and re-enable it on each transmission. We also change number
> of transmit descriptor to 1 as we would not require more than it, further
> it would not alter GMAC notion of transmit descriptor start queue as it
> always point to same descriptor.
>
> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
> ---
> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
> 1 file changed, 34 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index ac25b52..17bad33 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -55,7 +55,7 @@
>
> #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
> #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
> -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
> +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
> #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
> #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
>
> @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
> macb->tx_ring[tx_head].ctrl = ctrl;
> macb->tx_ring[tx_head].addr = paddr;
> barrier();
> - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
> + /*
> + * Due to issues on SPEAr320 RMII, disable TE first so that
> + * controller can come out if it is hanged during transmission
> + */
> + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
> + macb_writel(macb, NCR, macb_readl(macb, NCR) |
> + MACB_BIT(TE) | MACB_BIT(TSTART));
>
> /*
> * I guess this is necessary because the networking core may
> @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
> }
> }
>
> +static void macb_reset_hw(struct macb_device *bp)
> +{
> + /* Make sure we have the write buffer for ourselves */
> + barrier();
> + /*
> + * Disable RX and TX (XXX: Should we halt the transmission
> + * more gracefully?) and we should not close the mdio port
> + */
> + macb_writel(bp, NCR, 0);
> +
> + /* Clear the stats registers (XXX: Update stats first?) */
> + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
> +
> + /* keep the mdio port , otherwise other eth will not work */
> + macb_writel(bp, NCR, MACB_BIT(MPE));
> +
> + /* Clear all status flags */
> + macb_writel(bp, TSR, ~0UL);
> + macb_writel(bp, RSR, ~0UL);
> +
> + /* Disable all interrupts */
> + macb_writel(bp, IDR, ~0UL);
> + macb_readl(bp, ISR);
> +}
> +
> static int macb_init(struct eth_device *netdev, bd_t *bd)
> {
> struct macb_device *macb = to_macb(netdev);
> @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
> tsr = macb_readl(macb, TSR);
> } while (tsr & MACB_BIT(TGO));
>
> - /* Disable TX and RX, and clear statistics */
> - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
> + macb_reset_hw(macb);
> }
>
> static int macb_write_hwaddr(struct eth_device *dev)
This patch did not reappear in later versions of the series, and no
other standalone patch seems to match it. Was it dropped?
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-02-03 11:19 ` Albert ARIBAUD
@ 2013-02-28 12:59 ` Albert ARIBAUD
2013-03-01 3:08 ` Bo Shen
2013-03-01 3:41 ` Vipin Kumar
0 siblings, 2 replies; 72+ messages in thread
From: Albert ARIBAUD @ 2013-02-28 12:59 UTC (permalink / raw)
To: u-boot
On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:
> Hi Vipin,
>
> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar <vipin.kumar@st.com>
> wrote:
>
> > From: Shiraz Hashim <shiraz.hashim@st.com>
> >
> > It is observed on SPEAr320S RMII#1 interface that on transmitting
> > packets the MAC dma hangs randomly and constantly showing busy tx-go
> > state.
> >
> > It comes out if this situation only when Transmission is disabled and
> > enabled again.
> >
> > Since it happens randomly and u-boot doesn't require high performance we
> > disable TE and re-enable it on each transmission. We also change number
> > of transmit descriptor to 1 as we would not require more than it, further
> > it would not alter GMAC notion of transmit descriptor start queue as it
> > always point to same descriptor.
> >
> > Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
> > ---
> > drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
> > 1 file changed, 34 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > index ac25b52..17bad33 100644
> > --- a/drivers/net/macb.c
> > +++ b/drivers/net/macb.c
> > @@ -55,7 +55,7 @@
> >
> > #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
> > #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
> > -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
> > +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
> > #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
> > #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
> >
> > @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
> > macb->tx_ring[tx_head].ctrl = ctrl;
> > macb->tx_ring[tx_head].addr = paddr;
> > barrier();
> > - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
> > + /*
> > + * Due to issues on SPEAr320 RMII, disable TE first so that
> > + * controller can come out if it is hanged during transmission
> > + */
> > + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
> > + macb_writel(macb, NCR, macb_readl(macb, NCR) |
> > + MACB_BIT(TE) | MACB_BIT(TSTART));
> >
> > /*
> > * I guess this is necessary because the networking core may
> > @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
> > }
> > }
> >
> > +static void macb_reset_hw(struct macb_device *bp)
> > +{
> > + /* Make sure we have the write buffer for ourselves */
> > + barrier();
> > + /*
> > + * Disable RX and TX (XXX: Should we halt the transmission
> > + * more gracefully?) and we should not close the mdio port
> > + */
> > + macb_writel(bp, NCR, 0);
> > +
> > + /* Clear the stats registers (XXX: Update stats first?) */
> > + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
> > +
> > + /* keep the mdio port , otherwise other eth will not work */
> > + macb_writel(bp, NCR, MACB_BIT(MPE));
> > +
> > + /* Clear all status flags */
> > + macb_writel(bp, TSR, ~0UL);
> > + macb_writel(bp, RSR, ~0UL);
> > +
> > + /* Disable all interrupts */
> > + macb_writel(bp, IDR, ~0UL);
> > + macb_readl(bp, ISR);
> > +}
> > +
> > static int macb_init(struct eth_device *netdev, bd_t *bd)
> > {
> > struct macb_device *macb = to_macb(netdev);
> > @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
> > tsr = macb_readl(macb, TSR);
> > } while (tsr & MACB_BIT(TGO));
> >
> > - /* Disable TX and RX, and clear statistics */
> > - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
> > + macb_reset_hw(macb);
> > }
> >
> > static int macb_write_hwaddr(struct eth_device *dev)
>
> This patch did not reappear in later versions of the series, and no
> other standalone patch seems to match it. Was it dropped?
Ping?
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-02-28 12:59 ` Albert ARIBAUD
@ 2013-03-01 3:08 ` Bo Shen
2013-03-01 3:40 ` Vipin Kumar
2013-03-01 3:41 ` Vipin Kumar
1 sibling, 1 reply; 72+ messages in thread
From: Bo Shen @ 2013-03-01 3:08 UTC (permalink / raw)
To: u-boot
Hi All,
On 02/28/2013 08:59 PM, Albert ARIBAUD wrote:
> On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
>
>> Hi Vipin,
>>
>> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar<vipin.kumar@st.com>
>> wrote:
>>
>>> From: Shiraz Hashim<shiraz.hashim@st.com>
>>>
>>> It is observed on SPEAr320S RMII#1 interface that on transmitting
>>> packets the MAC dma hangs randomly and constantly showing busy tx-go
>>> state.
>>>
>>> It comes out if this situation only when Transmission is disabled and
>>> enabled again.
>>>
>>> Since it happens randomly and u-boot doesn't require high performance we
>>> disable TE and re-enable it on each transmission. We also change number
>>> of transmit descriptor to 1 as we would not require more than it, further
>>> it would not alter GMAC notion of transmit descriptor start queue as it
>>> always point to same descriptor.
>>>
>>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
>>> ---
>>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 34 insertions(+), 4 deletions(-)
Tested on Atmel EK board. It works.
Tested-by: Bo Shen <voice.shen@atmel.com>
BTW, would this be implemented as a workaround only for SPEAr320S?
Best Regards,
Bo Shen
>>> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>>> index ac25b52..17bad33 100644
>>> --- a/drivers/net/macb.c
>>> +++ b/drivers/net/macb.c
>>> @@ -55,7 +55,7 @@
>>>
>>> #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
>>> #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
>>> -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
>>> +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
>>> #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
>>> #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
>>>
>>> @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
>>> macb->tx_ring[tx_head].ctrl = ctrl;
>>> macb->tx_ring[tx_head].addr = paddr;
>>> barrier();
>>> - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
>>> + /*
>>> + * Due to issues on SPEAr320 RMII, disable TE first so that
>>> + * controller can come out if it is hanged during transmission
>>> + */
>>> + macb_writel(macb, NCR, macb_readl(macb, NCR)& ~MACB_BIT(TE));
>>> + macb_writel(macb, NCR, macb_readl(macb, NCR) |
>>> + MACB_BIT(TE) | MACB_BIT(TSTART));
>>>
>>> /*
>>> * I guess this is necessary because the networking core may
>>> @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
>>> }
>>> }
>>>
>>> +static void macb_reset_hw(struct macb_device *bp)
>>> +{
>>> + /* Make sure we have the write buffer for ourselves */
>>> + barrier();
>>> + /*
>>> + * Disable RX and TX (XXX: Should we halt the transmission
>>> + * more gracefully?) and we should not close the mdio port
>>> + */
>>> + macb_writel(bp, NCR, 0);
>>> +
>>> + /* Clear the stats registers (XXX: Update stats first?) */
>>> + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
>>> +
>>> + /* keep the mdio port , otherwise other eth will not work */
>>> + macb_writel(bp, NCR, MACB_BIT(MPE));
>>> +
>>> + /* Clear all status flags */
>>> + macb_writel(bp, TSR, ~0UL);
>>> + macb_writel(bp, RSR, ~0UL);
>>> +
>>> + /* Disable all interrupts */
>>> + macb_writel(bp, IDR, ~0UL);
>>> + macb_readl(bp, ISR);
>>> +}
>>> +
>>> static int macb_init(struct eth_device *netdev, bd_t *bd)
>>> {
>>> struct macb_device *macb = to_macb(netdev);
>>> @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
>>> tsr = macb_readl(macb, TSR);
>>> } while (tsr& MACB_BIT(TGO));
>>>
>>> - /* Disable TX and RX, and clear statistics */
>>> - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
>>> + macb_reset_hw(macb);
>>> }
>>>
>>> static int macb_write_hwaddr(struct eth_device *dev)
>>
>> This patch did not reappear in later versions of the series, and no
>> other standalone patch seems to match it. Was it dropped?
>
> Ping?
>
> Amicalement,
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-03-01 3:08 ` Bo Shen
@ 2013-03-01 3:40 ` Vipin Kumar
2013-03-01 3:48 ` Bo Shen
0 siblings, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2013-03-01 3:40 UTC (permalink / raw)
To: u-boot
On 3/1/2013 8:38 AM, Bo Shen wrote:
> Hi All,
>
> On 02/28/2013 08:59 PM, Albert ARIBAUD wrote:
>> On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
>> <albert.u.boot@aribaud.net> wrote:
>>
>>> Hi Vipin,
>>>
>>> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar<vipin.kumar@st.com>
>>> wrote:
>>>
>>>> From: Shiraz Hashim<shiraz.hashim@st.com>
>>>>
>>>> It is observed on SPEAr320S RMII#1 interface that on transmitting
>>>> packets the MAC dma hangs randomly and constantly showing busy tx-go
>>>> state.
>>>>
>>>> It comes out if this situation only when Transmission is disabled and
>>>> enabled again.
>>>>
>>>> Since it happens randomly and u-boot doesn't require high
>>>> performance we
>>>> disable TE and re-enable it on each transmission. We also change number
>>>> of transmit descriptor to 1 as we would not require more than it,
>>>> further
>>>> it would not alter GMAC notion of transmit descriptor start queue as it
>>>> always point to same descriptor.
>>>>
>>>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
>>>> ---
>>>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
>>>> 1 file changed, 34 insertions(+), 4 deletions(-)
>
> Tested on Atmel EK board. It works.
>
> Tested-by: Bo Shen <voice.shen@atmel.com>
>
> BTW, would this be implemented as a workaround only for SPEAr320S?
>
Yes, The idea was to implement this only for spear320s
After your tested-by, I am thinking may be I can make a separate
workaround config which can be enabled by any board using this peripheral.
Is that OK?
Regards
Vipin
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-02-28 12:59 ` Albert ARIBAUD
2013-03-01 3:08 ` Bo Shen
@ 2013-03-01 3:41 ` Vipin Kumar
2013-03-01 7:28 ` Albert ARIBAUD
1 sibling, 1 reply; 72+ messages in thread
From: Vipin Kumar @ 2013-03-01 3:41 UTC (permalink / raw)
To: u-boot
On 2/28/2013 6:29 PM, Albert ARIBAUD wrote:
> On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
>
>> Hi Vipin,
>>
>> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar<vipin.kumar@st.com>
>> wrote:
>>
>>> From: Shiraz Hashim<shiraz.hashim@st.com>
>>>
>>> It is observed on SPEAr320S RMII#1 interface that on transmitting
>>> packets the MAC dma hangs randomly and constantly showing busy tx-go
>>> state.
>>>
>>> It comes out if this situation only when Transmission is disabled and
>>> enabled again.
>>>
>>> Since it happens randomly and u-boot doesn't require high performance we
>>> disable TE and re-enable it on each transmission. We also change number
>>> of transmit descriptor to 1 as we would not require more than it, further
>>> it would not alter GMAC notion of transmit descriptor start queue as it
>>> always point to same descriptor.
>>>
>>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
>>> ---
>>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 34 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>>> index ac25b52..17bad33 100644
>>> --- a/drivers/net/macb.c
>>> +++ b/drivers/net/macb.c
>>> @@ -55,7 +55,7 @@
>>>
>>> #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
>>> #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
>>> -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
>>> +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
>>> #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
>>> #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
>>>
>>> @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
>>> macb->tx_ring[tx_head].ctrl = ctrl;
>>> macb->tx_ring[tx_head].addr = paddr;
>>> barrier();
>>> - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
>>> + /*
>>> + * Due to issues on SPEAr320 RMII, disable TE first so that
>>> + * controller can come out if it is hanged during transmission
>>> + */
>>> + macb_writel(macb, NCR, macb_readl(macb, NCR)& ~MACB_BIT(TE));
>>> + macb_writel(macb, NCR, macb_readl(macb, NCR) |
>>> + MACB_BIT(TE) | MACB_BIT(TSTART));
>>>
>>> /*
>>> * I guess this is necessary because the networking core may
>>> @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
>>> }
>>> }
>>>
>>> +static void macb_reset_hw(struct macb_device *bp)
>>> +{
>>> + /* Make sure we have the write buffer for ourselves */
>>> + barrier();
>>> + /*
>>> + * Disable RX and TX (XXX: Should we halt the transmission
>>> + * more gracefully?) and we should not close the mdio port
>>> + */
>>> + macb_writel(bp, NCR, 0);
>>> +
>>> + /* Clear the stats registers (XXX: Update stats first?) */
>>> + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
>>> +
>>> + /* keep the mdio port , otherwise other eth will not work */
>>> + macb_writel(bp, NCR, MACB_BIT(MPE));
>>> +
>>> + /* Clear all status flags */
>>> + macb_writel(bp, TSR, ~0UL);
>>> + macb_writel(bp, RSR, ~0UL);
>>> +
>>> + /* Disable all interrupts */
>>> + macb_writel(bp, IDR, ~0UL);
>>> + macb_readl(bp, ISR);
>>> +}
>>> +
>>> static int macb_init(struct eth_device *netdev, bd_t *bd)
>>> {
>>> struct macb_device *macb = to_macb(netdev);
>>> @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
>>> tsr = macb_readl(macb, TSR);
>>> } while (tsr& MACB_BIT(TGO));
>>>
>>> - /* Disable TX and RX, and clear statistics */
>>> - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
>>> + macb_reset_hw(macb);
>>> }
>>>
>>> static int macb_write_hwaddr(struct eth_device *dev)
>>
>> This patch did not reappear in later versions of the series, and no
>> other standalone patch seems to match it. Was it dropped?
>
> Ping?
>
No, I have been busy with something. I would come back to the u-boot
development soon
Vipin
> Amicalement,
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-03-01 3:40 ` Vipin Kumar
@ 2013-03-01 3:48 ` Bo Shen
0 siblings, 0 replies; 72+ messages in thread
From: Bo Shen @ 2013-03-01 3:48 UTC (permalink / raw)
To: u-boot
Hi Vipin,
On 3/1/2013 11:40, Vipin Kumar wrote:
[Snip]
>>>>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
>>>>> ---
>>>>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
>>>>> 1 file changed, 34 insertions(+), 4 deletions(-)
>>
>> Tested on Atmel EK board. It works.
>>
>> Tested-by: Bo Shen <voice.shen@atmel.com>
>>
>> BTW, would this be implemented as a workaround only for SPEAr320S?
>>
>
> Yes, The idea was to implement this only for spear320s
> After your tested-by, I am thinking may be I can make a separate
> workaround config which can be enabled by any board using this peripheral.
>
> Is that OK?
Agree.
Best Regards,
Bo Shen
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-03-01 3:41 ` Vipin Kumar
@ 2013-03-01 7:28 ` Albert ARIBAUD
2013-03-01 7:55 ` Vipin Kumar
0 siblings, 1 reply; 72+ messages in thread
From: Albert ARIBAUD @ 2013-03-01 7:28 UTC (permalink / raw)
To: u-boot
Hi Vipin,
On Fri, 1 Mar 2013 09:11:33 +0530, Vipin Kumar <vipin.kumar@st.com>
wrote:
> On 2/28/2013 6:29 PM, Albert ARIBAUD wrote:
> > On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
> > <albert.u.boot@aribaud.net> wrote:
> >
> >> Hi Vipin,
> >>
> >> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar<vipin.kumar@st.com>
> >> wrote:
> >>
> >>> From: Shiraz Hashim<shiraz.hashim@st.com>
> >>>
> >>> It is observed on SPEAr320S RMII#1 interface that on transmitting
> >>> packets the MAC dma hangs randomly and constantly showing busy tx-go
> >>> state.
> >>>
> >>> It comes out if this situation only when Transmission is disabled and
> >>> enabled again.
> >>>
> >>> Since it happens randomly and u-boot doesn't require high performance we
> >>> disable TE and re-enable it on each transmission. We also change number
> >>> of transmit descriptor to 1 as we would not require more than it, further
> >>> it would not alter GMAC notion of transmit descriptor start queue as it
> >>> always point to same descriptor.
> >>>
> >>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
> >>> ---
> >>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
> >>> 1 file changed, 34 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >>> index ac25b52..17bad33 100644
> >>> --- a/drivers/net/macb.c
> >>> +++ b/drivers/net/macb.c
> >>> @@ -55,7 +55,7 @@
> >>>
> >>> #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
> >>> #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
> >>> -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
> >>> +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
> >>> #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
> >>> #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
> >>>
> >>> @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
> >>> macb->tx_ring[tx_head].ctrl = ctrl;
> >>> macb->tx_ring[tx_head].addr = paddr;
> >>> barrier();
> >>> - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
> >>> + /*
> >>> + * Due to issues on SPEAr320 RMII, disable TE first so that
> >>> + * controller can come out if it is hanged during transmission
> >>> + */
> >>> + macb_writel(macb, NCR, macb_readl(macb, NCR)& ~MACB_BIT(TE));
> >>> + macb_writel(macb, NCR, macb_readl(macb, NCR) |
> >>> + MACB_BIT(TE) | MACB_BIT(TSTART));
> >>>
> >>> /*
> >>> * I guess this is necessary because the networking core may
> >>> @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
> >>> }
> >>> }
> >>>
> >>> +static void macb_reset_hw(struct macb_device *bp)
> >>> +{
> >>> + /* Make sure we have the write buffer for ourselves */
> >>> + barrier();
> >>> + /*
> >>> + * Disable RX and TX (XXX: Should we halt the transmission
> >>> + * more gracefully?) and we should not close the mdio port
> >>> + */
> >>> + macb_writel(bp, NCR, 0);
> >>> +
> >>> + /* Clear the stats registers (XXX: Update stats first?) */
> >>> + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
> >>> +
> >>> + /* keep the mdio port , otherwise other eth will not work */
> >>> + macb_writel(bp, NCR, MACB_BIT(MPE));
> >>> +
> >>> + /* Clear all status flags */
> >>> + macb_writel(bp, TSR, ~0UL);
> >>> + macb_writel(bp, RSR, ~0UL);
> >>> +
> >>> + /* Disable all interrupts */
> >>> + macb_writel(bp, IDR, ~0UL);
> >>> + macb_readl(bp, ISR);
> >>> +}
> >>> +
> >>> static int macb_init(struct eth_device *netdev, bd_t *bd)
> >>> {
> >>> struct macb_device *macb = to_macb(netdev);
> >>> @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
> >>> tsr = macb_readl(macb, TSR);
> >>> } while (tsr& MACB_BIT(TGO));
> >>>
> >>> - /* Disable TX and RX, and clear statistics */
> >>> - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
> >>> + macb_reset_hw(macb);
> >>> }
> >>>
> >>> static int macb_write_hwaddr(struct eth_device *dev)
> >>
> >> This patch did not reappear in later versions of the series, and no
> >> other standalone patch seems to match it. Was it dropped?
> >
> > Ping?
> >
>
> No, I have been busy with something. I would come back to the u-boot
> development soon
Thanks. Following your discussion with Bo Shen, should I expect a new
version of this patch in the future, or does it stand as it is?
> Vipin
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue
2013-03-01 7:28 ` Albert ARIBAUD
@ 2013-03-01 7:55 ` Vipin Kumar
0 siblings, 0 replies; 72+ messages in thread
From: Vipin Kumar @ 2013-03-01 7:55 UTC (permalink / raw)
To: u-boot
On 3/1/2013 12:58 PM, Albert ARIBAUD wrote:
> Hi Vipin,
>
> On Fri, 1 Mar 2013 09:11:33 +0530, Vipin Kumar<vipin.kumar@st.com>
> wrote:
>
>> On 2/28/2013 6:29 PM, Albert ARIBAUD wrote:
>>> On Sun, 3 Feb 2013 12:19:26 +0100, Albert ARIBAUD
>>> <albert.u.boot@aribaud.net> wrote:
>>>
>>>> Hi Vipin,
>>>>
>>>> On Fri, 2 Nov 2012 23:09:59 +0530, Vipin Kumar<vipin.kumar@st.com>
>>>> wrote:
>>>>
>>>>> From: Shiraz Hashim<shiraz.hashim@st.com>
>>>>>
>>>>> It is observed on SPEAr320S RMII#1 interface that on transmitting
>>>>> packets the MAC dma hangs randomly and constantly showing busy tx-go
>>>>> state.
>>>>>
>>>>> It comes out if this situation only when Transmission is disabled and
>>>>> enabled again.
>>>>>
>>>>> Since it happens randomly and u-boot doesn't require high performance we
>>>>> disable TE and re-enable it on each transmission. We also change number
>>>>> of transmit descriptor to 1 as we would not require more than it, further
>>>>> it would not alter GMAC notion of transmit descriptor start queue as it
>>>>> always point to same descriptor.
>>>>>
>>>>> Signed-off-by: Shiraz Hashim<shiraz.hashim@st.com>
>>>>> ---
>>>>> drivers/net/macb.c | 38 ++++++++++++++++++++++++++++++++++----
>>>>> 1 file changed, 34 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>>>>> index ac25b52..17bad33 100644
>>>>> --- a/drivers/net/macb.c
>>>>> +++ b/drivers/net/macb.c
>>>>> @@ -55,7 +55,7 @@
>>>>>
>>>>> #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
>>>>> #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
>>>>> -#define CONFIG_SYS_MACB_TX_RING_SIZE 16
>>>>> +#define CONFIG_SYS_MACB_TX_RING_SIZE 1
>>>>> #define CONFIG_SYS_MACB_TX_TIMEOUT 1000
>>>>> #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
>>>>>
>>>>> @@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
>>>>> macb->tx_ring[tx_head].ctrl = ctrl;
>>>>> macb->tx_ring[tx_head].addr = paddr;
>>>>> barrier();
>>>>> - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
>>>>> + /*
>>>>> + * Due to issues on SPEAr320 RMII, disable TE first so that
>>>>> + * controller can come out if it is hanged during transmission
>>>>> + */
>>>>> + macb_writel(macb, NCR, macb_readl(macb, NCR)& ~MACB_BIT(TE));
>>>>> + macb_writel(macb, NCR, macb_readl(macb, NCR) |
>>>>> + MACB_BIT(TE) | MACB_BIT(TSTART));
>>>>>
>>>>> /*
>>>>> * I guess this is necessary because the networking core may
>>>>> @@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
>>>>> }
>>>>> }
>>>>>
>>>>> +static void macb_reset_hw(struct macb_device *bp)
>>>>> +{
>>>>> + /* Make sure we have the write buffer for ourselves */
>>>>> + barrier();
>>>>> + /*
>>>>> + * Disable RX and TX (XXX: Should we halt the transmission
>>>>> + * more gracefully?) and we should not close the mdio port
>>>>> + */
>>>>> + macb_writel(bp, NCR, 0);
>>>>> +
>>>>> + /* Clear the stats registers (XXX: Update stats first?) */
>>>>> + macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
>>>>> +
>>>>> + /* keep the mdio port , otherwise other eth will not work */
>>>>> + macb_writel(bp, NCR, MACB_BIT(MPE));
>>>>> +
>>>>> + /* Clear all status flags */
>>>>> + macb_writel(bp, TSR, ~0UL);
>>>>> + macb_writel(bp, RSR, ~0UL);
>>>>> +
>>>>> + /* Disable all interrupts */
>>>>> + macb_writel(bp, IDR, ~0UL);
>>>>> + macb_readl(bp, ISR);
>>>>> +}
>>>>> +
>>>>> static int macb_init(struct eth_device *netdev, bd_t *bd)
>>>>> {
>>>>> struct macb_device *macb = to_macb(netdev);
>>>>> @@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
>>>>> tsr = macb_readl(macb, TSR);
>>>>> } while (tsr& MACB_BIT(TGO));
>>>>>
>>>>> - /* Disable TX and RX, and clear statistics */
>>>>> - macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
>>>>> + macb_reset_hw(macb);
>>>>> }
>>>>>
>>>>> static int macb_write_hwaddr(struct eth_device *dev)
>>>>
>>>> This patch did not reappear in later versions of the series, and no
>>>> other standalone patch seems to match it. Was it dropped?
>>>
>>> Ping?
>>>
>>
>> No, I have been busy with something. I would come back to the u-boot
>> development soon
>
> Thanks. Following your discussion with Bo Shen, should I expect a new
> version of this patch in the future, or does it stand as it is?
>
A new version
Vipin
>> Vipin
>
> Amicalement,
^ permalink raw reply [flat|nested] 72+ messages in thread
end of thread, other threads:[~2013-03-01 7:55 UTC | newest]
Thread overview: 72+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <cover.1351876757.git.vipin.kumar@st.com>
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 01/19] mtd/st_smi: Clear error flags while initiating a fresh write Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 02/19] mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 03/19] mtd/st_smi: Avoid issuing multiple WE commands Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 04/19] mtd/st_smi: Write to flash in a tight loop Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 05/19] mtd/st_smi: Use page sizes respective to flash Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 06/19] usbh/ehci: Increase timeout for enumeration Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 07/19] sdhci: Add sdhci support for spear devices Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 08/19] net/designware: Do not select MIIPORT for RGMII interface Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 10/19] usb/gadget/designware_otg: Add support for designware otg Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 11/19] usb/host/ehci: Add support for EHCI on spear Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 12/19] usbtty: adapt buffers for large packet support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 13/19] net/macb: Add arch specific routine to get mdio control Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [Drivers PATCH 14/19] net/macb: workaround for transmission hang issue Vipin Kumar
2013-02-03 11:19 ` Albert ARIBAUD
2013-02-28 12:59 ` Albert ARIBAUD
2013-03-01 3:08 ` Bo Shen
2013-03-01 3:40 ` Vipin Kumar
2013-03-01 3:48 ` Bo Shen
2013-03-01 3:41 ` Vipin Kumar
2013-03-01 7:28 ` Albert ARIBAUD
2013-03-01 7:55 ` Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 15/19] misc/crypto: Add support for C3 Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 16/19] armv7/ltimer: Add support for local timer on armv7 cpus Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 17/19] imls: Add support to list images in NAND device Vipin Kumar
2012-11-06 23:30 ` Scott Wood
2012-11-07 5:15 ` Vipin Kumar
2012-11-07 20:49 ` Scott Wood
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 18/19] u-boot/spl: Add u-boot-spl.img to u-boot targets Vipin Kumar
2012-11-02 17:40 ` [U-Boot] [Drivers PATCH 19/19] arm/boards: Define a new config option CONFIG_BOOT_PARAMS_P Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 1/7] spear1340: Add support for spear1340 SoC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 2/7] spear1310: Add support for spear1310 SoC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 3/7] spear1340evb: Add support for evb machine Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 4/7] spear1310evb: " Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 5/7] spear1340lcad: Add support for LCAD machine Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 6/7] spear1340evb: Add SPL support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr13xx PATCH 7/7] spear1310evb: " Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 1/9] spear: Add cache support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 2/9] spear3xx: Add pinmux support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 3/9] spear320plc: Correct the MACB interface Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 4/9] spear/configs: Modify several configurations Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 5/9] spear320: Add support for SD/MMC Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 6/9] spear320-hmi: Add support for hmi machine Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 7/9] spear6xx/spear3xx: Add support to boot via NAND device Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 8/9] spear/spl: Add support to boot from Parallel NOR device Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Enhancement PATCH 9/9] spear300evb: Add SPL support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 01/11] SPEAr: Remove extra spear board configurations Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 02/11] spear/configs: Split config files hierarchically into plat, arch, soc and board Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 03/11] spear/include: Clean up the spear include files Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 04/11] spear/board: Cleanup spear related board files Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 05/11] spear: Append MISC_ as prefix to misc register bitmasks Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 06/11] spear: Read ethaddr from I2C memory Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 07/11] spear: Cleanup SoC area Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 08/11] spear/spl: Cleanup spear SPL Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 09/11] spear: Add POST memory support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 10/11] spear: Enable ehci support Vipin Kumar
2012-11-02 17:39 ` [U-Boot] [SPEAr Fixes PATCH 11/11] spear3xx: FIX: Enable access to memory for spear310 and spear320 Vipin Kumar
2012-11-07 14:10 ` [U-Boot] [PATCH 00/46] Enhance spear support Stefan Roese
2012-11-08 4:58 ` Vipin Kumar
2012-11-08 4:58 ` Vipin Kumar
[not found] ` <509CD19A.2060903@st.com>
2012-11-09 11:56 ` Stefan Roese
2012-11-10 8:48 ` Albert ARIBAUD
2012-11-11 6:11 ` Stefan Roese
2012-11-11 7:50 ` Wolfgang Denk
2012-11-11 17:49 ` Albert ARIBAUD
2012-11-12 9:34 ` Armando Visconti
2012-11-12 10:35 ` Vipin Kumar
2012-11-21 9:24 ` Wolfgang Denk
2012-11-30 11:15 ` Armando Visconti
2012-11-30 12:34 ` Wolfgang Denk
2012-11-30 14:10 ` Armando Visconti
2012-12-03 5:51 ` Vipin Kumar
2012-11-20 9:46 ` Vipin Kumar
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