[U-Boot] [PATCH] mx23: Add POWER and CLKCTRL register definitions

Marek Vasut
2012-11-25T02:54:20Z

Dear Otavio Salvador,

> On Sat, Nov 24, 2012 at 10:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Add register definitions for the i.MX23 power control block and
> > clock control block. These are essential for the basic bootstrap
> > of the i.MX23. Also, properly include them in imx-regs.h .
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
>
> Please don't merge it now as this has been already done in my branch with
> mx23.

I'm attaching a proper diff against your branch. There are multiple wrong and
missing bits in your branch. This patch is done by processing the FSL-provided
header file and cross-checking with the datasheet.

So, this patch is right, yours is wrong. Sorry.

--- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h 2012-10-01
02:46:18.000000000 +0200
+++ ../u-boot-imx/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
2012-11-25 00:55:43.299072391 +0100
@@ -1,8 +1,11 @@
/*
* Freescale i.MX23 CLKCTRL Register Definitions
*
- * Copyright (C) 2012 Otavio Salvador <otavio@ossystems.com.br>
- * on behalf of O.S. Systems Software LTDA.
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -28,7 +31,8 @@
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
- mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
+ uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
@@ -39,15 +43,13 @@
mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */

- uint32_t reserved[4];
-
- mxs_reg_32(hw_clkctrl_saif) /* 0x0c0 */
- mxs_reg_32(hw_clkctrl_tv) /* 0x0d0 */
- mxs_reg_32(hw_clkctrl_etm) /* 0x0e0 */
-
- mxs_reg_8(hw_clkctrl_frac0) /* 0x0f0 */
- mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
+ uint32_t reserved1[4];

+ mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
+ mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
+ mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
+ mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
+ mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
mxs_reg_32(hw_clkctrl_status) /* 0x130 */
@@ -87,11 +89,11 @@
#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
-#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 5)
+#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
#define CLKCTRL_CPU_DIV_CPU_OFFSET 0

-#define CLKCTRL_HBUS_ASM_BUSY (1 << 29)
+#define CLKCTRL_HBUS_BUSY (1 << 29)
#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28)
#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27)
#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
@@ -101,7 +103,7 @@
#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20)
-#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 18)
+#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
@@ -114,16 +116,25 @@
#define CLKCTRL_HBUS_DIV_OFFSET 0

#define CLKCTRL_XBUS_BUSY (1 << 31)
-#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 9)
+#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_XBUS_DIV_MASK 0x3ff
#define CLKCTRL_XBUS_DIV_OFFSET 0

#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
+#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30)
#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
+#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28)
+#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27)
#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
#define CLKCTRL_XTAL_DIV_UART_OFFSET 0

+#define CLKCTRL_PIX_CLKGATE (1 << 31)
+#define CLKCTRL_PIX_BUSY (1 << 29)
+#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12)
+#define CLKCTRL_PIX_DIV_MASK 0xfff
+#define CLKCTRL_PIX_DIV_OFFSET 0
+
#define CLKCTRL_SSP_CLKGATE (1 << 31)
#define CLKCTRL_SSP_BUSY (1 << 29)
#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
@@ -151,11 +162,23 @@
#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
#define CLKCTRL_EMI_DIV_EMI_OFFSET 0

-#define CLKCTRL_SAIF_CLKGATE (1 << 31)
-#define CLKCTRL_SAIF_BUSY (1 << 29)
-#define CLKCTRL_SAIF_DIV_FRAC_EN (1 << 16)
-#define CLKCTRL_SAIF_DIV_MASK 0xffff
-#define CLKCTRL_SAIF_DIV_OFFSET 0
+#define CLKCTRL_IR_CLKGATE (1 << 31)
+#define CLKCTRL_IR_AUTO_DIV (1 << 29)
+#define CLKCTRL_IR_IR_BUSY (1 << 28)
+#define CLKCTRL_IR_IROV_BUSY (1 << 27)
+#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16)
+#define CLKCTRL_IR_IROV_DIV_OFFSET 16
+#define CLKCTRL_IR_IR_DIV_MASK 0x3ff
+#define CLKCTRL_IR_IR_DIV_OFFSET 0
+
+#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
+#define CLKCTRL_SAIF0_BUSY (1 << 29)
+#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
+#define CLKCTRL_SAIF0_DIV_MASK 0xffff
+#define CLKCTRL_SAIF0_DIV_OFFSET 0
+
+#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31)
+#define CLKCTRL_TV_CLK_TV_GATE (1 << 30)

#define CLKCTRL_ETM_CLKGATE (1 << 31)
#define CLKCTRL_ETM_BUSY (1 << 29)
@@ -169,13 +192,14 @@
#define CLKCTRL_FRAC_FRAC_OFFSET 0
#define CLKCTRL_FRAC0_CPU 0
#define CLKCTRL_FRAC0_EMI 1
-#define CLKCTRL_FRAC0_IO1 2
+#define CLKCTRL_FRAC0_PIX 2
#define CLKCTRL_FRAC0_IO0 3
+#define CLKCTRL_FRAC1_VID 3

#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
-#define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5) /* FIXME:
bypass SSP0 and SSP1? */
+#define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5)
#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3)
#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1)
@@ -194,7 +218,4 @@
#define CLKCTRL_VERSION_STEP_MASK 0xffff
#define CLKCTRL_VERSION_STEP_OFFSET 0

-/* Compatibility */
-#define CLKCTRL_CLKSEQ_BYPASS_SSP0 CLKCTRL_CLKSEQ_BYPASS_SSP
-
#endif /* __MX23_REGS_CLKCTRL_H__ */

Best regards,
Marek Vasut