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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 9/9] x86: coreboot: Enable LPC TPM
Date: Mon, 26 Nov 2012 20:34:29 +0100	[thread overview]
Message-ID: <201211262034.29834.marex@denx.de> (raw)
In-Reply-To: <1353910336-7193-10-git-send-email-sjg@chromium.org>

Dear Simon Glass,

> Coreboot boards have an LPC TPM connected, so enable this.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v4:
> - Remove CONFIG_NO_RESET_CODE from coreboot.h since this is not needed
> 
> Changes in v3: None
> Changes in v2: None
> 
>  include/configs/coreboot.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
> index 4999477..362310f 100644
> --- a/include/configs/coreboot.h
> +++ b/include/configs/coreboot.h
> @@ -66,6 +66,10 @@
>  					 CONFIG_SYS_SCSI_MAX_LUN)
>  #endif
> 
> +/* Generic TPM interfaced through LPC bus */
> +#define CONFIG_GENERIC_LPC_TPM
> +#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
> +
>  /*-----------------------------------------------------------------------
>   * Real Time Clock Configuration
>   */

Good, so now we have LPC enabled, problem solved then ?

Best regards,
Marek Vasut

  reply	other threads:[~2012-11-26 19:34 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-11-26  6:12 [U-Boot] [PATCH v4 2/9] x86: Allow excluding reset vector code from u-boot Simon Glass
2012-11-26  6:12 ` [U-Boot] [PATCH v4 8/9] x86: Remove coreboot start16 code Simon Glass
2012-11-26  6:12 ` [U-Boot] [PATCH v4 9/9] x86: coreboot: Enable LPC TPM Simon Glass
2012-11-26 19:34   ` Marek Vasut [this message]
2012-11-26  6:53 ` [U-Boot] [PATCH v4 2/9] x86: Allow excluding reset vector code from u-boot Wolfgang Denk
2012-11-26  7:10   ` Simon Glass
2012-11-26  9:31     ` Wolfgang Denk

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