From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Mon, 26 Nov 2012 20:34:29 +0100 Subject: [U-Boot] [PATCH v4 9/9] x86: coreboot: Enable LPC TPM In-Reply-To: <1353910336-7193-10-git-send-email-sjg@chromium.org> References: <1353910336-7193-3-git-send-email-sjg@chromium.org> <1353910336-7193-10-git-send-email-sjg@chromium.org> Message-ID: <201211262034.29834.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Simon Glass, > Coreboot boards have an LPC TPM connected, so enable this. > > Signed-off-by: Simon Glass > --- > Changes in v4: > - Remove CONFIG_NO_RESET_CODE from coreboot.h since this is not needed > > Changes in v3: None > Changes in v2: None > > include/configs/coreboot.h | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h > index 4999477..362310f 100644 > --- a/include/configs/coreboot.h > +++ b/include/configs/coreboot.h > @@ -66,6 +66,10 @@ > CONFIG_SYS_SCSI_MAX_LUN) > #endif > > +/* Generic TPM interfaced through LPC bus */ > +#define CONFIG_GENERIC_LPC_TPM > +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 > + > /*----------------------------------------------------------------------- > * Real Time Clock Configuration > */ Good, so now we have LPC enabled, problem solved then ? Best regards, Marek Vasut