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From: Allen Martin <amartin@nvidia.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver
Date: Fri, 11 Jan 2013 19:40:00 -0800	[thread overview]
Message-ID: <20130112034000.GB27011@badger> (raw)
In-Reply-To: <50F0AAB6.8040009@wwwdotorg.org>

On Fri, Jan 11, 2013 at 04:13:42PM -0800, Stephen Warren wrote:
> On 01/11/2013 11:44 AM, Allen Martin wrote:
> > Add support for configuring tegra SPI driver from devicetree.
> > Support is keyed off CONFIG_OF_CONTROL.  Add entry in seaboard dts
> > file for spi controller to describe seaboard spi.
> 
> > diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
> 
> .dtsi changes would typically be in a separate patch.

ok

> 
> > +	spi at 7000c380 {
> > +		compatible = "nvidia,tegra20-sflash";
> > +		reg = <0x7000c380 0x80>;
> > +		interrupts = <0 39 0x04>;
> > +		nvidia,dma-request-selector = <&apbdma 11>;
> 
> > +		spi-max-frequency = <25000000>;
> 
> spi-max-frequency is board-specific; it should appear in the board .dts
> file not the SoC .dtsi file.

ok

> 
> > diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
> 
> > @@ -85,7 +91,41 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> >  	spi->slave.bus = bus;
> >  	spi->slave.cs = cs;
> >  	spi->freq = max_hz;
> > +#ifdef CONFIG_OF_CONTROL
> > +	int node = fdtdec_next_compatible(gd->fdt_blob, 0,
> > +					  COMPAT_NVIDIA_TEGRA20_SFLASH);
> 
> I assume this function gets called once, and hence the line above simply
> finds the first sflash node in the device tree. What if there's more
> than one node? There certainly can be more than one SPI controller,
> although perhaps the sflash controller only has one instance on any
> current chip and it's the other IP block ("SPI") that has multiple
> instances in practice.

SFLASH only exists in tegra20, and there is only one.  This driver can
only handle a single controller anyway.  I highly doubt there will
ever be another chip with an SFLASH controller, never mind more than
one, but if there is, this driver will need lots of modification to
support multiple.  All newer chips have SLINK controllers only.

This function can be called more than once, like if you type "sf
probe" multiple times, but it passes in 0 as the initial node offset,
so it will always return the first compatible node.  So theoretically
if there ever is a tegra with more than one SFLASH controller, with
this patch the driver will operate like it did before this patch, it
will support the first controller only.

-Allen
-- 
nvpublic

  reply	other threads:[~2013-01-12  3:40 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-11 18:44 [U-Boot] [PATCH 0/7] tegra: SPI drivers Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 1/7] tegra: fdt: add apbdma node Allen Martin
2013-01-12  0:08   ` Stephen Warren
2013-01-12  3:19     ` Allen Martin
2013-01-12  6:07       ` Stephen Warren
2013-01-12  6:49         ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver Allen Martin
2013-01-12  0:13   ` Stephen Warren
2013-01-12  3:40     ` Allen Martin [this message]
2013-01-11 18:44 ` [U-Boot] [PATCH 3/7] tegra30: add SBC1 to periph id mapping table Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 4/7] tegra30: fdt: add SPI SLINK nodes Allen Martin
2013-01-12  0:17   ` Stephen Warren
2013-01-12  3:42     ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 5/7] tegra: add addresses of SPI SLINK controllers Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 6/7] tegra: add SPI SLINK driver Allen Martin
2013-01-12  0:22   ` Stephen Warren
2013-01-12  3:58     ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 7/7] tegra: cardhu: config: enable SPI Allen Martin

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