From: Allen Martin <amartin@nvidia.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 6/7] tegra: add SPI SLINK driver
Date: Fri, 11 Jan 2013 19:58:08 -0800 [thread overview]
Message-ID: <20130112035808.GD27011@badger> (raw)
In-Reply-To: <50F0ACD6.7090301@wwwdotorg.org>
On Fri, Jan 11, 2013 at 04:22:46PM -0800, Stephen Warren wrote:
> On 01/11/2013 11:44 AM, Allen Martin wrote:
> > Add driver for tegra SPI "SLINK" style driver. This controller is
> > similar to the tegra20 SPI "SFLASH" controller. The difference is
> > that the SLINK controller is a genernal purpose SPI controller and the
> > SFLASH controller is special purpose and can only talk to FLASH
> > devices. In addition there are potentially many instances of an SLINK
> > controller on tegra and only a single instance of SFLASH. Tegra20 is
> > currently ths only version of tegra that instantiates an SFLASH
> > controller.
> >
> > This driver supports basic PIO mode of operation and is configurable
> > (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
> > devices per controller may be attached, although typically only a
> > single chip select line is exposed from tegra per controller so in
> > reality this is usually limited to 1.
> >
> > To enable this driver, use CONFIG_TEGRA_SLINK
>
> > diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra_slink.c
>
> > +void spi_init(void)
> > +{
> > + int node = 0, i;
> > + struct tegra_spi_ctrl *ctrl;
> > + for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
> > + ctrl = &spi_ctrls[i];
> > +#ifdef CONFIG_OF_CONTROL
>
> Is this ever false for Tegra upstream? I don't think so.
No, but I think it's worthwhile to keep it under #ifdef so this driver
could be used from the SPL if the need ever comes up. I tested by
forcing it off for this driver and it works.
>
> > + node = fdtdec_next_compatible(gd->fdt_blob, node,
> > + COMPAT_NVIDIA_TEGRA20_SLINK);
> > + if (!node)
> > + break;
> > + ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
> > + node, "reg");
> > + if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
> > + debug("%s: no slink register found\n", __func__);
> > + break;
>
> Shouldn't most of the "break"s in this loop be "continue"s, so that any
> other nodes can be parsed? After all, this loop is trying to initialize
> all SLINK controllers in the DT right?
True, and looking at this code I think the driver is going to do
something bad if any of the controllers are not fully specified and
you go to use it later. I think the controller structure needs a
"valid" flag.
-Allen
--
nvpublic
next prev parent reply other threads:[~2013-01-12 3:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-11 18:44 [U-Boot] [PATCH 0/7] tegra: SPI drivers Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 1/7] tegra: fdt: add apbdma node Allen Martin
2013-01-12 0:08 ` Stephen Warren
2013-01-12 3:19 ` Allen Martin
2013-01-12 6:07 ` Stephen Warren
2013-01-12 6:49 ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver Allen Martin
2013-01-12 0:13 ` Stephen Warren
2013-01-12 3:40 ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 3/7] tegra30: add SBC1 to periph id mapping table Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 4/7] tegra30: fdt: add SPI SLINK nodes Allen Martin
2013-01-12 0:17 ` Stephen Warren
2013-01-12 3:42 ` Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 5/7] tegra: add addresses of SPI SLINK controllers Allen Martin
2013-01-11 18:44 ` [U-Boot] [PATCH 6/7] tegra: add SPI SLINK driver Allen Martin
2013-01-12 0:22 ` Stephen Warren
2013-01-12 3:58 ` Allen Martin [this message]
2013-01-11 18:44 ` [U-Boot] [PATCH 7/7] tegra: cardhu: config: enable SPI Allen Martin
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