[U-Boot] [PATCH 03/10] mx23evk: Adjust DRAM control register to use full 128MB of RAM

Marek Vasut
2013-01-30T15:55:41Z

Dear Otavio Salvador,

> On Wed, Jan 30, 2013 at 1:38 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Otavio Salvador,
> >
> >> On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
> >> > Dear Otavio Salvador,
> >> >
> >> >> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of
> >> >> full 128MB of RAM.
> >> >>
> >> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> >> >
> >> > Just enable the full set for all in the generic memory register set
> >> > (dram_vals)?
> >>
> >> Per datasheet description it shouldn't be done for LQFP;
> >
> > LQFP package is missing pinmux for the other pins, so that's ok.
> >
> >> so the safest
> >> setting is to the default we're using as it will work for new boards
> >> and the chip select can be adjusted when need.
> >
> > And since the block inside the CPU is the same, just missing the pinmux,
> > it is also safe to enable all CS lines for default operation.
>
> If this is the case why they added the CS selector?

CS selector?

> The datasheet is
> clear about the different setting in BGA and LQFP.

It'd be nice if you gave a ref. into the datasheet where I can find such
information.

> I'd prefer if
> someone from Freescale could check if it would be safe to enable them
> all or not. Fabio? :-)

According to table 12-36 and 37.4 , EMI has two CE lines max (CE0N and CE1N). If
CE1 is not present on the smaller package, it's not a problem, since whenever
asserted, the MUX won't let the signal go further. Moreover, the CE line is
asserted only when particular memory area is accessed.

Thus, CS_MAP shall be 0x3 in default setup.

btw. this patch is misconfiguring INTAREF field which is not documented in the
commit message.

Best regards,
Marek Vasut