From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nishanth Menon <nm@ti.com>
Date: Mon, 4 Feb 2013 13:41:14 -0600
Subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for
 ES2.0 revision.
In-Reply-To: <1359988164-24840-2-git-send-email-r.sricharan@ti.com>
References: <1359988164-24840-1-git-send-email-r.sricharan@ti.com>
	<1359988164-24840-2-git-send-email-r.sricharan@ti.com>
Message-ID: <20130204194114.GA4740@kahuna>
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On 19:59-20130204, R Sricharan wrote:
> Adding the CPU detection suport for OMAP5430 and
> OMAP5432 ES2.0 SOCs.
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
>  arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
>  arch/arm/include/asm/arch-omap5/omap.h |    2 ++
>  arch/arm/include/asm/armv7.h           |    1 +
>  arch/arm/include/asm/omap_common.h     |    2 ++
>  4 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
> index dfc0e44..0d8c95d 100644
> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
> @@ -216,8 +216,17 @@ void init_omap_revision(void)
>  			break;
>  		}
>  		break;
> -	default:
> -		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> +	case MIDR_CORTEX_A15_R2P2:
> +		switch (readl(CONTROL_ID_CODE)) {
> +		case OMAP5430_CONTROL_ID_CODE_ES2_0:
> +			*omap_si_rev = OMAP5430_ES2_0;
> +			break;
> +		case OMAP5432_CONTROL_ID_CODE_ES2_0:
> +			*omap_si_rev = OMAP5432_ES2_0;
> +			break;
> +		default:
> +			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> +		}

A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse
ID fused in, why would we want to make it a standard to check ARM
revision *and then* cross verify against control fuse verification, *and
then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks
entirely.
>  	}
>  }
>  
> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
> index 873ccd7..71935d8 100644
> --- a/arch/arm/include/asm/arch-omap5/omap.h
> +++ b/arch/arm/include/asm/arch-omap5/omap.h
> @@ -57,7 +57,9 @@
>  
>  /* To be verified */
>  #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
> +#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
>  #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
> +#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
>  
>  /* STD_FUSE_PROD_ID_1 */
>  #define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218)
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index ad9a875..a73630b 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -33,6 +33,7 @@
>  
>  /* Cortex-A15 revisions */
>  #define MIDR_CORTEX_A15_R0P0	0x410FC0F0
> +#define MIDR_CORTEX_A15_R2P2	0x412FC0F2
>  
>  /* CCSIDR */
>  #define CCSIDR_LINE_SIZE_OFFSET		0
> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
> index 2115687..4599167 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -542,4 +542,6 @@ static inline u32 omap_revision(void)
>  #define OMAP5430_SILICON_ID_INVALID	0
>  #define OMAP5430_ES1_0	0x54300100
>  #define OMAP5432_ES1_0	0x54320100
> +#define OMAP5430_ES2_0  0x54300200
> +#define OMAP5432_ES2_0  0x54320200
>  #endif /* _OMAP_COMMON_H_ */
> -- 
> 1.7.9.5
> 
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-- 
Regards,
Nishanth Menon