* [U-Boot] [PATCH 2/3] arm: zynq: Add SLCR support with system reset
2013-02-04 14:36 [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Michal Simek
@ 2013-02-04 14:36 ` Michal Simek
2013-02-04 14:36 ` [U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C Michal Simek
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Michal Simek @ 2013-02-04 14:36 UTC (permalink / raw)
To: u-boot
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/cpu/armv7/zynq/Makefile | 1 +
arch/arm/cpu/armv7/zynq/cpu.c | 2 +
arch/arm/cpu/armv7/zynq/slcr.c | 63 ++++++++++++++++++++++++++++
arch/arm/include/asm/arch-zynq/hardware.h | 41 ++++++++++++++++++
arch/arm/include/asm/arch-zynq/sys_proto.h | 30 +++++++++++++
5 files changed, 137 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/slcr.c
create mode 100644 arch/arm/include/asm/arch-zynq/hardware.h
create mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 499ace4..388085d 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-y := timer.o
COBJS-y += cpu.o
+COBJS-y += slcr.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index ab615cc..91618d3 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,11 +21,13 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/arch/sys_proto.h>
inline void lowlevel_init(void) {}
void reset_cpu(ulong addr)
{
+ zynq_slcr_cpu_reset();
while (1)
;
}
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644
index 0000000..788a8fd
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+
+#define SLCR_LOCK_MAGIC 0x767B
+#define SLCR_UNLOCK_MAGIC 0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+ if (!slcr_lock)
+ writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+ if (slcr_lock)
+ writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+ /*
+ * Unlock the SLCR then reset the system.
+ * Note that this seems to require raw i/o
+ * functions or there's a lockup?
+ */
+ zynq_slcr_unlock();
+
+ /*
+ * Clear 0x0F000000 bits of reboot status register to workaround
+ * the FSBL not loading the bitstream after soft-reboot
+ * This is a temporary solution until we know more.
+ */
+ clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+ writel(1, &slcr_base->pss_rst_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
new file mode 100644
index 0000000..ad17b27
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+ u32 scl; /* 0x0 */
+ u32 slcr_lock; /* 0x4 */
+ u32 slcr_unlock; /* 0x8 */
+ u32 reserved1[125];
+ u32 pss_rst_ctrl; /* 0x200 */
+ u32 reserved2[21];
+ u32 reboot_status; /* 0x258 */
+};
+
+#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
new file mode 100644
index 0000000..e788900
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+
+#endif /* _SYS_PROTO_H_ */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C
2013-02-04 14:36 [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Michal Simek
2013-02-04 14:36 ` [U-Boot] [PATCH 2/3] arm: zynq: Add SLCR support with system reset Michal Simek
@ 2013-02-04 14:36 ` Michal Simek
2013-02-21 18:16 ` Albert ARIBAUD
2013-02-21 18:15 ` [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Albert ARIBAUD
2013-02-21 18:15 ` Albert ARIBAUD
3 siblings, 1 reply; 6+ messages in thread
From: Michal Simek @ 2013-02-04 14:36 UTC (permalink / raw)
To: u-boot
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/cpu/armv7/zynq/cpu.c | 26 +++++++++++++++-
arch/arm/include/asm/arch-zynq/hardware.h | 46 ++++++++++++++++++++++++++++-
2 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 91618d3..e8f4c19 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,9 +21,33 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, &devcfg_base->unlock);
+ writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, &slcr_base->ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0xFFFFFFFF, &slcr_base->trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, &slcr_base->ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, &slcr_base->ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index ad17b27..d0c69da 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -24,6 +24,8 @@
#define _ASM_ARCH_HARDWARE_H
#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPSS_SCU_BASEADDR 0xF8F00000
/* Reflect slcr offsets */
struct slcr_regs {
@@ -32,10 +34,52 @@ struct slcr_regs {
u32 slcr_unlock; /* 0x8 */
u32 reserved1[125];
u32 pss_rst_ctrl; /* 0x200 */
- u32 reserved2[21];
+ u32 reserved2[15];
+ u32 fpga_rst_ctrl; /* 0x240 */
+ u32 reserved3[5];
u32 reboot_status; /* 0x258 */
+ u32 boot_mode; /* 0x25c */
+ u32 reserved4[116];
+ u32 trust_zone; /* 0x430 */ /* FIXME */
+ u32 reserved5[115];
+ u32 ddr_urgent; /* 0x600 */
+ u32 reserved6[6];
+ u32 ddr_urgent_sel; /* 0x61c */
+ u32 reserved7[188];
+ u32 ocm_cfg; /* 0x910 */
};
#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+struct devcfg_regs {
+ u32 ctrl; /* 0x0 */
+ u32 lock; /* 0x4 */
+ u32 cfg; /* 0x8 */
+ u32 int_sts; /* 0xc */
+ u32 int_mask; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 dma_src_addr; /* 0x18 */
+ u32 dma_dst_addr; /* 0x1c */
+ u32 dma_src_len; /* 0x20 */
+ u32 dma_dst_len; /* 0x24 */
+ u32 rom_shadow; /* 0x28 */
+ u32 reserved1[2];
+ u32 unlock; /* 0x34 */
+ u32 reserved2[18];
+ u32 mctrl; /* 0x80 */
+ u32 reserved3;
+ u32 write_count; /* 0x88 */
+ u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+ u32 reserved1[16];
+ u32 filter_start; /* 0x40 */
+ u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C
2013-02-04 14:36 ` [U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C Michal Simek
@ 2013-02-21 18:16 ` Albert ARIBAUD
0 siblings, 0 replies; 6+ messages in thread
From: Albert ARIBAUD @ 2013-02-21 18:16 UTC (permalink / raw)
To: u-boot
Hi Michal,
On Mon, 4 Feb 2013 15:36:07 +0100, Michal Simek
<michal.simek@xilinx.com> wrote:
> Do lowlevel initialization directly in C. Zynq do not
> require to do it in asm.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> arch/arm/cpu/armv7/zynq/cpu.c | 26 +++++++++++++++-
> arch/arm/include/asm/arch-zynq/hardware.h | 46 ++++++++++++++++++++++++++++-
> 2 files changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
> index 91618d3..e8f4c19 100644
> --- a/arch/arm/cpu/armv7/zynq/cpu.c
> +++ b/arch/arm/cpu/armv7/zynq/cpu.c
> @@ -21,9 +21,33 @@
> * MA 02111-1307 USA
> */
> #include <common.h>
> +#include <asm/io.h>
> #include <asm/arch/sys_proto.h>
> +#include <asm/arch/hardware.h>
>
> -inline void lowlevel_init(void) {}
> +void lowlevel_init(void)
> +{
> + zynq_slcr_unlock();
> + /* remap DDR to zero, FILTERSTART */
> + writel(0, &scu_base->filter_start);
> +
> + /* Device config APB, unlock the PCAP */
> + writel(0x757BDF0D, &devcfg_base->unlock);
> + writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
> +
> + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
> + writel(0x1F, &slcr_base->ocm_cfg);
> + /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
> + writel(0x0, &slcr_base->fpga_rst_ctrl);
> + /* TZ_DDR_RAM, Set DDR trust zone non-secure */
> + writel(0xFFFFFFFF, &slcr_base->trust_zone);
> + /* Set urgent bits with register */
> + writel(0x0, &slcr_base->ddr_urgent_sel);
> + /* Urgent write, ports S2/S3 */
> + writel(0xC, &slcr_base->ddr_urgent);
> +
> + zynq_slcr_lock();
> +}
>
> void reset_cpu(ulong addr)
> {
> diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
> index ad17b27..d0c69da 100644
> --- a/arch/arm/include/asm/arch-zynq/hardware.h
> +++ b/arch/arm/include/asm/arch-zynq/hardware.h
> @@ -24,6 +24,8 @@
> #define _ASM_ARCH_HARDWARE_H
>
> #define XPSS_SYS_CTRL_BASEADDR 0xF8000000
> +#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
> +#define XPSS_SCU_BASEADDR 0xF8F00000
>
> /* Reflect slcr offsets */
> struct slcr_regs {
> @@ -32,10 +34,52 @@ struct slcr_regs {
> u32 slcr_unlock; /* 0x8 */
> u32 reserved1[125];
> u32 pss_rst_ctrl; /* 0x200 */
> - u32 reserved2[21];
> + u32 reserved2[15];
> + u32 fpga_rst_ctrl; /* 0x240 */
> + u32 reserved3[5];
> u32 reboot_status; /* 0x258 */
> + u32 boot_mode; /* 0x25c */
> + u32 reserved4[116];
> + u32 trust_zone; /* 0x430 */ /* FIXME */
> + u32 reserved5[115];
> + u32 ddr_urgent; /* 0x600 */
> + u32 reserved6[6];
> + u32 ddr_urgent_sel; /* 0x61c */
> + u32 reserved7[188];
> + u32 ocm_cfg; /* 0x910 */
> };
>
> #define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
>
> +struct devcfg_regs {
> + u32 ctrl; /* 0x0 */
> + u32 lock; /* 0x4 */
> + u32 cfg; /* 0x8 */
> + u32 int_sts; /* 0xc */
> + u32 int_mask; /* 0x10 */
> + u32 status; /* 0x14 */
> + u32 dma_src_addr; /* 0x18 */
> + u32 dma_dst_addr; /* 0x1c */
> + u32 dma_src_len; /* 0x20 */
> + u32 dma_dst_len; /* 0x24 */
> + u32 rom_shadow; /* 0x28 */
> + u32 reserved1[2];
> + u32 unlock; /* 0x34 */
> + u32 reserved2[18];
> + u32 mctrl; /* 0x80 */
> + u32 reserved3;
> + u32 write_count; /* 0x88 */
> + u32 read_count; /* 0x8c */
> +};
> +
> +#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
> +
> +struct scu_regs {
> + u32 reserved1[16];
> + u32 filter_start; /* 0x40 */
> + u32 filter_end; /* 0x44 */
> +};
> +
> +#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
> +
> #endif /* _ASM_ARCH_HARDWARE_H */
Applied to u-boot-arm/master via microblaze/mainline/arm, thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board
2013-02-04 14:36 [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Michal Simek
2013-02-04 14:36 ` [U-Boot] [PATCH 2/3] arm: zynq: Add SLCR support with system reset Michal Simek
2013-02-04 14:36 ` [U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C Michal Simek
@ 2013-02-21 18:15 ` Albert ARIBAUD
2013-02-21 18:15 ` Albert ARIBAUD
3 siblings, 0 replies; 6+ messages in thread
From: Albert ARIBAUD @ 2013-02-21 18:15 UTC (permalink / raw)
To: u-boot
Hi Michal,
On Mon, 4 Feb 2013 15:36:05 +0100, Michal Simek
<michal.simek@xilinx.com> wrote:
> Enable DCC driver for arm zynq platform to be compiled.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> boards.cfg | 1 +
> include/configs/zynq.h | 5 +++++
> 2 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/boards.cfg b/boards.cfg
> index 98f7a14..1d30a18 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -296,6 +296,7 @@ snowball arm armv7 snowball st-e
> kzm9g arm armv7 kzm9g kmc rmobile
> armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
> zynq arm armv7 zynq xilinx zynq
> +zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC
> socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
> actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
> actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> index 18fd76f..2989e72 100644
> --- a/include/configs/zynq.h
> +++ b/include/configs/zynq.h
> @@ -58,6 +58,11 @@
> #define CONFIG_ZYNQ_GEM
> #define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
>
> +#if defined(CONFIG_ZYNQ_DCC)
> +# define CONFIG_ARM_DCC
> +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
> +#endif
> +
> #define CONFIG_BOOTP_SERVERIP
> #define CONFIG_BOOTP_BOOTPATH
> #define CONFIG_BOOTP_GATEWAY
Applied to u-boot-arm/master via microblaze/mainline/arm, thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board
2013-02-04 14:36 [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Michal Simek
` (2 preceding siblings ...)
2013-02-21 18:15 ` [U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board Albert ARIBAUD
@ 2013-02-21 18:15 ` Albert ARIBAUD
3 siblings, 0 replies; 6+ messages in thread
From: Albert ARIBAUD @ 2013-02-21 18:15 UTC (permalink / raw)
To: u-boot
Hi Michal,
On Mon, 4 Feb 2013 15:36:05 +0100, Michal Simek
<michal.simek@xilinx.com> wrote:
> Enable DCC driver for arm zynq platform to be compiled.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> boards.cfg | 1 +
> include/configs/zynq.h | 5 +++++
> 2 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/boards.cfg b/boards.cfg
> index 98f7a14..1d30a18 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -296,6 +296,7 @@ snowball arm armv7 snowball st-e
> kzm9g arm armv7 kzm9g kmc rmobile
> armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
> zynq arm armv7 zynq xilinx zynq
> +zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC
> socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
> actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
> actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
> diff --git a/include/configs/zynq.h b/include/configs/zynq.h
> index 18fd76f..2989e72 100644
> --- a/include/configs/zynq.h
> +++ b/include/configs/zynq.h
> @@ -58,6 +58,11 @@
> #define CONFIG_ZYNQ_GEM
> #define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
>
> +#if defined(CONFIG_ZYNQ_DCC)
> +# define CONFIG_ARM_DCC
> +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
> +#endif
> +
> #define CONFIG_BOOTP_SERVERIP
> #define CONFIG_BOOTP_BOOTPATH
> #define CONFIG_BOOTP_GATEWAY
Applied to u-boot-arm/master via microblaze/mainline/arm, thanks!
Amicalement,
--
Albert.
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