From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Fri, 22 Mar 2013 16:57:25 +0100 Subject: [U-Boot] [RFC] command/cache: Add flush_cache command In-Reply-To: <514C6AB0.7090808@ti.com> References: <20130321192510.7C892200547@gemini.denx.de> <1363898082.31522.22@snotra> <20130322073035.66674cf5@lilith> <514C4BE8.10508@ti.com> <20130322140330.4DC04200546@gemini.denx.de> <514C6AB0.7090808@ti.com> Message-ID: <20130322165725.2982934f@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Tom, On Fri, 22 Mar 2013 10:29:04 -0400, Tom Rini wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On 03/22/2013 10:03 AM, Wolfgang Denk wrote: > > Dear Tom, > > > > In message <514C4BE8.10508@ti.com> you wrote: > >> > >> It seems like we're going around and around with one point not > >> being addressed. When using 'go', how do you know the size to > >> flush? And since Scott is talking about performance testing > >> apps, the cache should not be disabled (unless we expect all > >> standalone apps to enable the cache, in which case we need to > >> provide something in the jump table to make that easy and > >> document this change). > > > > I also wonder about this. To me it appears much easier to use a > > IH_TYPE_STANDALONE image, which 1) provides the needed size > > information and 2) can be used with bootm, so the required > > additional steps (flush caches, release CPU) can be handled in > > bootm subcommands. > > But that then circles us back to Scott's other point of "go" is broken > then and it is the recommended way to start standalone applications. I am not sure I understand how exactly go is broken, or how the bootm proposal from Wolfgang circles back to a brokennness of 'go'. I am not even sure of the exact scenario. How many cores are we dealing with here, and what does each core do in sequence? > Scott, part of the problem here is that we have multiple cores, yes? > Say core0 is the one that read things in from NOR to DDR, core1 is the > one that will be running things. That's one possible scenario but I would like more detail before we look for a solution. Amicalement, -- Albert.