From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wolfgang Denk Date: Fri, 22 Mar 2013 21:57:47 +0100 Subject: [U-Boot] [PATCH 16/21] T4240/eth: fix SGMII card PHY address In-Reply-To: <1363973052-25918-14-git-send-email-yorksun@freescale.com> References: <1363973052-25918-1-git-send-email-yorksun@freescale.com> <1363973052-25918-14-git-send-email-yorksun@freescale.com> Message-ID: <20130322205747.7A03F2014CE@gemini.denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear York Sun, In message <1363973052-25918-14-git-send-email-yorksun@freescale.com> you wrote: > From: Shaohui Xie > > QSGMII card assumed to be used by default, but if SGMII card is used, > it will use different PHY address, but we don't know which card is used > until we access PHY on the card. So we check the card type slot by slot, > if we can read a PHY ID by reading a SGMII PHY address on a slot, then > the slot must have a SGMII card pluged, we mark all ports on that slot, > and fix dts to use the SGMII card PHY address when doing dts fixup > for the marked ports. > > Signed-off-by: Shaohui Xie > --- > board/freescale/t4qds/eth.c | 137 +++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 133 insertions(+), 4 deletions(-) CHECK: Alignment should match open parenthesis #139: FILE: board/freescale/t4qds/eth.c:196: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy21"); CHECK: Alignment should match open parenthesis #144: FILE: board/freescale/t4qds/eth.c:201: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy22"); CHECK: Alignment should match open parenthesis #149: FILE: board/freescale/t4qds/eth.c:206: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy23"); CHECK: Alignment should match open parenthesis #154: FILE: board/freescale/t4qds/eth.c:211: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy24"); CHECK: Alignment should match open parenthesis #159: FILE: board/freescale/t4qds/eth.c:216: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy12"); CHECK: Alignment should match open parenthesis #165: FILE: board/freescale/t4qds/eth.c:221: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy14"); CHECK: Alignment should match open parenthesis #168: FILE: board/freescale/t4qds/eth.c:224: + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii4"); CHECK: Alignment should match open parenthesis #174: FILE: board/freescale/t4qds/eth.c:229: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy13"); CHECK: Alignment should match open parenthesis #177: FILE: board/freescale/t4qds/eth.c:232: + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii3"); CHECK: Alignment should match open parenthesis #182: FILE: board/freescale/t4qds/eth.c:237: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy41"); CHECK: Alignment should match open parenthesis #187: FILE: board/freescale/t4qds/eth.c:242: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy42"); CHECK: Alignment should match open parenthesis #192: FILE: board/freescale/t4qds/eth.c:247: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy43"); CHECK: Alignment should match open parenthesis #197: FILE: board/freescale/t4qds/eth.c:252: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy44"); CHECK: Alignment should match open parenthesis #202: FILE: board/freescale/t4qds/eth.c:257: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy32"); CHECK: Alignment should match open parenthesis #208: FILE: board/freescale/t4qds/eth.c:262: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy34"); CHECK: Alignment should match open parenthesis #211: FILE: board/freescale/t4qds/eth.c:265: + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii12"); CHECK: Alignment should match open parenthesis #217: FILE: board/freescale/t4qds/eth.c:270: + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy33"); CHECK: Alignment should match open parenthesis #220: FILE: board/freescale/t4qds/eth.c:273: + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii11"); CHECK: Alignment should match open parenthesis #241: FILE: board/freescale/t4qds/eth.c:350: + if (miiphy_read(mdio_names[i], + SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) { Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de A witty saying proves nothing, but saying something pointless gets people's attention.