[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[TENART Antoine]

Rename some CONFIG_TI814X to a more generic CONFIG_81XX
---
 Makefile                                |    2 +-
 arch/arm/cpu/armv7/Makefile             |    2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |    2 +-
 arch/arm/include/asm/arch-am33xx/cpu.h  |    2 +-
 arch/arm/include/asm/arch-am33xx/omap.h |    2 +-
 drivers/serial/ns16550.c                |    4 ++--
 spl/Makefile                            |    2 +-
 7 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 7273fa4..811e7b6 100644
--- a/Makefile
+++ b/Makefile
@@ -330,7 +330,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index c961247..9bb2837 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI81XX),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 55e82ba..8da8f91 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS	+= emif-common.o
 COBJS	+= vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 3d3a7c8..13c0667 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -54,7 +54,7 @@
 /* Reset control */
 #ifdef CONFIG_AM33XX
 #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
 #define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
 #endif
 #define PRM_RSTST			(PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index d28f9a8..1a1cc18 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -31,7 +31,7 @@
 #ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000
-#elif defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI81XX)
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000
 #endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 02bc85b..c949423 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-			defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+			defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
@@ -58,7 +58,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
 	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
-	defined(CONFIG_TI814X)
+	defined(CONFIG_TI81XX)
 
 #if defined(CONFIG_APTIX)
 	/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/spl/Makefile b/spl/Makefile
index c398a5f..8692f30 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -82,7 +82,7 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-- 
1.7.10.4

[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[Peter Korsgaard]

>>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:

 TENART> Rename some CONFIG_TI814X to a more generic CONFIG_81XX

Acked-by: Peter Korsgaard <jacmet@Sunsite.dk>

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[Tom Rini]

On Thu, Mar 28, 2013 at 06:14:34PM +0100, TENART Antoine wrote:

> Rename some CONFIG_TI814X to a more generic CONFIG_81XX

This is fine except it breaks bisectability, you need to also add
CONFIG_TI81XX to ti814x_evm.h at this point.

-- 
Tom
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[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[Peter Korsgaard]

>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

 Tom> On Thu, Mar 28, 2013 at 06:14:34PM +0100, TENART Antoine wrote:
 >> Rename some CONFIG_TI814X to a more generic CONFIG_81XX

 Tom> This is fine except it breaks bisectability, you need to also add
 Tom> CONFIG_TI81XX to ti814x_evm.h at this point.

It afaik already has it.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[TENART Antoine]

>   Tom>  This is fine except it breaks bisectability, you need to also add
>   Tom>  CONFIG_TI81XX to ti814x_evm.h at this point.
>
> It afaik already has it.
>

Yes, it was introduced by Matt Porter in "ti814x_evm: add ti814x evm 
board support" patch :
+#define CONFIG_TI81XX
+#define CONFIG_TI814X

[U-Boot] [PATCH 1/8] Prepare for TI816X : reuse existing code from TI814X

[Tom Rini]

On Fri, Mar 29, 2013 at 10:09:30AM +0100, TENART Antoine wrote:
> >   Tom>  This is fine except it breaks bisectability, you need to also add
> >   Tom>  CONFIG_TI81XX to ti814x_evm.h at this point.
> >
> > It afaik already has it.
> >
> 
> Yes, it was introduced by Matt Porter in "ti814x_evm: add ti814x evm 
> board support" patch :
> +#define CONFIG_TI81XX
> +#define CONFIG_TI814X

OK, thanks, forgot Matt already set the symbol.

-- 
Tom
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[U-Boot] [PATCH 2/8] Add TI816X mux definitions.

[TENART Antoine]

---
 arch/arm/include/asm/arch-am33xx/mux.h        |    2 +
 arch/arm/include/asm/arch-am33xx/mux_ti816x.h |  363 +++++++++++++++++++++++++
 2 files changed, 365 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 1c6b65f..4caa4d8 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -23,6 +23,8 @@
 #include <asm/arch/mux_am33xx.h>
 #elif defined(CONFIG_TI814X)
 #include <asm/arch/mux_ti814x.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/mux_ti816x.h>
 #endif
 
 struct module_pin_mux {
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
new file mode 100644
index 0000000..0fcd49e
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
@@ -0,0 +1,363 @@
+/*
+ * mux_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI816X_H_
+#define _MUX_TI816X_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)  \
+	__raw_writel(value, (CTRL_BASE + offset));
+
+#define PULLDOWN_EN (0x0 << 4)	/* Pull Down Selection */
+#define PULLUP_EN   (0x1 << 4)	/* Pull Up Selection */
+#define PULLUDEN    (0x0 << 3)	/* Pull up enabled */
+#define PULLUDDIS   (0x1 << 3)	/* Pull up disabled */
+#define MODE(val)		val /* used for Readability */
+
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+	int pincntl271;
+	int pincntl272;
+	int pincntl273;
+	int pincntl274;
+	int pincntl275;
+	int pincntl276;
+	int pincntl277;
+	int pincntl278;
+	int pincntl279;
+	int pincntl280;
+	int pincntl281;
+	int pincntl282;
+	int pincntl283;
+	int pincntl284;
+	int pincntl285;
+	int pincntl286;
+	int pincntl287;
+	int pincntl288;
+	int pincntl289;
+	int pincntl290;
+	int pincntl291;
+	int pincntl292;
+	int pincntl293;
+	int pincntl294;
+	int pincntl295;
+	int pincntl296;
+	int pincntl297;
+	int pincntl298;
+	int pincntl299;
+	int pincntl300;
+	int pincntl301;
+	int pincntl302;
+	int pincntl303;
+	int pincntl304;
+	int pincntl305;
+	int pincntl306;
+	int pincntl307;
+	int pincntl308;
+	int pincntl309;
+	int pincntl310;
+	int pincntl311;
+	int pincntl312;
+	int pincntl313;
+	int pincntl314;
+	int pincntl315;
+	int pincntl316;
+	int pincntl317;
+	int pincntl318;
+	int pincntl319;
+	int pincntl320;
+	int pincntl321;
+	int pincntl322;
+	int pincntl323;
+};
+
+#endif /* endif _MUX_TI816X_H_ */
-- 
1.7.10.4

[U-Boot] [PATCH 2/8] Add TI816X mux definitions.

[Peter Korsgaard]

>>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>

I just now noticed that you forgot to sign off on your patches (-s
option).

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 2/8] Add TI816X mux definitions.

[Tom Rini]

On Thu, Mar 28, 2013 at 10:04:40PM +0100, Peter Korsgaard wrote:
> >>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:
> 
> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
> 
> I just now noticed that you forgot to sign off on your patches (-s
> option).

Yes, please fix with a v2 of the series which also addreses the other
feedback as well.  Also, patches 2-7 can be squashed into a single "Add
ti816x support" patch.

-- 
Tom
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[U-Boot] [PATCH 2/8] Add TI816X mux definitions.

[TENART Antoine]

> Yes, please fix with a v2 of the series which also addreses the other
> feedback as well.  Also, patches 2-7 can be squashed into a single "Add
> ti816x support" patch.
>

Thanks for your review, I'll do a v2 following your advices.

[U-Boot] [PATCH 3/8] Add TI816X clocks definitions

[TENART Antoine]

---
 arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h |  173 ++++++++++++++++++++++
 2 files changed, 177 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index ecb5901..123cc61 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -19,6 +19,10 @@
 #ifndef _CLOCKS_H_
 #define _CLOCKS_H_
 
+#if defined(CONFIG_TI816X)
+#include <asm/arch/clocks_ti816x.h>
+#else
 #include <asm/arch/clocks_am33xx.h>
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
new file mode 100644
index 0000000..bcc035a
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
@@ -0,0 +1,173 @@
+/*
+ * clocks_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_TI816X_H_
+#define _CLOCKS_TI816X_H_
+
+/*
+ * In TI816x the 27MHz crystal generates various root clks (main pll, audio pll, video pll and ddr pll)
+ * From these root clks the SYSCLKs are generated by making use of dividers and multipliers
+ */
+
+#define FAPLL_K			8
+#define SYSCLK_2_DIV		1
+#define OSC_FREQ		27
+/*
+ * Values supported 400,531,675,796
+ *
+ * On TI8168 rev C, use 400 or 531 MHz !
+ */
+#define DDR_PLL_400
+
+/* Main PLL */
+#define MAIN_N			64
+#define MAIN_P			0x1
+#define MAIN_INTFREQ1		0x8
+#define MAIN_FRACFREQ1		0x800000
+#define MAIN_MDIV1		0x2
+#define MAIN_INTFREQ2		0xE
+#define MAIN_FRACFREQ2		0x0
+#define MAIN_MDIV2		0x1
+#define MAIN_INTFREQ3		0x8
+#define MAIN_FRACFREQ3		0xAAAAB0
+#define MAIN_MDIV3		0x3
+#define MAIN_INTFREQ4		0x9
+#define MAIN_FRACFREQ4		0x55554F
+#define MAIN_MDIV4		0x3
+#define MAIN_INTFREQ5		0x9
+#define MAIN_FRACFREQ5		0x374BC6
+#define MAIN_MDIV5		0xC
+#define MAIN_MDIV6		0x48
+#define MAIN_MDIV7		0x4
+
+/* DDR PLL */
+/* For 400 MHz */
+#if defined(DDR_PLL_400)
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x4
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+/* For 531 MHz */
+#if defined(DDR_PLL_531)
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x3
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+/* For 675 MHz */
+#if defined(DDR_PLL_675)
+#define DDR_N			50
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x9
+#define DDR_FRACFREQ2		0x0
+#define DDR_MDIV2		0x19
+#define DDR_INTFREQ3		0x13
+#define DDR_FRACFREQ3		0x800000
+#define DDR_MDIV3		0x2
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+/* For 796 MHz */
+#if defined(DDR_PLL_796)
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+/* Video PLL */
+#define VIDEO_N			110
+#define VIDEO_P			0x2
+#define VIDEO_INTFREQ1		0xB
+#define VIDEO_FRACFREQ1		0x0
+#define VIDEO_MDIV1		0x5
+#define VIDEO_INTFREQ2		0xA
+#define VIDEO_FRACFREQ2		0x0
+#define VIDEO_MDIV2		0x2
+#define VIDEO_INTFREQ3		0xA
+#define VIDEO_FRACFREQ3		0x0
+#define VIDEO_MDIV3		0x2
+
+/* Audio PLL */
+#define AUDIO_N			64
+#define AUDIO_P			0x19
+#define AUDIO_INTFREQ2		0xE
+#define AUDIO_FRACFREQ2		0x0
+#define AUDIO_MDIV2		0x4
+#define AUDIO_INTFREQ3		0x9
+#define AUDIO_FRACFREQ3		0x0
+#define AUDIO_MDIV3		0x5
+#define AUDIO_INTFREQ4		0x9
+#define AUDIO_FRACFREQ4		0xCBC148
+#define AUDIO_MDIV4		0x14
+#define AUDIO_INTFREQ5		0xD
+#define AUDIO_FRACFREQ5		0x800000
+#define AUDIO_MDIV5		0x14
+
+#endif	/* endif _CLOCKS_TI816X_H_ */
-- 
1.7.10.4

[U-Boot] [PATCH 3/8] Add TI816X clocks definitions

[Tom Rini]

On Thu, Mar 28, 2013 at 06:14:36PM +0100, TENART Antoine wrote:

> ---
>  arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
>  arch/arm/include/asm/arch-am33xx/clocks_ti816x.h |  173 ++++++++++++++++++++++
>  2 files changed, 177 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 4/8] Add TI816X ddr definitions

[TENART Antoine]

---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h        |    4 +
 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h |  250 ++++++++++++++++++++
 2 files changed, 254 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 15ca4c1..b959ba8 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -22,6 +22,10 @@
 #include <asm/arch/hardware.h>
 #include <asm/emif.h>
 
+#if defined(CONFIG_TI816X)
+#include <asm/arch/ddr_defs_ti816x.h>
+#endif
+
 /* AM335X EMIF Register values */
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
new file mode 100644
index 0000000..0853d7f
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
@@ -0,0 +1,250 @@
+/*
+ * ddr_defs_ti816x.h
+ *
+ * ddr specific header for TI816X
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _DDR_DEFS_TI816X_H
+#define _DDR_DEFS_TI816X_H
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+
+#define CONFIG_TI816X_DDR3_796			/* Values supported 400,531,675,796 */
+#define CONFIG_TI816X_DDR3_SW_LEVELING	/* Enable software leveling as part of DDR3 init*/
+
+/*
+ * DDR3 force values.  These are board dependent
+ */
+
+/* EVM 400 MHz clock Settings
+ * EVM has only a single RANK (chip select) */
+#define N_RANK			1
+
+/*
+ * Invert clock adds an additional half cycle delay on the command
+ * interface.  The additional half cycle, is usually meant to enable
+ * leveling in the situation that DQS is later than CK on the board.  It
+ * also helps provide some additional margin for leveling.
+ *
+ * For the EVM this is helping us with additional room for the write
+ * leveling.  Since the dqs delays are very small.
+ */
+#define INVERT_CLOCK		1
+
+/*
+ * CMD_SLAVE_RATIO determines where is the command placed with respect
+ * to the clock edge.  This is a ratio, implying 0x100 is one cycle.
+ * Ideally the command is centered so - this should be half cycle
+ * delay (0x80).  But if invert clock is in use, an additional half
+ * cycle must be added
+ */
+#define CMD_SLAVE_FROM_INV_CLOCK(i) (((i) == 0) ? 0x80 : 0x100)
+#define CMD_SLAVE_RATIO		CMD_SLAVE_FROM_INV_CLOCK(INVERT_CLOCK)
+
+/*
+ * This represents the initial value for the leveling process.  The
+ * value is a ratio - so 0x100 represents one cycle.  The real delay
+ * is determined through the leveling process.
+ *
+ * During the leveling process, 0x20 is subtracted from the value, so
+ * we have added that to the value we want to set.  We also set the
+ * values such that byte3 completes leveling after byte2 and byte1
+ * after byte0.
+ */
+#define WR_DQS_RATIO_0		0x20
+#define WR_DQS_RATIO_1		0x20
+#define WR_DQS_RATIO_2		0x20
+#define WR_DQS_RATIO_3		0x20
+
+/*
+ * This represents the initial value for the leveling process.  The
+ * value is a ratio - so 0x100 represents one cycle.  The real delay
+ * is determined through the leveling process.
+ *
+ * During the leveling process, 0x20 is subtracted from the value, so
+ * we have added that to the value we want to set.  We also set the
+ * values such that byte3 completes leveling after byte2 and byte1
+ * after byte0.
+ */
+#define RD_GATE_RATIO_0	0x20
+#define RD_GATE_RATIO_1	0x20
+#define RD_GATE_RATIO_2	0x20
+#define RD_GATE_RATIO_3	0x20
+
+/*
+ * data rate in MHz.  The DDR clock will be 1/2 of this value
+ */
+#define DDR_DATA_RATE	800
+
+#define USE_EMIF0		1
+#define USE_EMIF1		1
+
+/*
+ * EMIF Paramters.  Refer the EMIF register documentation and the
+ * memory datasheet for details
+ */
+/* For 400 MHz */
+#if defined(CONFIG_TI816X_DDR3_400)
+#define EMIF_TIM1    0x0CCCE524
+#define EMIF_TIM2    0x30308023
+#define EMIF_TIM3    0x009F82CF
+#define EMIF_SDREF   0x10000C30
+#define EMIF_SDCFG   0x62A41032
+#define EMIF_PHYCFG  0x0000010B
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE		0x12A
+#define RD_DQS			0x3B
+#define WR_DQS			0xA6
+#endif
+
+#endif	/* CONFIG_TI816X_DDR3_400 */
+
+/* For 531 MHz */
+#if defined(CONFIG_TI816X_DDR3_531)
+#define EMIF_TIM1    0x0EF136AC
+#define EMIF_TIM2    0x30408063
+#define EMIF_TIM3    0x009F83AF
+#define EMIF_SDREF   0x1000102E
+#define EMIF_SDCFG   0x62A51832
+#define EMIF_PHYCFG  0x0000010C
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE		0x13D
+#define RD_DQS			0x39
+#define WR_DQS			0xB4
+#endif
+
+#endif /* CONFIG_TI816X_DDR_531 */
+
+/* For 675 MHz */
+#if defined(CONFIG_TI816X_DDR3_675)
+#define EMIF_TIM1    0x13358875
+#define EMIF_TIM2    0x5051806C
+#define EMIF_TIM3    0x009F84AF
+#define EMIF_SDREF   0x10001491
+#define EMIF_SDCFG   0x62A63032
+#define EMIF_PHYCFG  0x0000010F
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE		0x196
+#define RD_DQS			0x39
+#define WR_DQS			0x91
+
+#endif
+
+#endif /* CONFIG_TI816X_DDR3_675 */
+
+/* For 796 MHz */
+#if defined(CONFIG_TI816X_DDR3_796)
+#define EMIF_TIM1   0x1779C9FE
+#define EMIF_TIM2   0x50608074
+#define EMIF_TIM3   0x009F857F
+#define EMIF_SDREF  0x10001841
+#define EMIF_SDCFG  0x62A73832
+#define EMIF_PHYCFG 0x00000110
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE		0x1B3
+#define RD_DQS			0x35
+#define WR_DQS			0x93
+
+#endif
+
+#endif /* CONFIG_TI816X_DDR_796 */
+
+
+#if defined(CONFIG_TI816X_DDR3_SW_LEVELING)
+#define WR_DQS_RATIO_BYTE_LANE3	((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE2	((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE1	((WR_DQS << 10) | WR_DQS)
+#define WR_DQS_RATIO_BYTE_LANE0	((WR_DQS << 10) | WR_DQS)
+
+#define WR_DATA_RATIO_BYTE_LANE3	(((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE2	(((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE1	(((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE0	(((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40))
+
+#define RD_DQS_RATIO			((RD_DQS << 10) | RD_DQS)
+
+#define DQS_GATE_BYTE_LANE0		((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE1		((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE2		((RD_DQS_GATE << 10) | RD_DQS_GATE)
+#define DQS_GATE_BYTE_LANE3		((RD_DQS_GATE << 10) | RD_DQS_GATE)
+
+#endif	/* CONFIG_TI816X_DDR3_SW_LEVELING */
+
+#endif	/* CONFIG_TI816X_EVM_DDR3 */
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+
+#define INVERT_CLK_OUT		0x0
+#define CMD_SLAVE_RATIO		0x80
+/*
+ * DDR2 ratio values.  These are board dependent
+ * obtained from sweep experiments
+ */
+
+/* EVM 400 MHz clock Settings */
+
+#define WR_DQS_RATIO_BYTE_LANE3	((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE2	((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE1	((0x4a << 10) | 0x4a)
+#define WR_DQS_RATIO_BYTE_LANE0	((0x4a << 10) | 0x4a)
+
+#define WR_DATA_RATIO_BYTE_LANE3	(((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE2	(((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE1	(((0x4a + 0x40) << 10) | (0x4a + 0x40))
+#define WR_DATA_RATIO_BYTE_LANE0	(((0x4a + 0x40) << 10) | (0x4a + 0x40))
+
+#define RD_DQS_RATIO			((0x40 << 10) | 0x40)
+
+#define DQS_GATE_BYTE_LANE0		((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE1		((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE2		((0x13a << 10) | 0x13a)
+#define DQS_GATE_BYTE_LANE3		((0x13a << 10) | 0x13a)
+
+/*
+ * EMIF Paramters
+ */
+#define EMIF_TIM1    0xAAB15E2
+#define EMIF_TIM2    0x423631D2
+#define EMIF_TIM3    0x80032F
+#define EMIF_SDREF   0x10000C30
+#define EMIF_SDCFG   0x43801A3A  /* 32 bit ddr2, CL=6, CWL=5, 13 rows, 8 banks, 10 bit column, 2 CS */
+/*
+ * TI816x PG1.0 EMIF_PHYCFG 0x0000030B   local odt = 3, read latency = 11
+ * TI816x PG1.1 EMIF_PHYCFG 0x0000010B   local odt = 1, read latency = 11
+ */
+#define EMIF_PHYCFG  (pg_val_ti816x(0x0000030B, 0x0000010B))
+
+#endif	/* CONFIG_TI816X_EVM_DDR2 */
+#endif  /* _DDR_DEFS_TI816X_H */
-- 
1.7.10.4

[U-Boot] [PATCH 4/8] Add TI816X ddr definitions

[Tom Rini]

On Thu, Mar 28, 2013 at 06:14:37PM +0100, TENART Antoine wrote:

[snip]
> +#define CONFIG_TI816X_DDR3_796			/* Values supported 400,531,675,796 */
> +#define CONFIG_TI816X_DDR3_SW_LEVELING	/* Enable software leveling as part of DDR3 init*/

Lines too long.  Please run tools/checkpatch.pl on the whole series,
thanks!

-- 
Tom
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[U-Boot] [PATCH 5/8] Add TI816X cpu definitions

[TENART Antoine]

---
 arch/arm/include/asm/arch-am33xx/cpu.h        |    4 +
 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h |  269 +++++++++++++++++++++++++
 arch/arm/include/asm/emif.h                   |    4 +
 3 files changed, 277 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 13c0667..34b3aa9 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -25,6 +25,10 @@
 
 #include <asm/arch/hardware.h>
 
+#if defined(CONFIG_TI816X)
+#include <asm/arch/cpu_ti816x.h>
+#endif
+
 #define BIT(x)				(1 << x)
 #define CL_BIT(x)			(0 << x)
 
diff --git a/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
new file mode 100644
index 0000000..b4a13a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
@@ -0,0 +1,269 @@
+/*
+ * cpu_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _TI816X_CPU_H
+#define _TI816X_CPU_H
+
+#include <asm/arch/hardware.h>
+
+/* Timer registers */
+#define TIMER_TCLR			0x38		/* Timer control register */
+#define TIMER_TCRR			0x3C		/* Timer counter register */
+#define TIMER_TLDR			0x40		/* Timer load value register*/
+
+/* Control */
+#define CONTROL_STATUS		(CTRL_BASE + 0x40)
+
+/* device type */
+#define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE			0x0
+#define EMU_DEVICE			0x1
+#define HS_DEVICE			0x2
+#define GP_DEVICE			0x3
+
+/* This gives the buswidth of the booting device */
+#define SYSBOOT_BW_POS		(16)
+#define SYSBOOT_BW_MASK		(BIT(SYSBOOT_BW_POS))
+
+/* Reset control */
+#define PRM_DEVICE_RSTCTRL	(PRCM_BASE + 0x00A0)
+
+/* TI816X specific bits for PRM_DEVICE module */
+#define GLOBAL_RST_COLD		BIT(1)
+
+/* PLL related registers */
+#define MAINPLL_CTRL		(CTRL_BASE + 0x0400)
+#define MAINPLL_PWD			(CTRL_BASE + 0x0404)
+#define MAINPLL_FREQ1		(CTRL_BASE + 0x0408)
+#define MAINPLL_DIV1		(CTRL_BASE + 0x040C)
+#define MAINPLL_FREQ2		(CTRL_BASE + 0x0410)
+#define MAINPLL_DIV2		(CTRL_BASE + 0x0414)
+#define MAINPLL_FREQ3		(CTRL_BASE + 0x0418)
+#define MAINPLL_DIV3		(CTRL_BASE + 0x041C)
+#define MAINPLL_FREQ4		(CTRL_BASE + 0x0420)
+#define MAINPLL_DIV4		(CTRL_BASE + 0x0424)
+#define MAINPLL_FREQ5		(CTRL_BASE + 0x0428)
+#define MAINPLL_DIV5		(CTRL_BASE + 0x042C)
+#define MAINPLL_DIV6		(CTRL_BASE + 0x0434)
+#define MAINPLL_DIV7		(CTRL_BASE + 0x043C)
+
+#define DDRPLL_CTRL			(CTRL_BASE + 0x0440)
+#define DDRPLL_PWD			(CTRL_BASE + 0x0444)
+#define DDRPLL_DIV1			(CTRL_BASE + 0x044C)
+#define DDRPLL_FREQ2		(CTRL_BASE + 0x0450)
+#define DDRPLL_DIV2			(CTRL_BASE + 0x0454)
+#define DDRPLL_FREQ3		(CTRL_BASE + 0x0458)
+#define DDRPLL_DIV3			(CTRL_BASE + 0x045C)
+#define DDRPLL_FREQ4		(CTRL_BASE + 0x0460)
+#define DDRPLL_DIV4			(CTRL_BASE + 0x0464)
+#define DDRPLL_FREQ5		(CTRL_BASE + 0x0468)
+#define DDRPLL_DIV5			(CTRL_BASE + 0x046C)
+
+#define DDR_RCD				(CTRL_BASE + 0x070C)
+
+#define VIDEOPLL_CTRL		(CTRL_BASE + 0x0470)
+#define VIDEOPLL_PWD		(CTRL_BASE + 0x0474)
+#define VIDEOPLL_FREQ1		(CTRL_BASE + 0x0478)
+#define VIDEOPLL_DIV1		(CTRL_BASE + 0x047C)
+#define VIDEOPLL_FREQ2		(CTRL_BASE + 0x0480)
+#define VIDEOPLL_DIV2		(CTRL_BASE + 0x0484)
+#define VIDEOPLL_FREQ3		(CTRL_BASE + 0x0488)
+#define VIDEOPLL_DIV3		(CTRL_BASE + 0x048C)
+
+#define AUDIOPLL_CTRL		(CTRL_BASE + 0x04A0)
+#define AUDIOPLL_PWD		(CTRL_BASE + 0x04A4)
+#define AUDIOPLL_FREQ2		(CTRL_BASE + 0x04B0)
+#define AUDIOPLL_DIV2		(CTRL_BASE + 0x04B4)
+#define AUDIOPLL_FREQ3		(CTRL_BASE + 0x04B8)
+#define AUDIOPLL_DIV3		(CTRL_BASE + 0x04BC)
+#define AUDIOPLL_FREQ4		(CTRL_BASE + 0x04C0)
+#define AUDIOPLL_DIV4		(CTRL_BASE + 0x04C4)
+#define AUDIOPLL_FREQ5		(CTRL_BASE + 0x04C8)
+#define AUDIOPLL_DIV5		(CTRL_BASE + 0x04CC)
+
+/* PRCM */
+#define CM_DPLL_OFFSET		(PRCM_BASE + 0x0300)
+
+#ifdef CONFIG_TI816X
+#define CM_TIMER1_CLKSEL	(CM_DPLL_OFFSET + 0x90)
+
+/* Timers */
+#define CM_ALWON_TIMER_0_CLKCTRL	(PRCM_BASE + 0x156C)
+#define CM_ALWON_TIMER_1_CLKCTRL	(PRCM_BASE + 0x1570)
+#define CM_ALWON_TIMER_2_CLKCTRL	(PRCM_BASE + 0x1574)
+#define CM_ALWON_TIMER_3_CLKCTRL	(PRCM_BASE + 0x1578)
+#define CM_ALWON_TIMER_4_CLKCTRL	(PRCM_BASE + 0x157C)
+#define CM_ALWON_TIMER_5_CLKCTRL	(PRCM_BASE + 0x1580)
+#define CM_ALWON_TIMER_6_CLKCTRL	(PRCM_BASE + 0x1584)
+#define CM_ALWON_TIMER_7_CLKCTRL	(PRCM_BASE + 0x1588)
+#endif
+
+#define CM_ALWON_WDTIMER_CLKCTRL	(PRCM_BASE + 0x158C)
+#define CM_ALWON_SPI_CLKCTRL		(PRCM_BASE + 0x1590)
+#define CM_ALWON_CONTROL_CLKCTRL	(PRCM_BASE + 0x15C4)
+
+#define CM_ALWON_L3_SLOW_CLKSTCTRL	(PRCM_BASE + 0x1400)
+
+#ifdef CONFIG_TI816X
+#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
+#endif
+
+#define CM_ALWON_GPIO_0_CLKCTRL		(PRCM_BASE + 0x155c)
+#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (PRCM_BASE + 0x155c)
+
+#define CM_ALWON_GPIO_1_CLKCTRL		(PRCM_BASE + 0x1560)
+/* Ethernet */
+#define CM_ETHERNET_CLKSTCTRL		(PRCM_BASE + 0x1404)
+#define CM_ALWON_ETHERNET_0_CLKCTRL	(PRCM_BASE + 0x15D4)
+#define CM_ALWON_ETHERNET_1_CLKCTRL	(PRCM_BASE + 0x15D8)
+
+/* UARTs */
+#define CM_ALWON_UART_0_CLKCTRL		(PRCM_BASE + 0x1550)
+#define CM_ALWON_UART_1_CLKCTRL		(PRCM_BASE + 0x1554)
+#define CM_ALWON_UART_2_CLKCTRL		(PRCM_BASE + 0x1558)
+
+/* I2C */
+/* Note: In ti814x I2C0 and I2C2 have common clk control */
+#define CM_ALWON_I2C_0_CLKCTRL		(PRCM_BASE + 0x1564)
+
+/* HSMMC */
+#ifdef CONFIG_TI816X
+#define CM_ALWON_HSMMC_CLKCTRL		(PRCM_BASE + 0x15B0)
+#endif
+
+/* UART registers */
+#define UART_SYSCFG			(DEFAULT_UART_BASE + 0x54)
+#define UART_SYSSTS			(DEFAULT_UART_BASE + 0x58)
+#define UART_LCR			(DEFAULT_UART_BASE + 0x0C)
+#define UART_EFR			(DEFAULT_UART_BASE + 0x08)
+#define UART_MCR			(DEFAULT_UART_BASE + 0x10)
+#define UART_SCR			(DEFAULT_UART_BASE + 0x40)
+#define UART_TCR			(DEFAULT_UART_BASE + 0x18)
+#define UART_FCR			(DEFAULT_UART_BASE + 0x08)
+#define UART_DLL			(DEFAULT_UART_BASE + 0x00)
+#define UART_DLH			(DEFAULT_UART_BASE + 0x04)
+#define UART_MDR			(DEFAULT_UART_BASE + 0x20)
+
+/*DMM & EMIF4 MMR Declaration*/
+#define DMM_LISA_MAP__0			(DMM_BASE + 0x40)
+#define DMM_LISA_MAP__1			(DMM_BASE + 0x44)
+#define DMM_LISA_MAP__2			(DMM_BASE + 0x48)
+#define DMM_LISA_MAP__3			(DMM_BASE + 0x4C)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x460)
+
+#define EMIF4_0_SDRAM_ZQCR				(EMIF4_0_CFG_BASE + 0xC8)
+#define EMIF4_0_SDRAM_CONFIG			(EMIF4_0_CFG_BASE + 0x08)
+#define EMIF4_0_SDRAM_CONFIG2			(EMIF4_0_CFG_BASE + 0x0C)
+#define EMIF4_0_SDRAM_REF_CTRL			(EMIF4_0_CFG_BASE + 0x10)
+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW	(EMIF4_0_CFG_BASE + 0x14)
+#define EMIF4_0_SDRAM_TIM_1				(EMIF4_0_CFG_BASE + 0x18)
+#define EMIF4_0_SDRAM_TIM_1_SHADOW		(EMIF4_0_CFG_BASE + 0x1C)
+#define EMIF4_0_SDRAM_TIM_2				(EMIF4_0_CFG_BASE + 0x20)
+#define EMIF4_0_SDRAM_TIM_2_SHADOW		(EMIF4_0_CFG_BASE + 0x24)
+#define EMIF4_0_SDRAM_TIM_3				(EMIF4_0_CFG_BASE + 0x28)
+#define EMIF4_0_SDRAM_TIM_3_SHADOW		(EMIF4_0_CFG_BASE + 0x2C)
+#define EMIF4_0_DDR_PHY_CTRL_1			(EMIF4_0_CFG_BASE + 0xE4)
+#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW	(EMIF4_0_CFG_BASE + 0xE8)
+#define EMIF4_0_IODFT_TLGC				(EMIF4_0_CFG_BASE + 0x60)
+
+#define EMIF4_1_SDRAM_ZQCR				(EMIF4_1_CFG_BASE + 0xC8)
+#define EMIF4_1_SDRAM_CONFIG			(EMIF4_1_CFG_BASE + 0x08)
+#define EMIF4_1_SDRAM_CONFIG2			(EMIF4_1_CFG_BASE + 0x0C)
+#define EMIF4_1_SDRAM_REF_CTRL			(EMIF4_1_CFG_BASE + 0x10)
+#define EMIF4_1_SDRAM_REF_CTRL_SHADOW	(EMIF4_1_CFG_BASE + 0x14)
+#define EMIF4_1_SDRAM_TIM_1				(EMIF4_1_CFG_BASE + 0x18)
+#define EMIF4_1_SDRAM_TIM_1_SHADOW		(EMIF4_1_CFG_BASE + 0x1C)
+#define EMIF4_1_SDRAM_TIM_2				(EMIF4_1_CFG_BASE + 0x20)
+#define EMIF4_1_SDRAM_TIM_2_SHADOW		(EMIF4_1_CFG_BASE + 0x24)
+#define EMIF4_1_SDRAM_TIM_3				(EMIF4_1_CFG_BASE + 0x28)
+#define EMIF4_1_SDRAM_TIM_3_SHADOW		(EMIF4_1_CFG_BASE + 0x2C)
+#define EMIF4_1_DDR_PHY_CTRL_1			(EMIF4_1_CFG_BASE + 0xE4)
+#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW	(EMIF4_1_CFG_BASE + 0xE8)
+#define EMIF4_1_IODFT_TLGC				(EMIF4_1_CFG_BASE + 0x60)
+
+/*EMIF4 PRCM Defintion*/
+#define CM_DEFAULT_L3_FAST_CLKSTCTRL	(PRCM_BASE + 0x0508)
+#define CM_DEFAULT_EMIF_0_CLKCTRL		(PRCM_BASE + 0x0520)
+#define CM_DEFAULT_EMIF_1_CLKCTRL		(PRCM_BASE + 0x0524)
+#define CM_DEFAULT_DMM_CLKCTRL			(PRCM_BASE + 0x0528)
+#define CM_DEFAULT_FW_CLKCTRL			(PRCM_BASE + 0x052C)
+
+/* Smartreflex Registers */
+#define TI816X_SMRT_SCALE_ADDR		(CTRL_BASE + 0x06A0)
+#define TI816X_SMRT_OPP_SVT_ADDR	(CTRL_BASE + 0x06A8)
+#define TI816X_SMRT_OPP_HVT_ADDR	(CTRL_BASE + 0x06AC)
+
+
+/* ALWON PRCM */
+#define CM_ALWON_OCMC_0_CLKSTCTRL	(PRCM_BASE + 0x1414)
+#define CM_ALWON_OCMC_0_CLKCTRL		(PRCM_BASE + 0x15B4)
+#define CM_ALWON_OCMC_1_CLKSTCTRL	(PRCM_BASE + 0x1418)
+#define CM_ALWON_OCMC_1_CLKCTRL		(PRCM_BASE + 0x15B8)
+
+#define CM_ALWON_GPMC_CLKCTRL		(PRCM_BASE + 0x15D0)
+
+/* OCMC */
+#define SRAM0_SIZE				(0x40000)
+#define SRAM_GPMC_STACK_SIZE	(0x40)
+
+/* GPMC related */
+#define GPMC_CONFIG_CS0			(0x60)
+#define GPMC_CONFIG_CS0_BAS		(GPMC_BASE + GPMC_CONFIG_CS0)
+#define GPMC_CONFIG1			(0x00)
+#define GPMC_CONFIG2			(0x04)
+#define GPMC_CONFIG3			(0x08)
+#define GPMC_CONFIG4			(0x0C)
+#define GPMC_CONFIG5			(0x10)
+#define GPMC_CONFIG6			(0x14)
+#define GPMC_CONFIG7			(0x18)
+
+/* WDT related */
+#define WDT_WDSC		(WDT_BASE + 0x010)
+#define WDT_WDST		(WDT_BASE + 0x014)
+#define WDT_WISR		(WDT_BASE + 0x018)
+#define WDT_WIER		(WDT_BASE + 0x01C)
+#define WDT_WWER		(WDT_BASE + 0x020)
+#define WDT_WCLR		(WDT_BASE + 0x024)
+#define WDT_WCRR		(WDT_BASE + 0x028)
+#define WDT_WLDR		(WDT_BASE + 0x02C)
+#define WDT_WTGR		(WDT_BASE + 0x030)
+#define WDT_WWPS		(WDT_BASE + 0x034)
+#define WDT_WDLY		(WDT_BASE + 0x044)
+#define WDT_WSPR		(WDT_BASE + 0x048)
+#define WDT_WIRQEOI		(WDT_BASE + 0x050)
+#define WDT_WIRQSTATRAW	(WDT_BASE + 0x054)
+#define WDT_WIRQSTAT	(WDT_BASE + 0x058)
+#define WDT_WIRQENSET	(WDT_BASE + 0x05C)
+#define WDT_WIRQENCLR	(WDT_BASE + 0x060)
+
+#define WDT_UNFREEZE	(CTRL_BASE + 0x100)
+
+#endif /* _TI816X_CPU_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec..a7b938c 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -521,7 +521,11 @@
 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
 
 /* DMM */
+#if defined(CONFIG_TI816X)
+#define DMM_BASE			0x4E000000
+#else
 #define DMM_BASE			0x4E000040
+#endif
 
 /* Memory Adapter */
 #define MA_BASE				0x482AF040
-- 
1.7.10.4

[U-Boot] [PATCH 5/8] Add TI816X cpu definitions

[Peter Korsgaard]

>>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:

 TENART> ---
 TENART>  arch/arm/include/asm/arch-am33xx/cpu.h        |    4 +
 TENART>  arch/arm/include/asm/arch-am33xx/cpu_ti816x.h |  269 +++++++++++++++++++++++++
 TENART>  arch/arm/include/asm/emif.h                   |    4 +
 TENART>  3 files changed, 277 insertions(+)
 TENART>  create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h

 TENART> diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
 TENART> index 13c0667..34b3aa9 100644
 TENART> --- a/arch/arm/include/asm/arch-am33xx/cpu.h
 TENART> +++ b/arch/arm/include/asm/arch-am33xx/cpu.h
 TENART> @@ -25,6 +25,10 @@
 
 TENART>  #include <asm/arch/hardware.h>
 
 TENART> +#if defined(CONFIG_TI816X)
 TENART> +#include <asm/arch/cpu_ti816x.h>
 TENART> +#endif
 TENART> +
 TENART>  #define BIT(x)				(1 << x)
 TENART>  #define CL_BIT(x)			(0 << x)
 
 TENART> diff --git a/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
 TENART> new file mode 100644
 TENART> index 0000000..b4a13a8
 TENART> --- /dev/null
 TENART> +++ b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
 TENART> @@ -0,0 +1,269 @@
 TENART> +/*
 TENART> + * cpu_ti816x.h
 TENART> + *
 TENART> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
 TENART> + * Antoine Tenart, <atenart@adeneo-embedded.com>
 TENART> + *
 TENART> + * Based on TI-PSP-04.00.02.14 :
 TENART> + *
 TENART> + * (C) Copyright 2006
 TENART> + * Texas Instruments, <www.ti.com>
 TENART> + *
 TENART> + * See file CREDITS for list of people who contributed to this
 TENART> + * project.
 TENART> + *
 TENART> + * This program is free software; you can redistribute it and/or
 TENART> + * modify it under the terms of the GNU General Public License as
 TENART> + * published by the Free Software Foundation; either version 2 of
 TENART> + * the License, or (at your option) any later version.
 TENART> + *
 TENART> + * This program is distributed in the hope that it will be useful,
 TENART> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 TENART> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 TENART> + * GNU General Public License for more details.
 TENART> + *
 TENART> + * You should have received a copy of the GNU General Public License
 TENART> + * along with this program; if not, write to the Free Software
 TENART> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 TENART> + * MA 02111-1307 USA
 TENART> + *
 TENART> + */
 TENART> +
 TENART> +#ifndef _TI816X_CPU_H
 TENART> +#define _TI816X_CPU_H
 TENART> +
 TENART> +#include <asm/arch/hardware.h>
 TENART> +
 TENART> +/* Timer registers */
 TENART> +#define TIMER_TCLR			0x38		/* Timer control register */
 TENART> +#define TIMER_TCRR			0x3C		/* Timer counter register */
 TENART> +#define TIMER_TLDR			0x40		/* Timer load value register*/
 TENART> +

Are these defines all needed? As far as I can see from skimming the
series, they aren't referenced anywhere.

 TENART> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
 TENART> index ed251ec..a7b938c 100644
 TENART> --- a/arch/arm/include/asm/emif.h
 TENART> +++ b/arch/arm/include/asm/emif.h
 TENART> @@ -521,7 +521,11 @@
 TENART>  #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
 
 TENART>  /* DMM */
 TENART> +#if defined(CONFIG_TI816X)
 TENART> +#define DMM_BASE			0x4E000000
 TENART> +#else
 TENART>  #define DMM_BASE			0x4E000040
 TENART> +#endif

I don't think that's right. Matt's series uses DMM_BASE to refer to the
lisa registers, which are offset 0x40 from the DMM region, so I think
you can drop this.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 5/8] Add TI816X cpu definitions

[TENART Antoine]

>   TENART>   /* DMM */
>   TENART>  +#if defined(CONFIG_TI816X)
>   TENART>  +#define DMM_BASE			0x4E000000
>   TENART>  +#else
>   TENART>   #define DMM_BASE			0x4E000040
>   TENART>  +#endif
>
> I don't think that's right. Matt's series uses DMM_BASE to refer to the
> lisa registers, which are offset 0x40 from the DMM region, so I think
> you can drop this.
>

You're right, this is because I didn't use config_dmm(). I'll fix that.

[U-Boot] [PATCH 6/8] Add TI816X specific register definitions

[TENART Antoine]

Also move some non common defintions from hardware.h
---
 arch/arm/include/asm/arch-am33xx/hardware.h        |    7 +--
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    5 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    5 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   58 ++++++++++++++++++++
 4 files changed, 70 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 5a27f9c..7f3b555 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -23,6 +23,8 @@
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
 #elif defined(CONFIG_TI814X)
 #include <asm/arch/hardware_ti814x.h>
 #endif
@@ -67,15 +69,10 @@
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
-#define DDR_PHY_CMD_ADDR2		0x47C0C800
-#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE		UART0_BASE
 
-#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
-
 /* GPMC Base address */
 #define GPMC_BASE			0x50000000
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index fa02f19..49a4392 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -43,8 +43,13 @@
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x44E12000
 #define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 #define DDR_DATA_REGS_NR		2
 
+#define DDRPHY_0_CONFIG_BASE    (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE      DDRPHY_0_CONFIG_BASE
+
 /* CPSW Config space */
 #define CPSW_MDIO_BASE			0x4A101000
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index a950ac3..ae0f370 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -42,8 +42,13 @@
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x47C0C400
 #define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 #define DDR_DATA_REGS_NR		4
 
+#define DDRPHY_0_CONFIG_BASE	(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
 /* CPSW Config space */
 #define CPSW_MDIO_BASE			0x4A100800
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
new file mode 100644
index 0000000..cb75d09
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -0,0 +1,58 @@
+/*
+ * hardware_ti816x.h
+ *
+ * TI816x hardware specific header
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ * Based on TI-PSP-04.00.02.14
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI816X_H
+#define __AM33XX_HARDWARE_TI816X_H
+
+/* Watchdog Timer */
+#define WDT_BASE				0x480C2000
+
+/* Control Module Base Address */
+#define CTRL_BASE				0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE				0x48180000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48198358
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x48198000
+#define DDR_PHY_DATA_ADDR		0x481980C8
+#define DDR_PHY_CMD_ADDR2		0x4819A000
+#define DDR_PHY_DATA_ADDR2		0x4819A0C8
+#define DDR_DATA_REGS_NR		4
+
+/* UART */
+#define UART0_BASE				0x48020000
+#define UART1_BASE				0x48022000
+#define UART2_BASE				0x48024000
+
+#define DDRPHY_0_CONFIG_BASE	0x48198000
+#define DDRPHY_1_CONFIG_BASE	0x4819a000
+#define DDRPHY_CONFIG_BASE		((emif == 0) ? DDRPHY_0_CONFIG_BASE:DDRPHY_1_CONFIG_BASE)
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE				0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI816X_H */
-- 
1.7.10.4

[U-Boot] [PATCH 6/8] Add TI816X specific register definitions

[Peter Korsgaard]

>>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:

 TENART> Also move some non common defintions from hardware.h
 TENART> ---
 TENART>  arch/arm/include/asm/arch-am33xx/hardware.h        |    7 +--
 TENART>  arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    5 ++
 TENART>  arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    5 ++
 TENART>  arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   58 ++++++++++++++++++++
 TENART>  4 files changed, 70 insertions(+), 5 deletions(-)
 TENART>  create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h

..

 TENART> +#define DDRPHY_0_CONFIG_BASE	0x48198000
 TENART> +#define DDRPHY_1_CONFIG_BASE	0x4819a000
 TENART> +#define DDRPHY_CONFIG_BASE		((emif == 0) ? DDRPHY_0_CONFIG_BASE:DDRPHY_1_CONFIG_BASE)
 TENART> +
 TENART> +/* CPSW Config space */
 TENART> +#define CPSW_MDIO_BASE			0x4A100800

ti816x doesn't have CPSW, so the name is a bit odd (the base address
matches the emac mdio module). The emac driver expects an
asm/arch/emac_defs.h header with a EMAC_MDIO_BASE_ADDR define (among
others).

Perhaps just drop it from here as you're not adding emac support in this
series anyway.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 6/8] Add TI816X specific register definitions

[Tom Rini]

On Thu, Mar 28, 2013 at 10:37:28PM +0100, Peter Korsgaard wrote:
> >>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:
> 
>  TENART> Also move some non common defintions from hardware.h
>  TENART> ---
>  TENART>  arch/arm/include/asm/arch-am33xx/hardware.h        |    7 +--
>  TENART>  arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    5 ++
>  TENART>  arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    5 ++
>  TENART>  arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   58 ++++++++++++++++++++
>  TENART>  4 files changed, 70 insertions(+), 5 deletions(-)
>  TENART>  create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
> 
> ..
> 
>  TENART> +#define DDRPHY_0_CONFIG_BASE	0x48198000
>  TENART> +#define DDRPHY_1_CONFIG_BASE	0x4819a000
>  TENART> +#define DDRPHY_CONFIG_BASE		((emif == 0) ? DDRPHY_0_CONFIG_BASE:DDRPHY_1_CONFIG_BASE)
>  TENART> +
>  TENART> +/* CPSW Config space */
>  TENART> +#define CPSW_MDIO_BASE			0x4A100800
> 
> ti816x doesn't have CPSW, so the name is a bit odd (the base address
> matches the emac mdio module). The emac driver expects an
> asm/arch/emac_defs.h header with a EMAC_MDIO_BASE_ADDR define (among
> others).
> 
> Perhaps just drop it from here as you're not adding emac support in this
> series anyway.

Agreed, and please check the whole series over for other unused defines.
We shouldn't import things we aren't using.

-- 
Tom
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[U-Boot] [PATCH 7/8] Add TI816X mmc clock reference

[TENART Antoine]

---
 arch/arm/include/asm/arch-am33xx/mmc_host_def.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index e0a3b8b..09d7a77 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -155,6 +155,8 @@ typedef struct hsmmc {
 /* Clock Configurations and Macros */
 #ifdef CONFIG_AM33XX
 #define MMC_CLOCK_REFERENCE	96 /* MHz */
+#elif defined(CONFIG_TI816X)
+#define MMC_CLOCK_REFERENCE	48 /* MHz */
 #elif defined(CONFIG_TI814X)
 #define MMC_CLOCK_REFERENCE	192 /* MHz */
 #endif
-- 
1.7.10.4

[U-Boot] [PATCH 7/8] Add TI816X mmc clock reference

[Peter Korsgaard]

>>>>> "TENART" == TENART Antoine <atenart@adeneo-embedded.com> writes:

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 8/8] Add TI816X evm board support

[TENART Antoine]

---
 MAINTAINERS                            |    4 +
 arch/arm/include/asm/arch-am33xx/spl.h |    9 +
 board/ti/ti816x/Makefile               |   48 ++
 board/ti/ti816x/evm.c                  |  753 ++++++++++++++++++++++++++++++++
 boards.cfg                             |    1 +
 include/configs/ti816x_evm.h           |  172 ++++++++
 6 files changed, 987 insertions(+)
 create mode 100644 board/ti/ti816x/Makefile
 create mode 100644 board/ti/ti816x/evm.c
 create mode 100644 include/configs/ti816x_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 6b2202c..3aaac7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -922,6 +922,10 @@ Lucas Stach <dev@lynxeye.de>
 
 	colibri_t20_iris	Tegra20 (ARM7 & A9 Dual Core)
 
+Antoine Tenart <atenart@adeneo-embedded.com>
+
+	TI816X		ARM ARMV7 (TI816x Soc)
+
 Nick Thompson <nick.thompson@gefanuc.com>
 
 	da830evm	ARM926EJS (DA830/OMAP-L137)
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 9b5fe9e..d0c1ec9 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -23,6 +23,14 @@
 #ifndef	_ASM_ARCH_SPL_H_
 #define	_ASM_SPL_H_
 
+#if defined(CONFIG_TI816X)
+#define BOOT_DEVICE_XIP		2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_MMC2	5
+#define BOOT_DEVICE_UART	0x43
+#define BOOT_DEVICE_MMC2_2	0xFF
+#else
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
 #ifdef CONFIG_AM33XX
@@ -37,3 +45,4 @@
 #define BOOT_DEVICE_CPGMAC	70
 #define BOOT_DEVICE_MMC2_2      0xFF
 #endif
+#endif
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 0000000..59128ee
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+# Antoine Tenart, <atenart@adeneo-embedded.com>
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= evm.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 0000000..cb809e9
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,753 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING
+static void ddr3_sw_levelling(int emif);
+#endif
+
+int board_init(void)
+{
+    gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+    return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+
+static struct module_pin_mux mmc_pin_mux[] = {
+	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+	{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+	{ -1 },
+};
+
+/*
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ */
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b" : "=r" (loops) : "0"(loops));
+}
+
+/* assume delay is aprox at least 1us */
+void ddr_delay(int d)
+{
+  int i;
+
+  /*
+   * read a control module register.
+   * this is a bit more delay and cannot be optimized by the compiler
+   * assuming one read takes 200 cycles and A8 is runing 1 GHz
+   * somewhat conservative setting
+   */
+  for(i=0; i<50*d; i++)
+    readl(CONTROL_STATUS);
+}
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+/*
+ * Init DDR3 on TI816X EVM
+ */
+static void ddr_init_settings(int emif)
+{
+	/*
+	 * DLL Lockdiff DLL_Lockdiff determines effectively is the
+	 * threshold internal to the DLL to indicate that the DLL has
+	 * lost lock.  When this happens the PHY currently issues an
+	 * internal reset.  The reset value for this is 0x4, which is
+	 * insufficient.  Set this to 15 (maximum possible - to
+	 * prevent this reset.  If the reset happens it would cause
+	 * the data to be corrupted.
+	 */
+	if(0 == get_cpu_rev())
+	{
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x028);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x05C);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x090);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x138);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x1DC);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x280);
+		writel(0xF, DDRPHY_CONFIG_BASE + 0x324);
+	}
+
+	/*
+	 * setup use_rank_delays to 1.  This is only necessary when
+	 * multiple ranks are in use.  Though the EVM does not have
+	 * multiple ranks, this is a good value to set.
+	 */
+	writel(1, DDRPHY_CONFIG_BASE + 0x134);
+	writel(1, DDRPHY_CONFIG_BASE + 0x1d8);
+	writel(1, DDRPHY_CONFIG_BASE + 0x27c);
+	writel(1, DDRPHY_CONFIG_BASE + 0x320);
+
+	/* see ddr_defs.h for invert clock setting and details */
+	writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x02C); /* invert_clk_out cmd0 */
+	writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x060); /* invert_clk_out cmd0 */
+	writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x094); /* invert_clk_out cmd0 */
+
+	/* with inv clkout: 0x100. no inv clkout: 0x80.  See ddr_defs.h */
+	writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x01C); /* cmd0 slave ratio */
+	writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x050); /* cmd1 slave ratio */
+	writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x084); /* cmd2 slave ratio */
+
+	/* for ddr3 this needs to be set to 1 */
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
+	writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
+
+	/****  setup the initial levelinihg ratios ****/
+	/* these are derived from board delays and may be different for different boards
+	 * see ddr_defs.h
+	 * we are setting the values here for both the ranks, though only one is in use
+	 */
+	writel((WR_DQS_RATIO_3 << 10) | WR_DQS_RATIO_3, DDRPHY_CONFIG_BASE + 0x0F0); /*  data0 writelvl init ratio */
+	writel(0x00000, DDRPHY_CONFIG_BASE + 0x0F4);   /*   */
+	writel((WR_DQS_RATIO_2 << 10) | WR_DQS_RATIO_2, DDRPHY_CONFIG_BASE + 0x194); /*  data1 writelvl init ratio */
+	writel(0x00000, DDRPHY_CONFIG_BASE + 0x198);   /*   */
+	writel((WR_DQS_RATIO_1 << 10) | WR_DQS_RATIO_1, DDRPHY_CONFIG_BASE + 0x238); /*  data2 writelvl init ratio */
+	writel(0x00000, DDRPHY_CONFIG_BASE + 0x23c);   /*   */
+	writel((WR_DQS_RATIO_0 << 10) | WR_DQS_RATIO_0, DDRPHY_CONFIG_BASE + 0x2dc); /*  data3 writelvl init ratio */
+	writel(0x00000, DDRPHY_CONFIG_BASE + 0x2e0);   /*   */
+
+
+	writel((RD_GATE_RATIO_3 << 10) | RD_GATE_RATIO_3, DDRPHY_CONFIG_BASE + 0x0FC); /*  data0 gatelvl init ratio */
+	writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
+	writel((RD_GATE_RATIO_2 << 10) | RD_GATE_RATIO_2, DDRPHY_CONFIG_BASE + 0x1A0); /*  data1 gatelvl init ratio */
+	writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
+	writel((RD_GATE_RATIO_1 << 10) | RD_GATE_RATIO_1, DDRPHY_CONFIG_BASE + 0x244); /*  data2 gatelvl init ratio */
+	writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
+	writel((RD_GATE_RATIO_0 << 10) | RD_GATE_RATIO_0, DDRPHY_CONFIG_BASE + 0x2E8); /*  data3 gatelvl init ratio */
+	writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
+
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x00C);     /* cmd0 io config - output impedance of pad */
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x010);     /* cmd0 io clk config - output impedance of pad */
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x040);     /* cmd1 io config - output impedance of pad */
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x044);     /* cmd1 io clk config - output impedance of pad */
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x074);     /* cmd2 io config - output impedance of pad */
+	writel(0x5, DDRPHY_CONFIG_BASE + 0x078);     /* cmd2 io clk config - output impedance of pad */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8);     /* data0 io config - output impedance of pad */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC);     /* data0 io clk config - output impedance of pad */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x14C);     /* data1 io config - output impedance of pa     */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x150);     /* data1 io clk config - output impedance of pad */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0);     /* data2 io config - output impedance of pa */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4);     /* data2 io clk config - output impedance of pad */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x294);     /* data3 io config - output impedance of pa */
+	writel(0x4, DDRPHY_CONFIG_BASE + 0x298);     /* data3 io clk config - output impedance of pad */
+
+	if(0 == get_cpu_rev())
+	{
+		writel(0x5, DDRPHY_CONFIG_BASE + 0x338);     /* fifo_we_out0  - output impedance of pad */
+		writel(0x5, DDRPHY_CONFIG_BASE + 0x340);     /* fifo_we_out1 - output impedance of pad */
+		writel(0x5, DDRPHY_CONFIG_BASE + 0x348);     /* fifo_we_in2 - output impedance of pad */
+		writel(0x5, DDRPHY_CONFIG_BASE + 0x350);     /* fifo_we_in3 - output impedance of pad */
+	}
+}
+
+static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG, u32 RL)
+{
+	if(USE_EMIF0){
+		/*Program EMIF0 CFG Registers*/
+		writel(TIM1, EMIF4_0_SDRAM_TIM_1);
+		writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);
+		writel(TIM2, EMIF4_0_SDRAM_TIM_2);
+		writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);
+		writel(TIM3, EMIF4_0_SDRAM_TIM_3);
+		writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);
+		writel(SDCFG, EMIF4_0_SDRAM_CONFIG);
+		writel(RL, EMIF4_0_DDR_PHY_CTRL_1);
+		writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);
+		writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL);   /* initially a large refresh period */
+		writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL);   /* trigger initialization           */
+		writel((0x10000000|EMIF_SDREF), EMIF4_0_SDRAM_REF_CTRL);
+	}
+
+	if(USE_EMIF1){
+	/*Program EMIF1 CFG Registers*/
+		writel(TIM1, EMIF4_1_SDRAM_TIM_1);
+		writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW);
+		writel(TIM2, EMIF4_1_SDRAM_TIM_2);
+		writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW);
+		writel(TIM3, EMIF4_1_SDRAM_TIM_3);
+		writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW);
+		writel(SDCFG, EMIF4_1_SDRAM_CONFIG);
+		writel(RL, EMIF4_1_DDR_PHY_CTRL_1);
+		writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW);
+		writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL);   /* initially a large refresh period */
+		writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL);   /* trigger initialization           */
+		writel((0x10000000|EMIF_SDREF), EMIF4_1_SDRAM_REF_CTRL);
+	}
+
+	delay(1000);
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING
+    ddr3_sw_levelling(0);
+    ddr3_sw_levelling(1);
+#endif
+}
+
+static void config_ti816x_sdram_ddr(void)
+{
+	writel(0x2, CM_DEFAULT_FW_CLKCTRL);				/*Enable the EMIF Firewall clocks */
+	writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL);			/*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
+	writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL);				/*Enable EMIF0 Clock*/
+	writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL);				/*Enable EMIF1 Clock*/
+	while((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
+	while((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);	/*Poll for Module is functional*/
+	while((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);	/*Poll for Module is functional*/
+
+	if (USE_EMIF0) {
+		ddr_init_settings(0);
+	}
+
+	if (USE_EMIF1) {
+		ddr_init_settings(1);
+	}
+
+	writel(0x2, CM_DEFAULT_DMM_CLKCTRL);			/*Enable EMIF1 Clock*/
+	while((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2);		/*Poll for Module is functional*/
+
+	/* Program the DMM to for interleaved configuration */
+	writel(0x0, DMM_LISA_MAP__0);
+	writel(0x0, DMM_LISA_MAP__1);
+	writel(0x80640300, DMM_LISA_MAP__2);
+	writel(0xC0640320, DMM_LISA_MAP__3);
+
+	/*Enable Tiled Access*/
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
+
+	emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF & 0xFFFFFFF, EMIF_SDCFG, EMIF_PHYCFG);
+
+}
+
+#ifdef CONFIG_TI816X_DDR3_SW_LEVELING
+static void ddr3_sw_levelling(int emif)
+{
+    writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
+
+    writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108));
+    writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C));
+    writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC));
+    writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0));
+    writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250));
+    writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254));
+    writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4));
+    writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8));
+
+    writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0));
+    writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x184));
+    writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x228));
+    writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC));
+
+    writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x124));
+    writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8));
+    writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C));
+    writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x310));
+
+    writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC));
+    writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x170));
+    writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x214));
+    writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4));
+    writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8));
+}
+#endif /* CONFIG_TI816X_DDR3_SW_LEVELING */
+
+#endif /* CONFIG_TI816X_EVM_DDR3 */
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+static void ddr_init_settings(int emif)
+{
+	/* DLL Lockdiff */
+	if(0 == get_cpu_rev())
+	{
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x028));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x05C));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x090));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x138));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x1DC));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x280));
+		writel(0xF, (DDRPHY_CONFIG_BASE + 0x324));
+	}
+
+	if(1 == get_cpu_rev())
+	{
+		writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
+	}
+
+	/* setup rank delays */
+	writel(0x1, (DDRPHY_CONFIG_BASE + 0x134));
+	writel(0x1, (DDRPHY_CONFIG_BASE + 0x1D8));
+	writel(0x1, (DDRPHY_CONFIG_BASE + 0x27C));
+	writel(0x1, (DDRPHY_CONFIG_BASE + 0x320));
+
+
+	writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x02C));	/* invert_clk_out cmd0 */
+	writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x060));	/* invert_clk_out cmd0 */
+	writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x094));	/* invert_clk_out cmd0 */
+
+
+	writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x01C));	/* cmd0 slave ratio */
+	writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x050));	/* cmd0 slave ratio */
+	writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x084));	/* cmd0 slave ratio */
+
+	writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108));
+	writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C));
+	writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC));
+	writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0));
+	writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250));
+	writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254));
+	writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4));
+	writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8));
+
+	writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0));
+	writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x184));
+	writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x228));
+	writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC));
+
+	writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x124));
+	writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8));
+	writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C));
+	writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x310));
+
+	writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC));
+	writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x170));
+	writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x214));
+	writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4));
+	writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8));
+
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x00C));
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x010));
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x040));
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x044));
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x074));
+	writel(0x5, (DDRPHY_CONFIG_BASE + 0x078));
+
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x0A8));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x0AC));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x14C));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x150));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F0));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F4));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x294));
+	writel(0x4, (DDRPHY_CONFIG_BASE + 0x298));
+
+	if(0 == get_cpu_rev())
+	{
+		writel(0x5, (DDRPHY_CONFIG_BASE + 0x338));
+		writel(0x5, (DDRPHY_CONFIG_BASE + 0x340));
+		writel(0x5, (DDRPHY_CONFIG_BASE + 0x348));
+		writel(0x5, (DDRPHY_CONFIG_BASE + 0x350));
+	}
+
+}
+
+static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG, u32 RL)
+{
+	/*Program EMIF0 CFG Registers*/
+	writel(TIM1, EMIF4_0_SDRAM_TIM_1);
+	writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW);
+	writel(TIM2, EMIF4_0_SDRAM_TIM_2);
+	writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW);
+	writel(TIM3, EMIF4_0_SDRAM_TIM_3);
+	writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW);
+	writel(SDCFG, EMIF4_0_SDRAM_CONFIG);
+	writel(RL, EMIF4_0_DDR_PHY_CTRL_1);
+	writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW);
+
+	if (CONFIG_TI816X_TWO_EMIF){
+	writel(TIM1, EMIF4_1_SDRAM_TIM_1);
+	writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW);
+	writel(TIM2, EMIF4_1_SDRAM_TIM_2);
+	writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW);
+	writel(TIM3, EMIF4_1_SDRAM_TIM_3);
+	writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW);
+	writel(SDCFG, EMIF4_1_SDRAM_CONFIG);
+	writel(RL, EMIF4_1_DDR_PHY_CTRL_1);
+	writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW);
+	}
+
+	/* setup a small control period */
+	writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL);
+	writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL);
+	writel((0x10000000|SDREF), EMIF4_0_SDRAM_REF_CTRL);
+
+	if (CONFIG_TI816X_TWO_EMIF){
+	/* setup a small control period */
+	writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL);
+	writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL);
+	writel((0x10000000|SDREF), EMIF4_1_SDRAM_REF_CTRL);
+
+	}
+
+
+}
+
+static void config_ti816x_sdram_ddr(void)
+{
+	writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL);			/*Enable the Power Domain Transition of L3 Fast Domain Peripheral*/
+	writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL);				/*Enable EMIF0 Clock*/
+	writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL);				/*Enable EMIF1 Clock*/
+	while((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300);	/*Poll for L3_FAST_GCLK  & DDR_GCLK  are active*/
+	while((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2);	/*Poll for Module is functional*/
+	while((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2);	/*Poll for Module is functional*/
+
+	ddr_init_settings(0);
+
+	if (CONFIG_TI816X_TWO_EMIF){
+		ddr_init_settings(1);
+	}
+
+	writel(0x2, CM_DEFAULT_DMM_CLKCTRL);				/*Enable EMIF1 Clock*/
+	while((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2);		/*Poll for Module is functional*/
+
+	/*Program the DMM for interleave setting */
+	writel(0x0, DMM_LISA_MAP__0);
+	writel(0x0, DMM_LISA_MAP__1);
+	writel(0x80640300, DMM_LISA_MAP__2);
+	writel(0xC0640320, DMM_LISA_MAP__3);
+
+	/*Enable Tiled Access*/
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
+
+	emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF & 0xFFFFFFF, EMIF_SDCFG, EMIF_PHYCFG);
+
+}
+#endif
+
+/*
+ * TI816X specific functions
+ */
+static void main_pll_init_ti816x(u32 sil_index, u32 clk_index)
+{
+	u32 main_pll_ctrl=0;
+
+	/* Sequence to be followed:
+	 * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg
+	 * 2. Write the values of N,P in the CTRL reg
+	 * 3. Program the freq values, divider values for the required output in the Control module reg
+	 * 4. Note: Loading the freq value requires a particular bit to be set in the freq reg.
+	 * 4. Program the CM divider value in the CM module reg
+	 * 5. Enable the PLL by setting the appropriate bit in the CTRL reg of the PLL
+	 */
+
+	 /* If the registers have been set by the ROM code dont do anything
+	  */
+
+	 main_pll_ctrl = readl(MAINPLL_CTRL);
+	 main_pll_ctrl &= 0xFFFFFFFB;
+	 main_pll_ctrl |= 4;
+	 writel(main_pll_ctrl, MAINPLL_CTRL);
+
+	 main_pll_ctrl = readl(MAINPLL_CTRL);
+	 main_pll_ctrl &= 0xFFFFFFF7;
+	 main_pll_ctrl |= 8;
+	 writel(main_pll_ctrl, MAINPLL_CTRL);
+
+	 main_pll_ctrl = readl(MAINPLL_CTRL);
+	 main_pll_ctrl &= 0xFF;
+	 main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+	 writel(main_pll_ctrl, MAINPLL_CTRL);
+
+	 writel(0x0, MAINPLL_PWD);
+
+	 writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), MAINPLL_FREQ1);
+	 writel(((1<<8) | MAIN_MDIV1), MAINPLL_DIV1);
+
+	 writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), MAINPLL_FREQ2);
+	 writel(((1<<8) | MAIN_MDIV2), MAINPLL_DIV2);
+
+	 writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), MAINPLL_FREQ3);
+	 writel(((1<<8) | MAIN_MDIV3), MAINPLL_DIV3);
+
+	 writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), MAINPLL_FREQ4);
+	 writel(((1<<8) | MAIN_MDIV4), MAINPLL_DIV4);
+
+	 writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), MAINPLL_FREQ5);
+	 writel(((1<<8) | MAIN_MDIV5), MAINPLL_DIV5);
+
+	 writel((1<<8 | MAIN_MDIV6), MAINPLL_DIV6);
+
+	 writel((1<<8 | MAIN_MDIV7), MAINPLL_DIV7);
+
+	 while((readl(MAINPLL_CTRL) & 0x80) != 0x80);
+
+	 main_pll_ctrl = readl(MAINPLL_CTRL);
+	 main_pll_ctrl &= 0xFFFFFFFB;
+
+	 writel(main_pll_ctrl, MAINPLL_CTRL);
+
+}
+
+static void ddr_pll_init_ti816x(u32 sil_index, u32 clk_index)
+{
+	u32 ddr_pll_ctrl=0;
+
+	/* Sequence to be followed:
+	 * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg
+	 * 2. Write the values of N,P in the CTRL reg
+	 * 3. Program the freq values, divider values for the required output in the Control module reg
+	 * 4. Note: Loading the freq value requires a particular bit to be set in the freq reg.
+	 * 4. Program the CM divider value in the CM module reg
+	 * 5. Enable the PLL by setting the appropriate bit in the CTRL reg of the PLL
+	 */
+
+	 /* If the registers have been set by the ROM code dont do anything
+	  */
+
+	ddr_pll_ctrl = readl(DDRPLL_CTRL);
+	ddr_pll_ctrl &= 0xFFFFFFFB;
+	writel(ddr_pll_ctrl, DDRPLL_CTRL);
+
+	ddr_pll_ctrl = readl(DDRPLL_CTRL);
+	ddr_pll_ctrl &= 0xFFFFFFF7;
+	ddr_pll_ctrl |= 8;
+	writel(ddr_pll_ctrl, DDRPLL_CTRL);
+
+	ddr_pll_ctrl = readl(DDRPLL_CTRL);
+	ddr_pll_ctrl &= 0xFF;
+	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+	writel(ddr_pll_ctrl, DDRPLL_CTRL);
+
+	/* 10usec delay */
+	ddr_delay(10);
+
+	writel(0x0,DDRPLL_PWD);
+
+	writel(((0<<8) | DDR_MDIV1), DDRPLL_DIV1);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV1), DDRPLL_DIV1);
+
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), DDRPLL_FREQ2);
+	writel(((1<<8) | DDR_MDIV2), DDRPLL_DIV2);
+
+	writel(((0<<8) | DDR_MDIV3), DDRPLL_DIV3);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV3), DDRPLL_DIV3);
+	ddr_delay(1);
+	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), DDRPLL_FREQ3);
+	ddr_delay(1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), DDRPLL_FREQ3);
+
+	ddr_delay(5);
+
+	/* Wait for PLL to lock */
+	while((readl(DDRPLL_CTRL) & 0x80) != 0x80);
+
+	ddr_pll_ctrl = readl(DDRPLL_CTRL);
+	ddr_pll_ctrl &= 0xFFFFFFFB;
+	ddr_pll_ctrl |= 4;
+	writel(ddr_pll_ctrl, DDRPLL_CTRL);
+
+	writel(0x1, DDR_RCD);
+
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (TIMER1, UART0,...)
+ *
+ ******************************************************************/
+static void peripheral_enable(void)
+{
+	/* DMTimers */
+	writel(0x2, CM_ALWON_L3_SLOW_CLKSTCTRL);
+
+	/* Note on Timers:
+	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+	 * Timer 0 mux should not be changed
+	 * For other timers, there are 3 inputs TCLKIN, 32KHz (external clk or SYSCLK18?) and CLKIN(27MHz)
+	 * We select CLKIN and use that
+	 */
+
+	/* First we need to enable the modules and setup the clk path
+	 * Then the timers need to be configured by writing to their registers
+	 * To access the timer registers we need the module to be
+	 * enabled which is what we do in the first step
+	 */
+
+	/* TIMER 1 */
+	writel(0x2, CM_ALWON_TIMER_1_CLKCTRL);
+
+	/* Selects CLKIN (27MHz) */
+	writel(0x2, CM_TIMER1_CLKSEL);
+
+	while(((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & (0x80000<<1)) >> (19+1)) != 1);
+
+	while(((readl(CM_ALWON_TIMER_1_CLKCTRL) & 0x30000)>>16) !=0);
+
+
+	writel(0x2,(DM_TIMER1_BASE + 0x54));
+	while(readl(DM_TIMER1_BASE + 0x10) & 1);
+
+	writel(0x1,(DM_TIMER1_BASE + 0x38));
+
+	/* UARTs */
+	/* Note: The clock has been set to correct rate before this step */
+	writel(0x2, CM_ALWON_UART_0_CLKCTRL);
+	while(readl(CM_ALWON_UART_0_CLKCTRL) != 0x2);
+
+	writel(0x2, CM_ALWON_UART_1_CLKCTRL);
+	while(readl(CM_ALWON_UART_1_CLKCTRL) != 0x2);
+
+	writel(0x2, CM_ALWON_UART_2_CLKCTRL);
+	while(readl(CM_ALWON_UART_2_CLKCTRL) != 0x2);
+
+	while((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x2100) != 0x2100);
+
+	/* eFuse */
+	writel(0x2, CM_ALWON_CUST_EFUSE_CLKCTRL);
+	while(readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != 0x2);
+
+	/* GPIO0 */
+	writel(0x2, CM_ALWON_GPIO_0_CLKCTRL);
+	while(readl(CM_ALWON_GPIO_0_CLKCTRL) != 0x2);
+
+	writel((BIT(8)), CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK);
+
+	/* SPI */
+	writel(0x2, CM_ALWON_SPI_CLKCTRL);
+	while(readl(CM_ALWON_SPI_CLKCTRL) != 0x2);
+
+	/* I2C0 */
+	writel(0x2, CM_ALWON_I2C_0_CLKCTRL);
+	while(readl(CM_ALWON_I2C_0_CLKCTRL) != 0x2);
+
+	/* Ethernet */
+	writel(0x2, CM_ETHERNET_CLKSTCTRL);
+	writel(0x2, CM_ALWON_ETHERNET_0_CLKCTRL);
+	writel(0x2, CM_ALWON_ETHERNET_1_CLKCTRL);
+
+	/* HSMMC */
+	writel(0x2, CM_ALWON_HSMMC_CLKCTRL);
+	while(readl(CM_ALWON_HSMMC_CLKCTRL) != 0x2);
+
+	/* WDT */
+	/* For WDT to be functional, it needs to be first stopped by writing
+	 * the pattern 0xAAAA followed by 0x5555 in the WDT start/stop register.
+	 * After that a write-once register in Control module needs to be configured
+	 * to unfreeze the timer.
+	 * Note: It is important to stop the watchdog before unfreezing it
+	 */
+	writel(0xAAAA, WDT_WSPR);
+	while(readl(WDT_WWPS) != 0x0);
+	writel(0x5555, WDT_WSPR);
+	while(readl(WDT_WWPS) != 0x0);
+
+	/* Unfreeze WDT */
+	writel(0x2, WDT_UNFREEZE);
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ *****************************************************************************/
+void prcm_init(void)
+{
+	/* For future */
+	u32 clk_index = 0, sil_index = 0;
+
+	writel(0x2, 0x48200010);
+	/* Enable the control module */
+	writel(0x2, CM_ALWON_CONTROL_CLKCTRL);
+
+	/* Fix ROM code bug */
+	writel(0x0, 0x48180324);
+
+	main_pll_init_ti816x(clk_index, sil_index);
+	ddr_pll_init_ti816x(clk_index, sil_index);
+
+	/* With clk freqs setup to desired values, enable the required peripherals */
+	peripheral_enable();
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	prcm_init();			/* Setup the PLLs and the clocks for the peripherals */
+	configure_module_pin_mux(mmc_pin_mux);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	config_ti816x_sdram_ddr();	/* Do DDR settings */
+#endif
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0, 0, 0);
+	return 0;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index c98495a..aab56b9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -239,6 +239,7 @@ am335x_evm_uart3             arm         armv7       am335x              ti
 am335x_evm_uart4             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL5,CONS_INDEX=5
 am335x_evm_uart5             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL6,CONS_INDEX=6
 ti814x_evm                   arm         armv7       ti814x              ti             am33xx
+ti816x_evm                   arm         armv7       ti816x              ti             am33xx
 pcm051                       arm         armv7       pcm051              phytec         am33xx      pcm051
 highbank                     arm         armv7       highbank            -              highbank
 mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
new file mode 100644
index 0000000..e6b1ddc
--- /dev/null
+++ b/include/configs/ti816x_evm.h
@@ -0,0 +1,172 @@
+/*
+ * ti816x_evm.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __CONFIG_TI816X_EVM_H
+#define __CONFIG_TI816X_EVM_H
+
+#define CONFIG_TI81XX
+#define CONFIG_TI816X
+#define CONFIG_SYS_NO_FLASH
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (32 * 1024))
+#undef  CONFIG_SYS_LONGHELP 	/* undef save memory */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"u-boot/ti816x# "
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG			/* required for ramdisk support */
+
+#include <config_cmd_default.h>		/* u-boot default commands */
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_BOOTDELAY	3		/* set negative for no autoboot */
+#define CONFIG_EXTRA_EMV_SETTINGS \
+	"verify=yes\0" \
+
+#define CONFIG_BOOTCOMMAND	"mmc rescan 0; fatload mmc 0 0x81000000 uImage; bootm 0x81000000"
+#define CONFIG_BOOTARGS		"console=ttyO2,115200n8 noinitrd earlyprintk"
+
+/* Clock Defines */
+#define V_OSCK          24000000    /* Clock output from T2 */
+#define V_SCLK          (V_OSCK >> 1)
+
+#define CONFIG_SYS_MAXARGS	32	/* max number of command arguments */
+#define CONFIG_SYS_CBSIZE	512	/* console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+                + sizeof(CONFIG_SYS_PROMPT) + 16)	/* print buffer size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* boot arg buffer size */
+
+/* memtest works on 8 MB in DRAM after skipping 32MB from start addr of ram disk */
+#define CONFIG_SYS_MEMTEST_START    (PHYS_DRAM_1 + (64 *1024 *1024))
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START \
+                    + (8 * 1024 * 1024))
+
+#undef  CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR	0x81000000  /* Default load address */
+#define CONFIG_SYS_HZ			1000    /* 1ms clock */
+
+#define CONFIG_CMD_ASKEN
+#define CONFIG_CMD_ECHO
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_FS_FAT
+
+/* Only one of the following two options (DDR3/DDR2) should be enabled */
+/*
+#define CONFIG_TI816X_EVM_DDR2
+#define CONFIG_TI816X_TWO_EMIF	1
+*/
+#define CONFIG_TI816X_EVM_DDR3
+
+
+#define CONFIG_NR_DRAM_BANKS	2			/* we have 2 banks of DRAM */
+#define PHYS_DRAM_1				0x80000000	/* DRAM Bank #1 */
+#define PHYS_DRAM_1_SIZE        0x40000000  /* 1 GB */
+#define PHYS_DRAM_2				0xC0000000 	/* DRAM Bank #2 */
+#define PHYS_DRAM_2_SIZE		0x40000000	/* 1 GB */
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+                    GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_CLK_FREQ     27000000
+#define CONFIG_SYS_TIMERBASE    0x4802E000
+#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
+
+#undef CONFIG_NAND_OMAP_GPMC
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK      (48000000)
+#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
+
+#define CONFIG_BAUDRATE     115200
+#define CONFIG_SYS_BAUDRATE_TABLE   { 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SERIAL1
+#define CONFIG_SERIAL2
+#define CONFIG_SERIAL3
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE        0x40300000
+#define CONFIG_SPL_MAX_SIZE     ((128 - 18) * 1024)
+#define CONFIG_SPL_STACK        CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR   0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
+#define CONFIG_SPL_LDSCRIPT     "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_TEXT_BASE        0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#endif
-- 
1.7.10.4

[U-Boot] [PATCH 8/8] Add TI816X evm board support

[Tom Rini]

On Thu, Mar 28, 2013 at 06:14:41PM +0100, TENART Antoine wrote:

> ---
>  MAINTAINERS                            |    4 +
>  arch/arm/include/asm/arch-am33xx/spl.h |    9 +
>  board/ti/ti816x/Makefile               |   48 ++
>  board/ti/ti816x/evm.c                  |  753 ++++++++++++++++++++++++++++++++

This file has a large number of style problems, both things I know
checkpatch will catch as well as inconsistent spacing throughout and
/*
 * All multiline comments must look
 * like this.
 */

[snip]
> +#define CONFIG_SYS_BAUDRATE_TABLE   { 110, 300, 600, 1200, 2400, \
> +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }

Please use the fallback table instead of this.  And I snipped it before
I recalled, but you also should have enough memory to keep longhelp :)

-- 
Tom
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