From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 3 May 2013 04:25:32 +0200
Subject: [U-Boot] [PATCH v3 5/7] mxs: spl_mem_init: Remove erroneous DDR
	setting
In-Reply-To: <1367534661-13502-6-git-send-email-festevam@gmail.com>
References: <1367534661-13502-1-git-send-email-festevam@gmail.com>
	<1367534661-13502-6-git-send-email-festevam@gmail.com>
Message-ID: <201305030425.32401.marex@denx.de>
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To: u-boot@lists.denx.de

Dear Fabio Estevam,

> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.
> 
> Remove this erroneous setting.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - None
> Changes since v1:
> - Newly introduced as the previous patch is now splitted.
> 
>  arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 300da0a..df25535 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -279,10 +279,6 @@ static void mx23_mem_init(void)
> 
>  	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
>  	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
> -
> -	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
> -	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
> -		;

Is there no such similar bit indicating the init completed?

>  }
>  #endif

Best regards,
Marek Vasut