From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Tue, 21 May 2013 18:45:25 +0200 Subject: [U-Boot] ARM v7: Flush icache when executing a program with go In-Reply-To: References: <1368540962.4464.9.camel@localhost> <20130515171111.481eb3de@lilith> <1368635647.3991.18.camel@localhost> <20130515184410.26e34874@lilith> <20130515165121.GG29196@bill-the-cat> <20130515193959.69aa9d64@lilith> <1368669278.27007.43.camel@localhost> <20130516071406.6AD19380635@gemini.denx.de> <20130516133754.GF32163@bill-the-cat> <1368718669.25965.14.camel@localhost> Message-ID: <20130521184525.02f32f8e@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Kees, On Tue, 21 May 2013 14:38:01 +0200, Kees Jongenburger wrote: > To my > understanding also enabling d-cache on ARM has no effect as long as > the MMU is not turned on so I totally miss the point. Enabling dcache gives DDR access performance benefits regardless of enabling MMU. > Greetings Amicalement, -- Albert.