From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 21 May 2013 21:02:29 +0200
Subject: [U-Boot] [PATCH] arm: pxa: PXA270 D-Cache as ram
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	<201305211700.20807.marex@denx.de>
	<1369153867.12900.25.camel@host5.omatika.ru>
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Dear Sergey Yanovich,

> On Tue, 2013-05-21 at 17:00 +0200, Marek Vasut wrote:
> > > Yes, the patch as it is will only affects relocation speed and preserve
> > > SRAM from corruption.
> > 
> > Now this is the right (convincing) argument! What kind of corruption ?
> > When does it occur ?
> 
> The whole 256 kB of SRAM could be used for persistent storage with the
> patch. Without it, part of SRAM should be dedicated for U-Boot stack or
> be overwritten on boot.

This won't hold on any PXA that uses SPL, like the vpac270 with OneNAND SPL and 
PXA3xx (which is out of tree, none of your concern ;-) )

> > > The speed gain can also be applied to uImage
> > > copying/unpacking, but that requires deeper understanding than I have
> > > at the moment.
> > 
> > Uh ... I lost you here. Can you please elaborate some more ?
> 
> You are right. After SDRAM is configured, it is enough to turn on data
> caching to receive its speed benefits.

You must make sure anything that uses DMA won't crash. But I don't understand 
how locking cachelines as RAM and enabling dcache relate to each other in this 
context.

Best regards,
Marek Vasut