From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 24 May 2013 23:06:36 +0200 Subject: [U-Boot] [PATCH] usb: ehci: add missing cache managment In-Reply-To: <1369429397-16895-1-git-send-email-swarren@wwwdotorg.org> References: <1369429397-16895-1-git-send-email-swarren@wwwdotorg.org> Message-ID: <201305242306.37006.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Stephen Warren, > From: Stephen Warren > > Commit 8f62ca6 "usb: ehci: Support interrupt transfers via periodic list" > didn't include any cache management in the new interrupt transfer path. > It also added an extra write to or_asynclistaddr in usb_lowlevel_init(), > without having flushed out the data there. > > Add the missing cache management calls, so that the code works again. > > This allows the USB keyboard on Tegra's Seaboard/Springbank boards to > work. > > Cc: Patrick Georgi > Cc: Vincent Palatin > Cc: Julius Werner > Cc: Simon Glass > Cc: Marek Vasut > Signed-off-by: Stephen Warren Good find, applied! Best regards, Marek Vasut