From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sat, 22 Jun 2013 04:29:56 +0200 Subject: [U-Boot] [PATCH 2/2] pxa: fix memory coherency problem after relocation In-Reply-To: <1371831148-22380-3-git-send-email-mikedunn@newsguy.com> References: <1371831148-22380-1-git-send-email-mikedunn@newsguy.com> <1371831148-22380-3-git-send-email-mikedunn@newsguy.com> Message-ID: <201306220429.56662.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Mike Dunn, > On the xscale, the icache must be invalidated and the write buffers drained > after writing code over the data bus, even if the caches are disabled. > Tested on the pxa270. > > Signed-off-by: Mike Dunn > --- > arch/arm/lib/relocate.S | 9 +++++++++ > 1 files changed, 9 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S > index 4446da9..eedf314 100644 > --- a/arch/arm/lib/relocate.S > +++ b/arch/arm/lib/relocate.S > @@ -92,6 +92,15 @@ fixnext: > > relocate_done: > > +#ifdef __XSCALE__ > + /* > + * On xscale, icache must be invalidated and write buffers drained, > + * even with cache disabled - 4.2.7 of xscale core developer's manual > + */ > + mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ > + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ > +#endif > + > /* ARMv4- don't know bx lr but the assembler fails to see that */ > > #ifdef __ARM_ARCH_4__ Acked-by: Marek Vasut Albert, do you want me to pick these or will you? Best regards, Marek Vasut