From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sughosh Ganu <urwithsughosh@gmail.com>
Date: Thu, 4 Jul 2013 23:43:29 +0530
Subject: [U-Boot] TLB mapping for pcie mem space for fsl corenet processors
Message-ID: <20130704181329.GA8752@Hardy>
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To: u-boot@lists.denx.de

hi,
The tlb entries for the pcie mem space for the corenet SoC's is done
for 1.5GiB but certain boards use all the 4 pcie controller
instantiations, and each controller is assigned 512MiB size in the
config files. Should the tlb entries not map 2GiB space as against
1.5GiB. Am i missing something. Thanks.

-sughosh