[U-Boot] [RFC PATCH] arm: arm926ejs: flush cache before disable it

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hi Sughosh,

On Tue, 9 Jul 2013 11:41:34 +0530, Sughosh Ganu
<urwithsughosh@gmail.com> wrote:

> hi Albert,
> 
> On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
> 
> <snip>
> 
> > > > Invalidating the cache in addition to flushing it would not prevent
> > > > further writes from dirtying the cache lines if they happen before
> > > > the cache is disabled.
> > > 
> > > I have a doubt on this. The arm926ejs uses a read-allocate policy,
> > > wherein a new cache line is allocated only on a read miss -- a write
> > > to an address not present in the cache gets written to memory. So if
> > > the cache line is invalidated, how will data get written to the cache.
> > 
> > The arm926ej-s data cache does not have a single fixed policy, and
> > does not have a bypass-on-write policy, only write-through and
> > copy-back.
> > 
> > Other, more complex, policies may be defined, but at the MMU, not cache,
> > level, and those are not constant for all arm926ej-s based SoCs; not
> > even constant for a given SoC as they are configurable at run-time to
> > fit the chosen system addressing map.
> 
> Can you please elucidate on these policies. Based on my reading of the
> arm developers manual and the arm926ejs trm, the mmu makes a
> particular region cacheable and/or write bufferable. I did not find
> mention of any other  policies. Maybe pointers or links to the
> documents would help.

You are correct re the other policies of the DDI0198E (ARM926EJ-S
TRM) MMU -- page 3-11, bits 3-2 of the section descriptor. Note however
that you may have to refer to your specific SoC's TRM or equivalent, as
the SoC designer may have defined its own system-level cache and MMU
architecture.

Note in any case that none of the policies mentioned in DDI0198E is
described as read-allocate (let alone "read-allocate only" where writes
would bypass the enabled cache); on the contrary, the only cache
policies mentioned are write-through and write-back, both of which
contradict cache bypass on write.

> > (Besides, bypassing the cache for writes and not reads is of little
> > interest for plain DDR caching.)
> 
> Again, afaik this is independent of the target interface that is being
> cached(if i've missed something, can you please point me to the
> document). Thanks.

Sorry, I don't understand this last comment of yours wrt my point on the
(lack of) interest of bypassing cache for DDR caching.

> -sughosh

Amicalement,
-- 
Albert.