[U-Boot] [PATCH RFC V1 01/18] Add functions for use with i.mx6 otg udc

Troy Kisky
2013-07-16T20:47:29Z

Add functions for use with mx6 soc
void otg_enable(void);
void reset_usb_phy1(void);

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 70 +++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/sys_proto.h | 4 ++
2 files changed, 74 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index fc436fb..e5a5734 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -28,11 +28,81 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>

+#ifdef CONFIG_MV_UDC
+
+struct set_clr_tog {
+ u32 val;
+ u32 set;
+ u32 clr;
+ u32 tog;
+};
+
+struct usbphy {
+ struct set_clr_tog pwd;
+ struct set_clr_tog tx;
+ struct set_clr_tog rx;
+ struct set_clr_tog ctrl;
+};
+
+#define BM_USBPHY_CTRL_CLKGATE 0x40000000
+
+static void enable_usb_phy1_clk(unsigned char enable)
+{
+ struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR;
+
+ writel(BM_USBPHY_CTRL_CLKGATE,
+ enable ? &phy->ctrl.clr : &phy->ctrl.set);
+}
+
+#define BM_USBPHY_CTRL_SFTRST 0x80000000
+
+void reset_usb_phy1(void)
+{
+ struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR;
+
+ /* Reset USBPHY module */
+ writel(BM_USBPHY_CTRL_SFTRST, &phy->ctrl.set);
+ udelay(10);
+
+ /* Remove CLKGATE and SFTRST */
+ writel(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST, &phy->ctrl.clr);
+ udelay(10);
+
+ /* Power up the PHY */
+ writel(0, &phy->pwd.val);
+}
+
+
+#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
+#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
+
+static void set_usb_phy1_clk(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+
+ writel(BM_ANADIG_USB1_CHRG_DETECT_EN_B
+ | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B,
+ &anatop->usb1_chrg_detect_set);
+
+ /* make sure pll is enable here */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
+ &anatop->usb1_pll_480_ctrl_set);
+}
+
+void otg_enable(void)
+{
+ set_usb_phy1_clk();
+ enable_usboh3_clk(1);
+ enable_usb_phy1_clk(1);
+}
+#endif
+
struct scu_regs {
u32 ctrl;
u32 config;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 38e4e51..8ac57df 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -56,4 +56,8 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg,
int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
+
+void otg_enable(void);
+void reset_usb_phy1(void);
+
#endif
--
1.8.1.2