From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Wed, 17 Jul 2013 12:42:25 +0200 Subject: [U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode In-Reply-To: <51E67191.4000102@atmel.com> References: <1374052458-3326-1-git-send-email-voice.shen@atmel.com> <20130717121040.4f0e1243@lilith> <51E67191.4000102@atmel.com> Message-ID: <20130717124225.187b81d4@lilith> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Bo, On Wed, 17 Jul 2013 18:27:29 +0800, Bo Shen wrote: > Hi Albert, > > On 07/17/2013 06:10 PM, Albert ARIBAUD wrote: > > Hi Bo, > > > > On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen > > wrote: > > > >> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12 > >> and share the lower 8 bits data line. If use low drive of the data > >> line, it will cause DDR data access corrupt in lower address, so > >> change the data line to high drive mode > >> > >> This will fix the Linux kernel boot issue when use Lower address > > > > Wait--does this mean that there is no separate chip selects for NAND and > > DDR on this SoC? > > No. The NAND and DDR has there own chip selects. > This is chip specific. If DDR and NAND share data line, if we use low > drive for EBI IO, it will cause DDR low memory address content corrupt. > For example, if the DDR base address is 0x20000000, if we use 0x20008000 > as entry address of Linux kernel, then it won't boot up successfully. > So, if we need to use low memory address, we need this to fix. I understand the symptom. What I don't undestand is how come NAND does not keep its data lines in high impedance when its chip select is inactive, which it is when DDR is being accessed. > Best Regards, > Bo Shen Amicalement, -- Albert.