[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Bo Shen]

As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
and share the lower 8 bits data line. If use low drive of the data
line, it will cause DDR data access corrupt in lower address, so
change the data line to high drive mode

This will fix the Linux kernel boot issue when use Lower address

Signed-off-by: Bo Shen <voice.shen@atmel.com>
---
 board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 3013a42..66c4c1f 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -59,7 +59,7 @@ static void at91sam9n12ek_nand_hw_init(void)
 	/* Configure databus */
 	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
 	/* Configure IO drive */
-	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 
 	writel(csa, &matrix->ebicsa);
 
-- 
1.7.9.5

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Albert ARIBAUD]

Hi Bo,

On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen <voice.shen@atmel.com>
wrote:

> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
> and share the lower 8 bits data line. If use low drive of the data
> line, it will cause DDR data access corrupt in lower address, so
> change the data line to high drive mode
> 
> This will fix the Linux kernel boot issue when use Lower address

Wait--does this mean that there is no separate chip selects for NAND and
DDR on this SoC?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Bo Shen]

Hi Albert,

On 07/17/2013 06:10 PM, Albert ARIBAUD wrote:
> Hi Bo,
>
> On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen <voice.shen@atmel.com>
> wrote:
>
>> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
>> and share the lower 8 bits data line. If use low drive of the data
>> line, it will cause DDR data access corrupt in lower address, so
>> change the data line to high drive mode
>>
>> This will fix the Linux kernel boot issue when use Lower address
>
> Wait--does this mean that there is no separate chip selects for NAND and
> DDR on this SoC?

No. The NAND and DDR has there own chip selects.

This is chip specific. If DDR and NAND share data line, if we use low 
drive for EBI IO, it will cause DDR low memory address content corrupt. 
For example, if the DDR base address is 0x20000000, if we use 0x20008000 
as entry address of Linux kernel, then it won't boot up successfully. 
So, if we need to use low memory address, we need this to fix.

> Amicalement,
>

Best Regards,
Bo Shen

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Albert ARIBAUD]

Hi Bo,

On Wed, 17 Jul 2013 18:27:29 +0800, Bo Shen <voice.shen@atmel.com>
wrote:

> Hi Albert,
> 
> On 07/17/2013 06:10 PM, Albert ARIBAUD wrote:
> > Hi Bo,
> >
> > On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen <voice.shen@atmel.com>
> > wrote:
> >
> >> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
> >> and share the lower 8 bits data line. If use low drive of the data
> >> line, it will cause DDR data access corrupt in lower address, so
> >> change the data line to high drive mode
> >>
> >> This will fix the Linux kernel boot issue when use Lower address
> >
> > Wait--does this mean that there is no separate chip selects for NAND and
> > DDR on this SoC?
> 
> No. The NAND and DDR has there own chip selects.
> This is chip specific. If DDR and NAND share data line, if we use low 
> drive for EBI IO, it will cause DDR low memory address content corrupt. 
> For example, if the DDR base address is 0x20000000, if we use 0x20008000 
> as entry address of Linux kernel, then it won't boot up successfully. 
> So, if we need to use low memory address, we need this to fix.

I understand the symptom. What I don't undestand is how come NAND
does not keep its data lines in high impedance when its chip select is
inactive, which it is when DDR is being accessed.

> Best Regards,
> Bo Shen

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Michael Cashwell]

On Jul 17, 2013, at 6:42 AM, Albert ARIBAUD <albert.u.boot@aribaud.net> wrote:

> I understand the symptom. What I don't undestand is how come NAND
> does not keep its data lines in high impedance when its chip select is
> inactive, which it is when DDR is being accessed.

Chip selects prevent contention but they do not make the load vanish.
A deselected chip is not electrically the same as a non-populated chip,
especially at high frequencies.

Think of it another way. CMOS pins that are input-only are always high-z
but they still must be counted as a load when adding up the fan out seen
by the upstream output driver.

-Mike

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Albert ARIBAUD]

Hi Michael,

On Wed, 17 Jul 2013 07:27:36 -0400, Michael Cashwell
<mboards@prograde.net> wrote:

> On Jul 17, 2013, at 6:42 AM, Albert ARIBAUD <albert.u.boot@aribaud.net> wrote:
> 
> > I understand the symptom. What I don't undestand is how come NAND
> > does not keep its data lines in high impedance when its chip select is
> > inactive, which it is when DDR is being accessed.
> 
> Chip selects prevent contention but they do not make the load vanish.
> A deselected chip is not electrically the same as a non-populated chip,
> especially at high frequencies.
> 
> Think of it another way. CMOS pins that are input-only are always high-z
> but they still must be counted as a load when adding up the fan out seen
> by the upstream output driver.

They must be counted as load alright, I understand this. But that
leaves / leads to some questions:

- how come the issue never appeared so far? If this is so basic a
  problem, I would have expected it to show up as soon as the SoC gets
  frequent use.

- doesn't the driving lines' fan-out take this load into account?
  Again, I would expect a device's drive to be strong enough to
  overcome a few Hi-Zs, since that's an expected type of load.

- why is the issue not symmetric? Techno's CMOS or CMOS-like, I guess,
  so there is no reason to pull up rather than down. Unless there are
  pulldowns in the NAND or elsewhere, but then it's not Hi-Z any more.

> -Mike

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Michael Cashwell]

On Jul 17, 2013, at 9:05 AM, Albert ARIBAUD <albert.u.boot@aribaud.net> wrote:

> Hi Michael,
> 
> On Wed, 17 Jul 2013 07:27:36 -0400, Michael Cashwell
> <mboards@prograde.net> wrote:
> 
>> Chip selects prevent contention but they do not make the load vanish.
>> A deselected chip is not electrically the same as a non-populated chip,
>> especially at high frequencies.
>> 
>> Think of it another way. CMOS pins that are input-only are always high-z
>> but they still must be counted as a load when adding up the fan out seen
>> by the upstream output driver.
> 
> They must be counted as load alright, I understand this. But that
> leaves / leads to some questions:
> 
> - how come the issue never appeared so far? If this is so basic a
>  problem, I would have expected it to show up as soon as the SoC gets
>  frequent use.

Yes, agreed. It seems something changed. That needs to be understood.

> - doesn't the driving lines' fan-out take this load into account?
>  Again, I would expect a device's drive to be strong enough to
>  overcome a few Hi-Zs, since that's an expected type of load.

Setting the drive strength in the CPU is how fan out is accounted for.
(And I've seen similar settings in DDR chip so their drive is right
going the other way.)

In cases like this where it's adjustable the goal is to use the lowest
drive level that covers the fan out. Too high wastes power and generates
heat. Too low is unreliable.

> - why is the issue not symmetric? Techno's CMOS or CMOS-like, I guess,
>  so there is no reason to pull up rather than down. Unless there are
>  pulldowns in the NAND or elsewhere, but then it's not Hi-Z any more.


I'm not sure what symmetry you mean.

Very weak pulls are normal to avoid floating lines which can cause
damage to CMOS inputs. But these are in the 100K? range. That shouldn't
count more than one load. Strong pulls built into devices are a problem
when connected in parallel.

But again, it all does beg the question of what changed.

-Mike

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Bo Shen]

Hi Albert,

On 07/17/2013 06:42 PM, Albert ARIBAUD wrote:
> Hi Bo,
>
> On Wed, 17 Jul 2013 18:27:29 +0800, Bo Shen <voice.shen@atmel.com>
> wrote:
>
>> Hi Albert,
>>
>> On 07/17/2013 06:10 PM, Albert ARIBAUD wrote:
>>> Hi Bo,
>>>
>>> On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen <voice.shen@atmel.com>
>>> wrote:
>>>
>>>> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
>>>> and share the lower 8 bits data line. If use low drive of the data
>>>> line, it will cause DDR data access corrupt in lower address, so
>>>> change the data line to high drive mode
>>>>
>>>> This will fix the Linux kernel boot issue when use Lower address
>>>
>>> Wait--does this mean that there is no separate chip selects for NAND and
>>> DDR on this SoC?
>>
>> No. The NAND and DDR has there own chip selects.
>> This is chip specific. If DDR and NAND share data line, if we use low
>> drive for EBI IO, it will cause DDR low memory address content corrupt.
>> For example, if the DDR base address is 0x20000000, if we use 0x20008000
>> as entry address of Linux kernel, then it won't boot up successfully.
>> So, if we need to use low memory address, we need this to fix.
>
> I understand the symptom. What I don't undestand is how come NAND
> does not keep its data lines in high impedance when its chip select is
> inactive, which it is when DDR is being accessed.

So, I expect this patch be applied in v2013.07 release, would it be OK?

Hi Andreas,
   If no objection from Albert, would it be possible to apply it and 
include it in v2013.07 release.

>> Best Regards,
>> Bo Shen
>
> Amicalement,
>

Best Regards,
Bo Shen

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Albert ARIBAUD]

Hi Bo,

On Fri, 19 Jul 2013 09:51:02 +0800, Bo Shen <voice.shen@atmel.com>
wrote:

> Hi Albert,
> 
> On 07/17/2013 06:42 PM, Albert ARIBAUD wrote:
> > Hi Bo,
> >
> > On Wed, 17 Jul 2013 18:27:29 +0800, Bo Shen <voice.shen@atmel.com>
> > wrote:
> >
> >> Hi Albert,
> >>
> >> On 07/17/2013 06:10 PM, Albert ARIBAUD wrote:
> >>> Hi Bo,
> >>>
> >>> On Wed, 17 Jul 2013 17:14:17 +0800, Bo Shen <voice.shen@atmel.com>
> >>> wrote:
> >>>
> >>>> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
> >>>> and share the lower 8 bits data line. If use low drive of the data
> >>>> line, it will cause DDR data access corrupt in lower address, so
> >>>> change the data line to high drive mode
> >>>>
> >>>> This will fix the Linux kernel boot issue when use Lower address
> >>>
> >>> Wait--does this mean that there is no separate chip selects for NAND and
> >>> DDR on this SoC?
> >>
> >> No. The NAND and DDR has there own chip selects.
> >> This is chip specific. If DDR and NAND share data line, if we use low
> >> drive for EBI IO, it will cause DDR low memory address content corrupt.
> >> For example, if the DDR base address is 0x20000000, if we use 0x20008000
> >> as entry address of Linux kernel, then it won't boot up successfully.
> >> So, if we need to use low memory address, we need this to fix.
> >
> > I understand the symptom. What I don't undestand is how come NAND
> > does not keep its data lines in high impedance when its chip select is
> > inactive, which it is when DDR is being accessed.
> 
> So, I expect this patch be applied in v2013.07 release, would it be OK?
> 
> Hi Andreas,
>    If no objection from Albert, would it be possible to apply it and 
> include it in v2013.07 release.

I understand that I did read 'high drive' as "driving toward Vcc"
instead of "driving stronger", which answers my question about symmetry
-- by making it pointless, but hey. :)

That leaves two questions: why does this happens only now, and how was
the conclusion drawn that this is the right solution? I mean, the
stronger drive fixes the issue, so it's definitely HW, but maybe the
real issue is some other device on the bus being misconfigured, and
driving stronger just hides it.

As for applying it to 2013.07... At this point, Tom (added to To list)
will decide, if he has not already.

> Best Regards,
> Bo Shen

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Tom Rini]

On Wed, Jul 17, 2013 at 05:14:17PM +0800, Bo Shen wrote:

> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
> and share the lower 8 bits data line. If use low drive of the data
> line, it will cause DDR data access corrupt in lower address, so
> change the data line to high drive mode
> 
> This will fix the Linux kernel boot issue when use Lower address
> 
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
> ---
>  board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
> index 3013a42..66c4c1f 100644
> --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
> +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
> @@ -59,7 +59,7 @@ static void at91sam9n12ek_nand_hw_init(void)
>  	/* Configure databus */
>  	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
>  	/* Configure IO drive */
> -	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
> +	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
>  
>  	writel(csa, &matrix->ebicsa);
>  

So, the change is small and isolated, so I'm OK applying it to master
directly, once we've got acks.  But it sounds like there's a question of
"why does this fix the problem" and "how does the problem even happen?".

-- 
Tom
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[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Andreas Bießmann]

Hi all,

was on vacation, so answering late.

On 19.07.13 14:13, Tom Rini wrote:
> On Wed, Jul 17, 2013 at 05:14:17PM +0800, Bo Shen wrote:
> 
>> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
>> and share the lower 8 bits data line. If use low drive of the data
>> line, it will cause DDR data access corrupt in lower address, so
>> change the data line to high drive mode
>>
>> This will fix the Linux kernel boot issue when use Lower address
>>
>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>> ---
>>  board/atmel/at91sam9n12ek/at91sam9n12ek.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> index 3013a42..66c4c1f 100644
>> --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
>> @@ -59,7 +59,7 @@ static void at91sam9n12ek_nand_hw_init(void)
>>  	/* Configure databus */
>>  	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
>>  	/* Configure IO drive */
>> -	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
>> +	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
>>  
>>  	writel(csa, &matrix->ebicsa);
>>  
> 
> So, the change is small and isolated, so I'm OK applying it to master
> directly, once we've got acks.  But it sounds like there's a question of
> "why does this fix the problem" and "how does the problem even happen?".

Well, you have to know that the at91sam9n12 SoC is relatively new and
introduced alongside the at91sam9n12-ek board by
9e336903891f1c28be04f0b5503ca54939b2976a in this releases MW. The
question "how does the problem even happen" could therefore possibly
answered with "not enough testing before sending the patch".
I can't say much about that, cause I have no access to such a board and
have to rely on Bo's and Josh's input. So when Bo says it fixes a real
bug I believe in it.

To answer the second question we can have a look at the specs. I can
presume by looking at the specs that we need to switch the drive
strength for the data I/O pins to higher level for this board to fix the
problem mentioned in the commit message. You have to know that this
specific part (configuring EBI for NAND access) is copied from board to
board (yes, another point to consolidate in near future). And this
specific part is copied over from at91samx5ek which seems to work with
lower drive strength. Unfortunately the concrete limit of EBI
capacitance is not specified in specs for at91sam9n12 nor at91sam9x35
devices. More distracting this parameter (EBI_DRIVE) seems to have
different reset values in at91sam9n12 and atsam9x35 devices, at least
the specs say so ... Atmel guys, please have a look on that and update
your specs!
Especially fill the TBD field in at91sam9n12 spec p. 311 (EBI_DRIVE in
CCFG_EBICSA) in version 11063I?ATARM?17-Apr-13. And possibly check why
there is EBI_DRIVE default to 'low' for 9x5 and default to 'high' for
9n12. There is also another bug in the specs, when you have to decide
between 'high' and 'low' you cant say the 'low' is required for
'capacitance < TBD pF' and 'high' is required for 'capacitance < TBD
pF', presumably the 'high' part should be chosen for 'capacitance > TBD pF'.

So from my point of view this patch fixes an existing bug in a new board
introduced in this releases MW. It uses a fairly new SoC which is first
used in this new board. Therefore

Acked-by: Andreas Bie?mann <andreas.devel@googlemail.com>

And Tom, please apply this patch directly.

Best regards

Andreas Bie?mann

[U-Boot] [PATCH] arm: at91sam9n12: change EBI IO to high drive mode

[Bo Shen]

Hi Andreas,

On 07/21/2013 07:02 AM, Andreas Bie?mann wrote:
> To answer the second question we can have a look at the specs. I can
> presume by looking at the specs that we need to switch the drive
> strength for the data I/O pins to higher level for this board to fix the
> problem mentioned in the commit message. You have to know that this
> specific part (configuring EBI for NAND access) is copied from board to
> board (yes, another point to consolidate in near future). And this
> specific part is copied over from at91samx5ek which seems to work with
> lower drive strength. Unfortunately the concrete limit of EBI
> capacitance is not specified in specs for at91sam9n12 nor at91sam9x35
> devices. More distracting this parameter (EBI_DRIVE) seems to have
> different reset values in at91sam9n12 and atsam9x35 devices, at least
> the specs say so ... Atmel guys, please have a look on that and update
> your specs!
> Especially fill the TBD field in at91sam9n12 spec p. 311 (EBI_DRIVE in
> CCFG_EBICSA) in version 11063I?ATARM?17-Apr-13. And possibly check why
> there is EBI_DRIVE default to 'low' for 9x5 and default to 'high' for
> 9n12. There is also another bug in the specs, when you have to decide
> between 'high' and 'low' you cant say the 'low' is required for
> 'capacitance < TBD pF' and 'high' is required for 'capacitance < TBD
> pF', presumably the 'high' part should be chosen for 'capacitance > TBD pF'.

Thank for this information, I will check this with our colleagues.
Thanks again.

> So from my point of view this patch fixes an existing bug in a new board
> introduced in this releases MW. It uses a fairly new SoC which is first
> used in this new board. Therefore
>
> Acked-by: Andreas Bie?mann<andreas.devel@googlemail.com>
>
> And Tom, please apply this patch directly.
>
> Best regards
>
> Andreas Bie?mann

Best Regards,
Bo Shen

[U-Boot] arm: at91sam9n12: change EBI IO to high drive mode

[Tom Rini]

On Wed, Jul 17, 2013 at 05:14:17PM +0800, Bo Shen wrote:

> As both the DDR SDRAM and NAND flash connect to EBI on at91sam9n12
> and share the lower 8 bits data line. If use low drive of the data
> line, it will cause DDR data access corrupt in lower address, so
> change the data line to high drive mode
> 
> This will fix the Linux kernel boot issue when use Lower address
> 
> Signed-off-by: Bo Shen <voice.shen@atmel.com>
> Acked-by: Andreas Bie??mann <andreas.devel@googlemail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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