From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Fri, 19 Jul 2013 04:38:45 +0200 Subject: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific In-Reply-To: <51E85BD6.7010202@wwwdotorg.org> References: <1374174821-19981-1-git-send-email-thierry.reding@gmail.com> <51E85BD6.7010202@wwwdotorg.org> Message-ID: <20130719023843.GA14413@mithrandir> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote: > On 07/18/2013 01:13 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > > therefore uses a cache line size of 64 bytes. Move the cache line size > > setting to the per-SoC common configuration file. > > Tested-by: Stephen Warren > Reviewed-by: Stephen Warren Do these apply to patch 2 of this series as well? Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: not available URL: