* [U-Boot] Enabling L2 cache on mx53
@ 2013-08-19 13:55 Fabio Estevam
2013-08-19 15:16 ` Dirk Behme
0 siblings, 1 reply; 7+ messages in thread
From: Fabio Estevam @ 2013-08-19 13:55 UTC (permalink / raw)
To: u-boot
Hi,
I notice slow tftp transfer on mx53qsb and I suspected it could be due
to L2 cache being disabled.
Tried enabling with:
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,11 @@
#endif
mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #(1 << 1) /* enable l2 cache */
+ mcr 15, 0, r0, c1, c0, 1
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
,but still see the same low tftp throughput (720 kB/s - on mx28 I see
the double rate).
Any suggestions as to how properly enable L2 cache on mx53?
Thanks,
Fabio Estevam
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] Enabling L2 cache on mx53 2013-08-19 13:55 [U-Boot] Enabling L2 cache on mx53 Fabio Estevam @ 2013-08-19 15:16 ` Dirk Behme 2013-08-19 15:22 ` Fabio Estevam 0 siblings, 1 reply; 7+ messages in thread From: Dirk Behme @ 2013-08-19 15:16 UTC (permalink / raw) To: u-boot Am 19.08.2013 15:55, schrieb Fabio Estevam: > Hi, > > I notice slow tftp transfer on mx53qsb and I suspected it could be due > to L2 cache being disabled. > > Tried enabling with: > > --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S > +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S > @@ -45,6 +45,11 @@ > #endif > > mcr 15, 1, r0, c9, c0, 2 > + > + /* enable L2 cache */ > + mrc 15, 0, r0, c1, c0, 1 > + orr r0, r0, #(1 << 1) /* enable l2 cache */ > + mcr 15, 0, r0, c1, c0, 1 > .endm /* init_l2cc */ > > /* AIPS setup - Only setup MPROTx registers. > > > ,but still see the same low tftp throughput (720 kB/s - on mx28 I see > the double rate). > > Any suggestions as to how properly enable L2 cache on mx53? Is the mx53 L2 cache the same like on mx6? If so, besides enabling it, it needs a proper configuration. Have a look to https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5a5ca56e057d206db13461b84a7da3a3543e1206 https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=b3a9c315378ff811bf34393f2f0a6e8b9ffced3b Best regards Dirk ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] Enabling L2 cache on mx53 2013-08-19 15:16 ` Dirk Behme @ 2013-08-19 15:22 ` Fabio Estevam 2013-08-19 19:51 ` Marek Vasut 0 siblings, 1 reply; 7+ messages in thread From: Fabio Estevam @ 2013-08-19 15:22 UTC (permalink / raw) To: u-boot Hi Dirk, On Mon, Aug 19, 2013 at 12:16 PM, Dirk Behme <dirk.behme@gmail.com> wrote: > Is the mx53 L2 cache the same like on mx6? I think they are different. On mx6 the L2 cache controller is memory mapped ,but on mx53 there is no L2 cache entry in its memory map. Regards, Fabio Estevam ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] Enabling L2 cache on mx53 2013-08-19 15:22 ` Fabio Estevam @ 2013-08-19 19:51 ` Marek Vasut 2013-08-19 20:26 ` Fabio Estevam 0 siblings, 1 reply; 7+ messages in thread From: Marek Vasut @ 2013-08-19 19:51 UTC (permalink / raw) To: u-boot Dear Fabio Estevam, > Hi Dirk, > > On Mon, Aug 19, 2013 at 12:16 PM, Dirk Behme <dirk.behme@gmail.com> wrote: > > Is the mx53 L2 cache the same like on mx6? > > I think they are different. > > On mx6 the L2 cache controller is memory mapped ,but on mx53 there is > no L2 cache entry in its memory map. > > Regards, > > Fabio Estevam L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks). Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] Enabling L2 cache on mx53 2013-08-19 19:51 ` Marek Vasut @ 2013-08-19 20:26 ` Fabio Estevam 2013-08-19 20:31 ` Marek Vasut 0 siblings, 1 reply; 7+ messages in thread From: Fabio Estevam @ 2013-08-19 20:26 UTC (permalink / raw) To: u-boot Hi Marek, On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut <marex@denx.de> wrote: > L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no > configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- > Boot, then it's not on at all (and that sucks). This is what I have done: --- a/arch/arm/cpu/armv7/mx5/ lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 << 1) /* enable l2 cache */ + mcr 15, 0, r0, c1, c0, 1 .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. Anything else I am missing? ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] Enabling L2 cache on mx53 2013-08-19 20:26 ` Fabio Estevam @ 2013-08-19 20:31 ` Marek Vasut 2013-08-20 7:21 ` Stefano Babic 0 siblings, 1 reply; 7+ messages in thread From: Marek Vasut @ 2013-08-19 20:31 UTC (permalink / raw) To: u-boot Dear Fabio Estevam, > Hi Marek, > > On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut <marex@denx.de> wrote: > > L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, > > there's no configuration. Not even Linux enables the L2CC on MX53, so if > > it's not on in U- Boot, then it's not on at all (and that sucks). > > This is what I have done: > > --- a/arch/arm/cpu/armv7/mx5/ > lowlevel_init.S > +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S > @@ -45,6 +45,11 @@ > #endif > > mcr 15, 1, r0, c9, c0, 2 > + > + /* enable L2 cache */ > + mrc 15, 0, r0, c1, c0, 1 > + orr r0, r0, #(1 << 1) /* enable l2 cache */ > + mcr 15, 0, r0, c1, c0, 1 > .endm /* init_l2cc */ > > /* AIPS setup - Only setup MPROTx registers. > > Anything else I am missing? Try profiling the RX routine, maybe it's looping somewhere there for too long. Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] Enabling L2 cache on mx53 2013-08-19 20:31 ` Marek Vasut @ 2013-08-20 7:21 ` Stefano Babic 0 siblings, 0 replies; 7+ messages in thread From: Stefano Babic @ 2013-08-20 7:21 UTC (permalink / raw) To: u-boot Hi Marek, On 19/08/2013 22:31, Marek Vasut wrote: > Dear Fabio Estevam, > >> Hi Marek, >> >> On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut <marex@denx.de> wrote: >>> L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, >>> there's no configuration. Not even Linux enables the L2CC on MX53, so if >>> it's not on in U- Boot, then it's not on at all (and that sucks). >> >> This is what I have done: >> >> --- a/arch/arm/cpu/armv7/mx5/ >> lowlevel_init.S >> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S >> @@ -45,6 +45,11 @@ >> #endif >> >> mcr 15, 1, r0, c9, c0, 2 >> + >> + /* enable L2 cache */ >> + mrc 15, 0, r0, c1, c0, 1 >> + orr r0, r0, #(1 << 1) /* enable l2 cache */ >> + mcr 15, 0, r0, c1, c0, 1 >> .endm /* init_l2cc */ >> >> /* AIPS setup - Only setup MPROTx registers. >> >> Anything else I am missing? > > Try profiling the RX routine, maybe it's looping somewhere there for too long. > But the RX routine belongs to the FEC driver that it is used by all i.MXes. Is there maybe a problem with the phy and the negotiated speed is less than expected ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-08-20 7:21 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-08-19 13:55 [U-Boot] Enabling L2 cache on mx53 Fabio Estevam 2013-08-19 15:16 ` Dirk Behme 2013-08-19 15:22 ` Fabio Estevam 2013-08-19 19:51 ` Marek Vasut 2013-08-19 20:26 ` Fabio Estevam 2013-08-19 20:31 ` Marek Vasut 2013-08-20 7:21 ` Stefano Babic
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