From: Tom Rini <trini@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Date: Tue, 20 Aug 2013 15:38:00 -0400 [thread overview]
Message-ID: <20130820193800.GD2644@bill-the-cat> (raw)
In-Reply-To: <1377004656-17435-1-git-send-email-r.sricharan@ti.com>
On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote:
> Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
> software leveling. This was done since hardware leveling was not
> working. Now that the right sequence to do hw leveling is identified,
> use it. This is required for EMIF clockdomain to idle and come back
> during lowpower usecases.
[snip]
> #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
OK, so this reminds me, should we be printing out something more now
then, when we're calculating timings, rather than using precalculated
ones? Or is that a different issue I'm thinking of?
--
Tom
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next prev parent reply other threads:[~2013-08-20 19:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-20 13:17 [U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling Sricharan R
2013-08-20 19:38 ` Tom Rini [this message]
2013-08-21 4:22 ` Sricharan R
2013-08-22 11:39 ` Sricharan R
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