[U-Boot] [PATCH v2 2/7] USB: XHCI: Add xHCI host controller support for Exynos5

Dan Murphy
2013-09-03T15:03:07Z

On 08/21/2013 05:12 AM, Vivek Gautam wrote:
> This adds driver layer for xHCI controller in Samsung's
> exynos5 soc. This interacts with xHCI host controller stack.
>
> Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Cc: Julius Werner <jwerner@chromium.org>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Cc: Dan Murphy <dmurphy@ti.com>
> Cc: Marek Vasut <marex@denx.de>
> ---
> arch/arm/include/asm/arch-exynos/cpu.h | 8 +
> arch/arm/include/asm/arch-exynos/xhci-exynos.h | 90 +++++++
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/xhci-exynos5.c | 324 ++++++++++++++++++++++++
> include/linux/usb/dwc3.h | 190 ++++++++++++++
> 5 files changed, 613 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/xhci-exynos.h
> create mode 100644 drivers/usb/host/xhci-exynos5.c
> create mode 100644 include/linux/usb/dwc3.h
>
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
> index cb924fb..0d2b511 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -50,6 +50,8 @@
> #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
>
> /* EXYNOS4X12 */
> #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
> @@ -85,6 +87,8 @@
> #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
> #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
> +#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
>
> /* EXYNOS5 Common*/
> #define EXYNOS5_I2C_SPACING 0x10000
> @@ -103,6 +107,8 @@
> #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
> #define EXYNOS5_GPIO_PART1_BASE 0x11400000
> #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
> +#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
> +#define EXYNOS5_USB3PHY_BASE 0x12100000
> #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
> #define EXYNOS5_USBPHY_BASE 0x12130000
> #define EXYNOS5_USBOTG_BASE 0x12140000
> @@ -217,7 +223,9 @@ SAMSUNG_BASE(swreset, SWRESET)
> SAMSUNG_BASE(timer, PWMTIMER_BASE)
> SAMSUNG_BASE(uart, UART_BASE)
> SAMSUNG_BASE(usb_phy, USBPHY_BASE)
> +SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
> SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
> +SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
> SAMSUNG_BASE(usb_otg, USBOTG_BASE)
> SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
> SAMSUNG_BASE(power, POWER_BASE)
> diff --git a/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/arch/arm/include/asm/arch-exynos/xhci-exynos.h
> new file mode 100644
> index 0000000..acbb37d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/xhci-exynos.h
> @@ -0,0 +1,90 @@
> +/* Copyright (c) 2012 Samsung Electronics Co. Ltd
> + *
> + * Exynos Phy register definitions
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */

Needs new license unless you only want to restrict this to GPL v2

> +
> +#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
> +#define _ASM_ARCH_XHCI_EXYNOS_H_
> +
> +/* Phy register MACRO definitions */
> +
> +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
> +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
> +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
> +
> +#define PHYUTMI_OTGDISABLE (1 << 6)
> +#define PHYUTMI_FORCESUSPEND (1 << 1)
> +#define PHYUTMI_FORCESLEEP (1 << 0)
> +
> +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
> +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
> +
> +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
> +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
> +
> +#define PHYCLKRST_SSC_EN (0x1 << 20)
> +#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
> +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
> +
> +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
> +
> +#define PHYCLKRST_FSEL_MASK (0x3f << 5)
> +#define PHYCLKRST_FSEL(_x) ((_x) << 5)
> +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
> +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
> +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
> +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
> +
> +#define PHYCLKRST_RETENABLEN (0x1 << 4)
> +
> +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
> +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
> +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
> +
> +#define PHYCLKRST_PORTRESET (0x1 << 1)
> +#define PHYCLKRST_COMMONONN (0x1 << 0)
> +
> +#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
> +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
> +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
> +
> +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
> +#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
> +
> +#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
> +#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
> +
> +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
> +
> +#define FSEL_CLKSEL_24M (0x5)
> +
> +/* XHCI PHY register structure */
> +struct exynos_usb3_phy {
> + unsigned int reserve1;
> + unsigned int link_system;
> + unsigned int phy_utmi;
> + unsigned int phy_pipe;
> + unsigned int phy_clk_rst;
> + unsigned int phy_reg0;
> + unsigned int phy_reg1;
> + unsigned int phy_param0;
> + unsigned int phy_param1;
> + unsigned int phy_term;
> + unsigned int phy_test;
> + unsigned int phy_adp;
> + unsigned int phy_batchg;
> + unsigned int phy_resume;
> + unsigned int reserve2[3];
> + unsigned int link_port;
> +};
> +
> +#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 6bd6c86..eb50bc1 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -44,6 +44,7 @@ COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
>
> # xhci
> COBJS-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
> +COBJS-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
> new file mode 100644
> index 0000000..d5796c0
> --- /dev/null
> +++ b/drivers/usb/host/xhci-exynos5.c
> @@ -0,0 +1,324 @@
> +/*
> + * SAMSUNG EXYNOS5 USB HOST XHCI Controller
> + *
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + * Vivek Gautam <gautam.vivek@samsung.com>
> + * Vikas Sajjan <vikas.sajjan@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +

Needs new license

> +/*
> + * This file is a conglomeration for DWC3-init sequence and further
> + * exynos5 specific PHY-init sequence.
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <libfdt.h>
> +#include <malloc.h>
> +#include <usb.h>
> +#include <watchdog.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/power.h>
> +#include <asm/arch/xhci-exynos.h>
> +#include <asm-generic/errno.h>
> +#include <linux/compat.h>
> +#include <linux/usb/dwc3.h>
> +
> +#include "xhci.h"
> +
> +/* Declare global data pointer */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/**
> + * Contains pointers to register base addresses
> + * for the usb controller.
> + */
> +struct exynos_xhci {
> + struct exynos_usb3_phy *usb3_phy;
> + struct xhci_hccr *hcd;
> + struct dwc3 *dwc3_reg;
> +};
> +
> +static struct exynos_xhci exynos;
> +
> +#ifdef CONFIG_OF_CONTROL
> +static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos)
> +{
> + fdt_addr_t addr;
> + unsigned int node;
> + int depth;
> +
> + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI);
> + if (node <= 0) {
> + debug("XHCI: Can't get device node for xhci\n");
> + return -ENODEV;
> + }
> +
> + /*
> + * Get the base address for XHCI controller from the device node
> + */
> + addr = fdtdec_get_addr(blob, node, "reg");
> + if (addr == FDT_ADDR_T_NONE) {
> + debug("Can't get the XHCI register base address\n");
> + return -ENXIO;
> + }
> + exynos->hcd = (struct xhci_hccr *)addr;
> +
> + depth = 0;
> + node = fdtdec_next_compatible_subnode(blob, node,
> + COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
> + if (node <= 0) {
> + debug("XHCI: Can't get device node for usb3-phy controller\n");
> + return -ENODEV;
> + }
> +
> + /*
> + * Get the base address for usbphy from the device node
> + */
> + exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node,
> + "reg");
> + if (exynos->usb3_phy == NULL) {
> + debug("Can't get the usbphy register address\n");
> + return -ENXIO;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
> +{
> + u32 reg;
> +
> + /* enabling usb_drd phy */
> + set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
> +
> + /* Reset USB 3.0 PHY */
> + writel(0x0, &phy->phy_reg0);
> +
> + clrbits_le32(&phy->phy_param0,
> + /* Select PHY CLK source */
> + PHYPARAM0_REF_USE_PAD |
> + /* Set Loss-of-Signal Detector sensitivity */
> + PHYPARAM0_REF_LOSLEVEL_MASK);
> + setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
> +
> + writel(0x0, &phy->phy_resume);
> +
> + /*
> + * Setting the Frame length Adj value[6:1] to default 0x20
> + * See xHCI 1.0 spec, 5.2.4
> + */
> + setbits_le32(&phy->link_system,
> + LINKSYSTEM_XHCI_VERSION_CONTROL |
> + LINKSYSTEM_FLADJ(0x20));
> +
> + /* Set Tx De-Emphasis level */
> + clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
> + setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
> +
> + setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
> +
> + /* PHYTEST POWERDOWN Control */
> + clrbits_le32(&phy->phy_test,
> + PHYTEST_POWERDOWN_SSP |
> + PHYTEST_POWERDOWN_HSP);
> +
> + /* UTMI Power Control */
> + writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
> +
> + /* Use core clock from main PLL */
> + reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
> + /* Default 24Mhz crystal clock */
> + PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
> + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x88) |
> + /* Force PortReset of PHY */
> + PHYCLKRST_PORTRESET |
> + /* Digital power supply in normal operating mode */
> + PHYCLKRST_RETENABLEN |
> + /* Enable ref clock for SS function */
> + PHYCLKRST_REF_SSP_EN |
> + /* Enable spread spectrum */
> + PHYCLKRST_SSC_EN |
> + /* Power down HS Bias and PLL blocks in suspend mode */
> + PHYCLKRST_COMMONONN;
> +
> + writel(reg, &phy->phy_clk_rst);
> +
> + /* giving time to Phy clock to settle before resetting */
> + udelay(10);
> +
> + reg &= ~PHYCLKRST_PORTRESET;
> + writel(reg, &phy->phy_clk_rst);
> +}
> +
> +static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
> +{
> + setbits_le32(&phy->phy_utmi,
> + PHYUTMI_OTGDISABLE |
> + PHYUTMI_FORCESUSPEND |
> + PHYUTMI_FORCESLEEP);
> +
> + clrbits_le32(&phy->phy_clk_rst,
> + PHYCLKRST_REF_SSP_EN |
> + PHYCLKRST_SSC_EN |
> + PHYCLKRST_COMMONONN);
> +
> + /* PHYTEST POWERDOWN Control to remove leakage current */
> + setbits_le32(&phy->phy_test,
> + PHYTEST_POWERDOWN_SSP |
> + PHYTEST_POWERDOWN_HSP);
> +
> + /* disabling usb_drd phy */
> + set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
> +}
> +
> +void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
> +{
> + clrsetbits_le32(&dwc3_reg->g_ctl,
> + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
> + DWC3_GCTL_PRTCAPDIR(mode));
> +}
> +
> +static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
> +{
> + /* Before Resetting PHY, put Core in Reset */
> + setbits_le32(&dwc3_reg->g_ctl,
> + DWC3_GCTL_CORESOFTRESET);
> +
> + /* Assert USB3 PHY reset */
> + setbits_le32(&dwc3_reg->g_usb3pipectl[0],
> + DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> + /* Assert USB2 PHY reset */
> + setbits_le32(&dwc3_reg->g_usb2phycfg,
> + DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +
> + mdelay(100);
> +
> + /* Clear USB3 PHY reset */
> + clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
> + DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> + /* Clear USB2 PHY reset */
> + clrbits_le32(&dwc3_reg->g_usb2phycfg,
> + DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +
> + /* After PHYs are stable we can take Core out of reset state */
> + clrbits_le32(&dwc3_reg->g_ctl,
> + DWC3_GCTL_CORESOFTRESET);
> +}
> +
> +static int dwc3_core_init(struct dwc3 *dwc3_reg)
> +{
> + u32 reg;
> + u32 revision;
> + unsigned int dwc3_hwparams1;
> +
> + revision = readl(&dwc3_reg->g_snpsid);
> + /* This should read as U3 followed by revision number */
> + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
> + printf("this is not a DesignWare USB3 DRD Core\n");

Use puts for non-arg based logging

> + return -1;
> + }
> +
> + dwc3_core_soft_reset(dwc3_reg);
> +
> + dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
> +
> + reg = readl(&dwc3_reg->g_ctl);
> + reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> + reg &= ~DWC3_GCTL_DISSCRAMBLE;
> + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
> + case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> + reg &= ~DWC3_GCTL_DSBLCLKGTNG;
> + break;
> + default:
> + debug("No power optimization available\n");
> + }
> +
> + /*
> + * WORKAROUND: DWC3 revisions <1.90a have a bug
> + * where the device can fail to connect at SuperSpeed
> + * and falls back to high-speed mode which causes
> + * the device to enter a Connect/Disconnect loop
> + */
> + if ((revision & DWC3_REVISION_MASK) < 0x190a)
> + reg |= DWC3_GCTL_U2RSTECN;
> +
> + writel(reg, &dwc3_reg->g_ctl);
> +
> + return 0;
> +}
> +
> +static int exynos_xhci_core_init(struct exynos_xhci *exynos)
> +{
> + int ret;
> +
> + exynos5_usb3_phy_init(exynos->usb3_phy);
> +
> + ret = dwc3_core_init(exynos->dwc3_reg);
> + if (ret) {
> + debug("failed to initialize core\n");
> + return -1;
> + }
> +
> + /* We are hard-coding DWC3 core to Host Mode */
> + dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> +
> + return 0;
> +}
> +
> +static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
> +{
> + exynos5_usb3_phy_exit(exynos->usb3_phy);
> +}
> +
> +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
> +{
> + struct exynos_xhci *ctx = &exynos;
> +
> +#ifdef CONFIG_OF_CONTROL
> + exynos_usb3_parse_dt(gd->fdt_blob, ctx);
> +#else
> + ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();
> + ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();
> +#endif
> +
> + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
> +
> + exynos_xhci_core_init(ctx);
> +
> + *hccr = (ctx->hcd);
> + *hcor = (struct xhci_hcor *)((uint32_t) *hccr
> + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> + debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n",
> + (uint32_t)*hccr, (uint32_t)*hcor,
> + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> + return 0;
> +}
> +
> +void xhci_hcd_stop(int index)
> +{
> + struct exynos_xhci *ctx = &exynos;
> +
> + exynos_xhci_core_exit(ctx);
> +}
> diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
> new file mode 100644
> index 0000000..933c894
> --- /dev/null
> +++ b/include/linux/usb/dwc3.h
> @@ -0,0 +1,190 @@
> +/* include/linux/usb/dwc3.h
> + *
> + * Copyright (c) 2012 Samsung Electronics Co. Ltd
> + *
> + * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +

Needs new license unless you only want to restrict this to GPL v2

> +#ifndef __DWC3_H_
> +#define __DWC3_H_
> +
> +/* Global constants */
> +#define DWC3_ENDPOINTS_NUM 32
> +
> +#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
> +#define DWC3_EVENT_TYPE_MASK 0xfe
> +
> +#define DWC3_EVENT_TYPE_DEV 0
> +#define DWC3_EVENT_TYPE_CARKIT 3
> +#define DWC3_EVENT_TYPE_I2C 4
> +
> +#define DWC3_DEVICE_EVENT_DISCONNECT 0
> +#define DWC3_DEVICE_EVENT_RESET 1
> +#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
> +#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
> +#define DWC3_DEVICE_EVENT_WAKEUP 4
> +#define DWC3_DEVICE_EVENT_EOPF 6
> +#define DWC3_DEVICE_EVENT_SOF 7
> +#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
> +#define DWC3_DEVICE_EVENT_CMD_CMPL 10
> +#define DWC3_DEVICE_EVENT_OVERFLOW 11
> +
> +#define DWC3_GEVNTCOUNT_MASK 0xfffc
> +#define DWC3_GSNPSID_MASK 0xffff0000
> +#define DWC3_GSNPSID_SHIFT 16
> +#define DWC3_GSNPSREV_MASK 0xffff
> +
> +#define DWC3_REVISION_MASK 0xffff
> +
> +#define DWC3_REG_OFFSET 0xC100
> +
> +struct g_event_buffer {
> + u64 g_evntadr;
> + u32 g_evntsiz;
> + u32 g_evntcount;
> +};
> +
> +struct d_physical_endpoint {
> + u32 d_depcmdpar2;
> + u32 d_depcmdpar1;
> + u32 d_depcmdpar0;
> + u32 d_depcmd;
> +};
> +
> +struct dwc3 { /* offset: 0xC100 */
> + u32 g_sbuscfg0;
> + u32 g_sbuscfg1;
> + u32 g_txthrcfg;
> + u32 g_rxthrcfg;
> + u32 g_ctl;
> +
> + u32 reserved1;
> +
> + u32 g_sts;
> +
> + u32 reserved2;
> +
> + u32 g_snpsid;
> + u32 g_gpio;
> + u32 g_uid;
> + u32 g_uctl;
> + u64 g_buserraddr;
> + u64 g_prtbimap;
> +
> + u32 g_hwparams0;
> + u32 g_hwparams1;
> + u32 g_hwparams2;
> + u32 g_hwparams3;
> + u32 g_hwparams4;
> + u32 g_hwparams5;
> + u32 g_hwparams6;
> + u32 g_hwparams7;
> +
> + u32 g_dbgfifospace;
> + u32 g_dbgltssm;
> + u32 g_dbglnmcc;
> + u32 g_dbgbmu;
> + u32 g_dbglspmux;
> + u32 g_dbglsp;
> + u32 g_dbgepinfo0;
> + u32 g_dbgepinfo1;
> +
> + u64 g_prtbimap_hs;
> + u64 g_prtbimap_fs;
> +
> + u32 reserved3[28];
> +
> + u32 g_usb2phycfg[16];
> + u32 g_usb2i2cctl[16];
> + u32 g_usb2phyacc[16];
> + u32 g_usb3pipectl[16];
> +
> + u32 g_txfifosiz[32];
> + u32 g_rxfifosiz[32];
> +
> + struct g_event_buffer g_evnt_buf[32];
> +
> + u32 g_hwparams8;
> +
> + u32 reserved4[63];
> +
> + u32 d_cfg;
> + u32 d_ctl;
> + u32 d_evten;
> + u32 d_sts;
> + u32 d_gcmdpar;
> + u32 d_gcmd;
> +
> + u32 reserved5[2];
> +
> + u32 d_alepena;
> +
> + u32 reserved6[55];
> +
> + struct d_physical_endpoint d_phy_ep_cmd[32];
> +
> + u32 reserved7[128];
> +
> + u32 o_cfg;
> + u32 o_ctl;
> + u32 o_evt;
> + u32 o_evten;
> + u32 o_sts;
> +
> + u32 reserved8[3];
> +
> + u32 adp_cfg;
> + u32 adp_ctl;
> + u32 adp_evt;
> + u32 adp_evten;
> +
> + u32 bc_cfg;
> +
> + u32 reserved9;
> +
> + u32 bc_evt;
> + u32 bc_evten;
> +};
> +
> +/* Global Configuration Register */
> +#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
> +#define DWC3_GCTL_U2RSTECN (1 << 16)
> +#define DWC3_GCTL_RAMCLKSEL(x) \
> + (((x) & DWC3_GCTL_CLK_MASK) << 6)
> +#define DWC3_GCTL_CLK_BUS (0)
> +#define DWC3_GCTL_CLK_PIPE (1)
> +#define DWC3_GCTL_CLK_PIPEHALF (2)
> +#define DWC3_GCTL_CLK_MASK (3)
> +#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
> +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
> +#define DWC3_GCTL_PRTCAP_HOST 1
> +#define DWC3_GCTL_PRTCAP_DEVICE 2
> +#define DWC3_GCTL_PRTCAP_OTG 3
> +#define DWC3_GCTL_CORESOFTRESET (1 << 11)
> +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
> +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
> +#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
> +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
> +
> +/* Global HWPARAMS1 Register */
> +#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
> +#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
> +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
> +
> +/* Global USB2 PHY Configuration Register */
> +#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
> +#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
> +
> +/* Global USB3 PIPE Control Register */
> +#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
> +#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
> +
> +/* Global TX Fifo Size Register */
> +#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
> +#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
> +
> +#endif /* __DWC3_H_ */

total: 0 errors, 0 warnings, 13 checks, 644 lines checked

--
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Dan Murphy