From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Date: Tue, 1 Oct 2013 17:06:38 +0200 Subject: [U-Boot] [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX In-Reply-To: <5FBF8E85CA34454794F0F7ECBA79798F37D5917AD7@HQMAIL04.nvidia.com> References: <1379966870-4087-1-git-send-email-treding@nvidia.com> <1379966870-4087-2-git-send-email-treding@nvidia.com> <5FBF8E85CA34454794F0F7ECBA79798F37D5917AD7@HQMAIL04.nvidia.com> Message-ID: <20131001150637.GB5262@ulmo.nvidia.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Sep 30, 2013 at 02:25:57PM -0700, Tom Warren wrote: > Thierry, > > > -----Original Message----- > > From: Thierry Reding [mailto:thierry.reding at gmail.com] > > Sent: Monday, September 23, 2013 1:08 PM > > To: Tom Warren > > Cc: u-boot at lists.denx.de > > Subject: [PATCH v2 2/2] Tegra114: Do not program CPCON field for PLLX > > > > PLLX no longer has the CPCON field on Tegra114, so do not attempt to > > program it. > > > > Signed-off-by: Thierry Reding > > --- > > Changes in v2: > > - new patch > > > > arch/arm/cpu/arm720t/tegra-common/cpu.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c > > b/arch/arm/cpu/arm720t/tegra-common/cpu.c > > index aa1e04f..5ab2ebf 100644 > > --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c > > +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c > > @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int > > pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, > > u32 divp, u32 cpcon) > > { > > + int chip = tegra_get_chip(); > > u32 reg; > > > > /* If PLLX is already enabled, just return */ @@ -151,7 +152,8 @@ int > > pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, > > writel(reg, &pll->pll_base); > > > > /* Set cpcon to PLLX_MISC */ > > - reg = (cpcon << PLL_CPCON_SHIFT); > > + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) > > + reg = (cpcon << PLL_CPCON_SHIFT); > If it's not a T20/T30, reg is still set to the PLLX_BASE setting from above. It'll then be written to PLLX_MISC w/bad bits below. > You need to set a default, or read pllx_misc first. Ugh... you're right of course. Sent a v3 with reg = 0 in the else branch. Thanks, Thierry -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: not available URL: