[U-Boot] [PATCH v5 0/8] ARMv7: Add HYP mode switching support

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Hi Andre,

On Thu, 19 Sep 2013 18:06:38 +0200, Andre Przywara
<andre.przywara@linaro.org> wrote:

> (for GIT URL and Changelog see below)
> 
> ARM CPUs with the virtualization extension have a new mode called
> HYP mode, which allows hypervisors to safely control and monitor
> guests. The current hypervisor implementations (KVM and Xen)
> require the kernel to be entered in that HYP mode.
> 
> This patch series introduces a configuration variable
> CONFIG_ARMV7_VIRT which enables code to switch all cores into HYP
> mode. This is done automatically during execution of the bootm
> command.
> 
> The process of switching into HYP mode requires the CPU to be in
> secure state initially when entering u-boot, it will then setup some
> register and switch to non-secure state. This requires the GIC to be
> programmed properly first. Explanations about the details are in the
> commit messages of the respective patches.
> 
> The patches are structured like this:
> 1/8: prepare header file
> 2/8: add monitor handler (assembly)
> 3/8: add per CPU non-secure switch routine (assembly)
> 4/8: add system wide non-secure setup (C)
> 5/8: trigger non-secure switch during bootm command
> 6/8: add generic SMP functionality
> 7/8: add HYP mode switching
> 8/8: board specific code for ARM Versatile Express TC2
> 
> Since up to patch 6/8 this code works on non-virtualization capable
> CPUs also and as there has been a request, there is now a second
> configuration variable CONFIG_ARMV7_NONSEC, which omits the final
> HYP mode switch and just goes into non-secure SVC state.
> You can specify either (or none) of them, the code cares about
> the dependency.
> 
> The code aims to be as generic as possible, though currently it has
> only been tested on the Versatile Express TC-2 board. The last patch
> thus enables the feature for that board and should serve as an
> example for supporting other boards.
> I have had reports from different parties of successful adaptions to
> other boards as well (Arndale, Cubieboard, Chromebook), so I will
> create a hypmode-ports branch in the below repository to collect
> those patches and prepare them for upstreaming.
> 
> For convenience there is a GIT tree which you can pull these patches
> from ("hypmode_v5" branch):
> git://git.linaro.org/people/aprzywara/u-boot.git
> 
> Changes RFC..v1
> * not a dedicated command anymore, code run by bootm & friends
> * protecting code with #ifdefs to avoid unnecessary inclusion and
>   accidental crashing (when accessing restricted registers)
> * moving prototypes to header file to meet checkpatch recommendation
> * adding comment as proposed by Christoffer
> 
> Changes v1..v2
> mostly style and code layout changes 
> * restructure assembly code to live in a new file and not start.S
> * split smp, nonsec_init and hyp_init to be separate functions
> * used named constants from common header files
> * split C function to be more readable
> * extend comments to be more precise and elaborate
> * add provision to override GIC base address (needed for Arndale?)
> * add configuration variable to enable VExpress specific SMP code
> * use writel/readl for MMIO GIC accesses
> * remove superfluous isb instructions
> * more minor fixes
> 
> Changes v2..v3
> * fix clobbering of GICC address actually spoiling the stack
> * do CNTFRQ setup in assembly per core (and not only once per SoC)
> * moving the new code files into arch/arm/cpu/armv7
> * add config variable for doing non-secure switch only
> * use actual HYP and secure instructions mnemonics instead of
>   the encoded byte sequence. This requires more recent compilers.
> * make the identification of the CPU core more robust and saner
> * use enum for error codes and rename them
> * lots of smaller layout and style fixes
> 
> Changes v3..v4
> * mask reserved bits in CBAR register
> * move the VExpress board specific SMP code into the board directory
> * embed error reporting in the respective functions and getting
>   rid of the error code enum at all (by popular demand ;-)
> * minor style fixes
> 
> Changes v4..v5:
> * remove unneeded padding in exception table
> * only clear unbanked interrupts in GIC distributor for non-secure
> * add a default weak implementation for the smp_waitloop() function,
>   there only needs to be provided the address of the SMP pen now
> * fix compilation error with non-A15 VExpress boards
> * adding patch specific changelogs for v3..v4 and v4..v5
> 
> Please review, comment ... and commit ;-)
> 
> Contributions and comments to support other boards are welcome.
> 
> Andre Przywara (8):
>   ARM: prepare armv7.h to be included from assembly source
>   ARM: add secure monitor handler to switch to non-secure state
>   ARM: add assembly routine to switch to non-secure state
>   ARM: add C function to switch to non-secure state
>   ARM: trigger non-secure state switch during bootm execution
>   ARM: add SMP support for non-secure switch
>   ARM: extend non-secure switch to also go into HYP mode
>   ARM: VExpress: enable ARMv7 virt support for VExpress A15
> 
>  arch/arm/cpu/armv7/Makefile             |   5 +
>  arch/arm/cpu/armv7/nonsec_virt.S        | 208 ++++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/virt-v7.c            | 173 ++++++++++++++++++++++++++
>  arch/arm/include/asm/armv7.h            |  33 ++++-
>  arch/arm/include/asm/gic.h              |  19 +++
>  arch/arm/lib/bootm.c                    |  18 +++
>  board/armltd/vexpress/vexpress_common.c |  15 +++
>  include/common.h                        |   2 +
>  include/configs/vexpress_ca15_tc2.h     |   5 +-
>  9 files changed, 476 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S
>  create mode 100644 arch/arm/cpu/armv7/virt-v7.c
>  create mode 100644 arch/arm/include/asm/gic.h

Series applied to u-boot-arm/master, with the 'empty line at EOF'
warning in 2/8 fixed.

Amicalement,
-- 
Albert.