* [U-Boot] [PATCH v2 1/6] usb: omap: Move the xhci-omap header file to common location
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 2/6] usb: omap5: Update the board_usb_init api Dan Murphy
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Moving the xhci-omap header to a more global location so that
other code can reference this code.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - Reformatted patch with -M - http://patchwork.ozlabs.org/patch/281933/
drivers/usb/host/xhci-omap.c | 2 +-
.../arch-omap5 => include/linux/usb}/xhci-omap.h | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename {arch/arm/include/asm/arch-omap5 => include/linux/usb}/xhci-omap.h (100%)
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index f4e41fd..a8702da 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -15,10 +15,10 @@
#include <asm/omap_common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/xhci-omap.h>
#include <linux/compat.h>
#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
#include "xhci.h"
diff --git a/arch/arm/include/asm/arch-omap5/xhci-omap.h b/include/linux/usb/xhci-omap.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap5/xhci-omap.h
rename to include/linux/usb/xhci-omap.h
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 2/6] usb: omap5: Update the board_usb_init api
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 1/6] usb: omap: Move the xhci-omap header file to common location Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 3/6] usb: omap: Move the usb phy code to the usb/phy directory Dan Murphy
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Recent patches declares board_usb_init function prototype for a new
usb architecture.
Turning on the OMAP_XHCI defines cause a redefinition compiler failure.
So update the board_usb_init to the latest prototype.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - Adopted to board_usb_init and not create a new API - http://patchwork.ozlabs.org/patch/281931/
board/ti/omap5_uevm/evm.c | 2 +-
drivers/usb/host/xhci-omap.c | 7 ++++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 228df29..6a01200 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -219,7 +219,7 @@ void usb_hub_reset_devices(int port)
*
* @return 0
*/
-int board_usb_init(void)
+int board_usb_init(int index, enum board_usb_init_type init)
{
int ret;
#ifdef CONFIG_PALMAS_USB_SS_PWR
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index a8702da..4f98c77 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -182,11 +182,12 @@ static void omap_enable_phy_clocks(struct omap_xhci *omap)
};
-inline int __board_usb_init(void)
+inline int __board_usb_init(int index, enum board_usb_init_type init)
{
return 0;
}
-int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+int board_usb_init(int index, enum board_usb_init_type init) \
+ __attribute__((weak, alias("__board_usb_init")));
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
@@ -295,7 +296,7 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
- ret = board_usb_init();
+ ret = board_usb_init(index, USB_INIT_HOST);
if (ret != 0) {
puts("Failed to initialize board for USB\n");
return ret;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 3/6] usb: omap: Move the usb phy code to the usb/phy directory
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 1/6] usb: omap: Move the xhci-omap header file to common location Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 2/6] usb: omap5: Update the board_usb_init api Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 4/6] usb: dra7xx: Add support for dra7xx xhci USB host Dan Murphy
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Moving the usb/phy code from xhci-omap to the usb/phy directory
and moving the associated phy code over to the new file.
Newer TI processors adding xHCI support will have different PHY configurations
so therefore abstracting this code away will prevent messing around with the
xhci-omap file itself.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - No code change just a patch format change for copied code - http://patchwork.ozlabs.org/patch/281934/
drivers/usb/host/xhci-omap.c | 171 +-------------------
drivers/usb/phy/Makefile | 1 +
.../usb/{host/xhci-omap.c => phy/omap_usb_phy.c} | 142 +---------------
include/linux/usb/xhci-omap.h | 6 +
4 files changed, 15 insertions(+), 305 deletions(-)
copy drivers/usb/{host/xhci-omap.c => phy/omap_usb_phy.c} (58%)
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 4f98c77..7292ed8 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -27,161 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct omap_xhci omap;
-struct usb_dpll_params {
- u16 m;
- u8 n;
- u8 freq:3;
- u8 sd;
- u32 mf;
-};
-
-#define NUM_USB_CLKS 6
-
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
- {1250, 5, 4, 20, 0}, /* 12 MHz */
- {3125, 20, 4, 20, 0}, /* 16.8 MHz */
- {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
- {1250, 12, 4, 20, 0}, /* 26 MHz */
- {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
- {1000, 7, 4, 10, 0}, /* 20 MHz */
-};
-
-static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
-{
- u32 val;
-
- writel(SET_PLL_GO, &phy_regs->pll_go);
- do {
- val = readl(&phy_regs->pll_status);
- if (val & PLL_LOCK)
- break;
- } while (1);
-}
-
-static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
-{
- u32 clk_index = get_sys_clk_index();
- u32 val;
-
- val = readl(&phy_regs->pll_config_1);
- val &= ~PLL_REGN_MASK;
- val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
- writel(val, &phy_regs->pll_config_1);
-
- val = readl(&phy_regs->pll_config_2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
- writel(val, &phy_regs->pll_config_2);
-
- val = readl(&phy_regs->pll_config_1);
- val &= ~PLL_REGM_MASK;
- val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
- writel(val, &phy_regs->pll_config_1);
-
- val = readl(&phy_regs->pll_config_4);
- val &= ~PLL_REGM_F_MASK;
- val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
- writel(val, &phy_regs->pll_config_4);
-
- val = readl(&phy_regs->pll_config_3);
- val &= ~PLL_SD_MASK;
- val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
- writel(val, &phy_regs->pll_config_3);
-
- omap_usb_dpll_relock(phy_regs);
-}
-
-static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
-{
- u32 rate = get_sys_clk_freq()/1000000;
- u32 val;
-
- val = readl((*ctrl)->control_phy_power_usb);
- val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
- val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
- val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
-
- writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-static void usb3_phy_power(int on)
-{
- u32 val;
-
- val = readl((*ctrl)->control_phy_power_usb);
- if (on) {
- val &= ~USB3_PWRCTL_CLK_CMD_MASK;
- val |= USB3_PHY_TX_RX_POWERON;
- } else {
- val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
- }
-
- writel(val, (*ctrl)->control_phy_power_usb);
-}
-
-static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
-{
- omap_usb_dpll_lock(phy_regs);
-
- usb3_phy_partial_powerup(phy_regs);
- /*
- * Give enough time for the PHY to partially power-up before
- * powering it up completely. delay value suggested by the HW
- * team.
- */
- mdelay(100);
- usb3_phy_power(1);
-}
-
-static void omap_enable_phy_clocks(struct omap_xhci *omap)
-{
- u32 val;
-
- /* Setting OCP2SCP1 register */
- setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
- OCP2SCP1_CLKCTRL_MODULEMODE_HW);
-
- /* Turn on 32K AON clk */
- setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
- /* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
- writel(0x0, (*prcm)->cm_l3init_clkstctrl);
-
- val = (USBOTGSS_DMADISABLE |
- USBOTGSS_STANDBYMODE_SMRT_WKUP |
- USBOTGSS_IDLEMODE_NOIDLE);
- writel(val, &omap->otg_wrapper->sysconfig);
-
- /* Clear the utmi OTG status */
- val = readl(&omap->otg_wrapper->utmi_otg_status);
- writel(val, &omap->otg_wrapper->utmi_otg_status);
-
- /* Enable interrupts */
- writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
- val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN |
- USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN |
- USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
- USBOTGSS_IRQ_SET_1_OEVT_EN);
- writel(val, &omap->otg_wrapper->irqenable_set_1);
-
- /* Clear the IRQ status */
- val = readl(&omap->otg_wrapper->irqstatus_1);
- writel(val, &omap->otg_wrapper->irqstatus_1);
- val = readl(&omap->otg_wrapper->irqstatus_0);
- writel(val, &omap->otg_wrapper->irqstatus_0);
-
- /* Enable the USB OTG Super speed clocks */
- val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
-
-};
-
inline int __board_usb_init(int index, enum board_usb_init_type init)
{
return 0;
@@ -201,19 +46,7 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(100);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+ omap_reset_usb_phy(dwc3_reg);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
@@ -267,7 +100,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
omap_enable_phy_clocks(omap);
- dwc_usb3_phy_init(omap->usb3_phy);
+ omap_usb3_phy_init(omap->usb3_phy);
ret = dwc3_core_init(omap->dwc3_reg);
if (ret) {
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index f93121a..5beec78 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libusb_phy.o
COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
+COBJS-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/phy/omap_usb_phy.c
similarity index 58%
copy from drivers/usb/host/xhci-omap.c
copy to drivers/usb/phy/omap_usb_phy.c
index 4f98c77..ed727bf 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -1,5 +1,5 @@
/*
- * OMAP USB HOST xHCI Controller
+ * OMAP USB PHY Support
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
@@ -20,12 +20,7 @@
#include <linux/usb/dwc3.h>
#include <linux/usb/xhci-omap.h>
-#include "xhci.h"
-
-/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct omap_xhci omap;
+#include "../host/xhci.h"
struct usb_dpll_params {
u16 m;
@@ -104,7 +99,7 @@ static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
writel(val, (*ctrl)->control_phy_power_usb);
}
-static void usb3_phy_power(int on)
+void usb3_phy_power(int on)
{
u32 val;
@@ -119,7 +114,7 @@ static void usb3_phy_power(int on)
writel(val, (*ctrl)->control_phy_power_usb);
}
-static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
{
omap_usb_dpll_lock(phy_regs);
@@ -133,7 +128,7 @@ static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
usb3_phy_power(1);
}
-static void omap_enable_phy_clocks(struct omap_xhci *omap)
+void omap_enable_phy_clocks(struct omap_xhci *omap)
{
u32 val;
@@ -182,25 +177,8 @@ static void omap_enable_phy_clocks(struct omap_xhci *omap)
};
-inline int __board_usb_init(int index, enum board_usb_init_type init)
-{
- return 0;
-}
-int board_usb_init(int index, enum board_usb_init_type init) \
- __attribute__((weak, alias("__board_usb_init")));
-
-static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
-{
- clrsetbits_le32(&dwc3_reg->g_ctl,
- DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
- DWC3_GCTL_PRTCAPDIR(mode));
-}
-
-static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
{
- /* Before Resetting PHY, put Core in Reset */
- setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
@@ -215,113 +193,5 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
- /* After PHYs are stable we can take Core out of reset state */
- clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
-}
-
-static int dwc3_core_init(struct dwc3 *dwc3_reg)
-{
- u32 reg;
- u32 revision;
- unsigned int dwc3_hwparams1;
-
- revision = readl(&dwc3_reg->g_snpsid);
- /* This should read as U3 followed by revision number */
- if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
- puts("this is not a DesignWare USB3 DRD Core\n");
- return -1;
- }
-
- dwc3_core_soft_reset(dwc3_reg);
-
- dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
-
- reg = readl(&dwc3_reg->g_ctl);
- reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
- reg &= ~DWC3_GCTL_DISSCRAMBLE;
- switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
- case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
- reg &= ~DWC3_GCTL_DSBLCLKGTNG;
- break;
- default:
- debug("No power optimization available\n");
- }
-
- /*
- * WORKAROUND: DWC3 revisions <1.90a have a bug
- * where the device can fail to connect@SuperSpeed
- * and falls back to high-speed mode which causes
- * the device to enter a Connect/Disconnect loop
- */
- if ((revision & DWC3_REVISION_MASK) < 0x190a)
- reg |= DWC3_GCTL_U2RSTECN;
-
- writel(reg, &dwc3_reg->g_ctl);
-
- return 0;
-}
-
-static int omap_xhci_core_init(struct omap_xhci *omap)
-{
- int ret = 0;
-
- omap_enable_phy_clocks(omap);
-
- dwc_usb3_phy_init(omap->usb3_phy);
-
- ret = dwc3_core_init(omap->dwc3_reg);
- if (ret) {
- debug("%s:failed to initialize core\n", __func__);
- return ret;
- }
-
- /* We are hard-coding DWC3 core to Host Mode */
- dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
-
- return ret;
-}
-
-static void omap_xhci_core_exit(struct omap_xhci *omap)
-{
- usb3_phy_power(0);
}
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
- struct omap_xhci *ctx = &omap;
- int ret = 0;
-
- ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
- ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
- ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
- ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
-
- ret = board_usb_init(index, USB_INIT_HOST);
- if (ret != 0) {
- puts("Failed to initialize board for USB\n");
- return ret;
- }
-
- ret = omap_xhci_core_init(ctx);
- if (ret < 0) {
- puts("Failed to initialize xhci\n");
- return ret;
- }
-
- *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
- *hcor = (struct xhci_hcor *)((uint32_t) *hccr
- + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
-
- debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)*hccr, (uint32_t)*hcor,
- (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
-
- return ret;
-}
-
-void xhci_hcd_stop(int index)
-{
- struct omap_xhci *ctx = &omap;
-
- omap_xhci_core_exit(ctx);
-}
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index b557a43..a73c0f9 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -121,4 +121,10 @@ struct omap_xhci {
struct dwc3 *dwc3_reg;
};
+/* USB PHY functions */
+void omap_enable_phy_clocks(struct omap_xhci *omap);
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb3_phy_power(int on);
+
#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 4/6] usb: dra7xx: Add support for dra7xx xhci USB host
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
` (2 preceding siblings ...)
2013-10-11 17:28 ` [U-Boot] [PATCH v2 3/6] usb: omap: Move the usb phy code to the usb/phy directory Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-12 1:13 ` Marek Vasut
2013-10-11 17:28 ` [U-Boot] [PATCH v2 5/6] usb: am437x: Add support for am437x " Dan Murphy
` (2 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.
The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - In omap_enable_usb2_phy2 changed int to u32 - http://patchwork.ozlabs.org/patch/281935/
arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
arch/arm/include/asm/arch-omap5/clock.h | 4 +++
arch/arm/include/asm/omap_common.h | 1 +
board/ti/dra7xx/evm.c | 6 -----
board/ti/dra7xx/mux_data.h | 1 +
drivers/usb/host/xhci-omap.c | 6 ++---
drivers/usb/phy/omap_usb_phy.c | 45 +++++++++++++++++++++++++++++--
include/configs/dra7xx_evm.h | 11 ++++++++
include/linux/usb/xhci-omap.h | 12 ++++++---
9 files changed, 72 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b48c65c..85a65be 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -795,6 +795,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 5cbbc44..8869b50 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -202,6 +202,10 @@
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR 0x12
#define SMPS_REG_ADDR_12_MPU 0x23
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index bea1835..8a395e8 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -144,6 +144,7 @@ struct prcm_regs {
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy_core_clkctrl;
+ u32 cm_coreaon_usb_phy2_core_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9a114e2..9657c75 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -17,12 +17,6 @@
#include "mux_data.h"
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 6965cc5..38de9d5 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -61,5 +61,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
+ {USB2_DRVVBUS, (M0 | IEN | FSC) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index 7292ed8..f6099ac 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -98,9 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;
- omap_enable_phy_clocks(omap);
-
- omap_usb3_phy_init(omap->usb3_phy);
+ omap_enable_phy(omap);
ret = dwc3_core_init(omap->dwc3_reg);
if (ret) {
@@ -116,7 +114,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
static void omap_xhci_core_exit(struct omap_xhci *omap)
{
- usb3_phy_power(0);
+ usb_phy_power(0);
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index ed727bf..f074a88 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -22,6 +22,7 @@
#include "../host/xhci.h"
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
struct usb_dpll_params {
u16 m;
u8 n;
@@ -99,7 +100,7 @@ static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
writel(val, (*ctrl)->control_phy_power_usb);
}
-void usb3_phy_power(int on)
+void usb_phy_power(int on)
{
u32 val;
@@ -128,7 +129,7 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
usb3_phy_power(1);
}
-void omap_enable_phy_clocks(struct omap_xhci *omap)
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
{
u32 val;
@@ -176,6 +177,35 @@ void omap_enable_phy_clocks(struct omap_xhci *omap)
setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
};
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+ u32 reg, val;
+
+ val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+ writel(val, (*ctrl)->control_srcomp_north_side);
+
+ setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+ USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+ OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+ /* This is an undocumented Reserved register */
+ reg = 0x4a0086c0;
+ val = readl(reg);
+ val |= 0x100;
+ setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+ return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
{
@@ -195,3 +225,14 @@ void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
}
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+ omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+ omap_enable_usb3_phy(omap);
+ omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 51e0e80..b56ea1c 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -67,4 +67,15 @@
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index a73c0f9..c3fcc03 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -10,9 +10,16 @@
#ifndef _ASM_ARCH_XHCI_OMAP_H_
#define _ASM_ARCH_XHCI_OMAP_H_
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#else
+/* Default to the OMAP5 XHCI defines */
#define OMAP_XHCI_BASE 0x4a030000
#define OMAP_OCP1_SCP_BASE 0x4a084c00
#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
/* Phy register MACRO definitions */
#define PLL_REGM_MASK 0x001FFE00
@@ -122,9 +129,8 @@ struct omap_xhci {
};
/* USB PHY functions */
-void omap_enable_phy_clocks(struct omap_xhci *omap);
-void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs);
+void omap_enable_phy(struct omap_xhci *omap);
void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
-void usb3_phy_power(int on);
+void usb_phy_power(int on);
#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 5/6] usb: am437x: Add support for am437x xhci USB host
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
` (3 preceding siblings ...)
2013-10-11 17:28 ` [U-Boot] [PATCH v2 4/6] usb: dra7xx: Add support for dra7xx xhci USB host Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-11 17:28 ` [U-Boot] [PATCH v2 6/6] ARM: omap5-evm: Move MAC creation to misc_init Dan Murphy
2013-10-12 1:15 ` [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Marek Vasut
6 siblings, 0 replies; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Add the support for the am437x xhci usb host.
The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - Changed int->const u32 for usb_otg_ss_clk_val - http://patchwork.ozlabs.org/patch/281932/
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 10 +++++++++
drivers/usb/phy/omap_usb_phy.c | 23 ++++++++++++++++++++
include/configs/am43xx_evm.h | 11 ++++++++++
include/linux/usb/xhci-omap.h | 4 ++++
4 files changed, 48 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 303c594..3b665e6 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -51,4 +51,14 @@
/* RTC base address */
#define RTC_BASE 0x44E3E000
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN (1 << 2)
+
#endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f074a88..af46db2 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -207,6 +207,25 @@ void usb_phy_power(int on)
}
#endif /* CONFIG_OMAP_USB2PHY2_HOST */
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
+{
+ const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
+ USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+
+ writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
+ writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
+
+ writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
+ writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
+}
+
+void usb_phy_power(int on)
+{
+ return;
+}
+#endif /* CONFIG_AM437X_USB2PHY2_HOST */
+
void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
@@ -231,6 +250,10 @@ void omap_enable_phy(struct omap_xhci *omap)
omap_enable_usb2_phy2(omap);
#endif
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+ am437x_enable_usb2_phy2(omap);
+#endif
+
#ifdef CONFIG_OMAP_USB3PHY1_HOST
omap_enable_usb3_phy(omap);
omap_usb3_phy_init(omap->usb3_phy);
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5c802a1..64c4811 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -24,6 +24,7 @@
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
@@ -132,4 +133,14 @@
/* Unsupported features */
#undef CONFIG_USE_IRQ
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
#endif /* __CONFIG_AM43XX_EVM_H */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
index c3fcc03..82630ad 100644
--- a/include/linux/usb/xhci-omap.h
+++ b/include/linux/usb/xhci-omap.h
@@ -14,6 +14,10 @@
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
#else
/* Default to the OMAP5 XHCI defines */
#define OMAP_XHCI_BASE 0x4a030000
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 6/6] ARM: omap5-evm: Move MAC creation to misc_init
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
` (4 preceding siblings ...)
2013-10-11 17:28 ` [U-Boot] [PATCH v2 5/6] usb: am437x: Add support for am437x " Dan Murphy
@ 2013-10-11 17:28 ` Dan Murphy
2013-10-12 1:15 ` [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Marek Vasut
6 siblings, 0 replies; 9+ messages in thread
From: Dan Murphy @ 2013-10-11 17:28 UTC (permalink / raw)
To: u-boot
Move the MAC creation from the USB init to an function
that is called on every boot. This will then populate the
usbethaddr mac that kernel driver can pick up from the
device tree blob.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v2 - No code changes - http://patchwork.ozlabs.org/patch/281930/
board/ti/omap5_uevm/evm.c | 39 ++++++++++++++++++++-------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 6a01200..0044c22 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -110,10 +110,30 @@ static void enable_host_clocks(void)
*/
int misc_init_r(void)
{
+ int reg;
+ uint8_t device_mac[6];
+
#ifdef CONFIG_PALMAS_POWER
palmas_init_settings();
#endif
+ if (!getenv("usbethaddr")) {
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = readl(reg + 0x10) & 0xff;
+ device_mac[2] = readl(reg + 0xC) & 0xff;
+ device_mac[3] = readl(reg + 0x8) & 0xff;
+ device_mac[4] = readl(reg) & 0xff;
+ device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+
return 0;
}
@@ -162,28 +182,9 @@ static struct omap_usbhs_board_data usbhs_bdata = {
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
- int reg;
- uint8_t device_mac[6];
enable_host_clocks();
- if (!getenv("usbethaddr")) {
- reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
- /*
- * create a fake MAC address from the processor ID code.
- * first byte is 0x02 to signify locally administered.
- */
- device_mac[0] = 0x02;
- device_mac[1] = readl(reg + 0x10) & 0xff;
- device_mac[2] = readl(reg + 0xC) & 0xff;
- device_mac[3] = readl(reg + 0x8) & 0xff;
- device_mac[4] = readl(reg) & 0xff;
- device_mac[5] = (readl(reg) >> 8) & 0xff;
-
- eth_setenv_enetaddr("usbethaddr", device_mac);
- }
-
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0) {
puts("Failed to initialize ehci\n");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset
2013-10-11 17:28 [U-Boot] [PATCH v2 0/6] TI xHCI Updated patchset Dan Murphy
` (5 preceding siblings ...)
2013-10-11 17:28 ` [U-Boot] [PATCH v2 6/6] ARM: omap5-evm: Move MAC creation to misc_init Dan Murphy
@ 2013-10-12 1:15 ` Marek Vasut
6 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2013-10-12 1:15 UTC (permalink / raw)
To: u-boot
Dear Dan Murphy,
> V2 patchset for TI SoC's that support xHCI controllers
>
> Dan Murphy (6):
> usb: omap: Move the xhci-omap header file to common location
> usb: omap5: Update the board_usb_init api
> usb: omap: Move the usb phy code to the usb/phy directory
> usb: dra7xx: Add support for dra7xx xhci USB host
> usb: am437x: Add support for am437x xhci USB host
> ARM: omap5-evm: Move MAC creation to misc_init
>
> arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
> arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 10 ++
> arch/arm/include/asm/arch-omap5/clock.h | 4 +
> arch/arm/include/asm/omap_common.h | 1 +
> board/ti/dra7xx/evm.c | 6 -
> board/ti/dra7xx/mux_data.h | 1 +
> board/ti/omap5_uevm/evm.c | 41 ++---
> drivers/usb/host/xhci-omap.c | 184
> +------------------ drivers/usb/phy/Makefile |
> 1 +
> .../usb/{host/xhci-omap.c => phy/omap_usb_phy.c} | 187
> +++++++------------- include/configs/am43xx_evm.h |
> 11 ++
> include/configs/dra7xx_evm.h | 11 ++
> .../arch-omap5 => include/linux/usb}/xhci-omap.h | 16 ++
> 13 files changed, 146 insertions(+), 328 deletions(-)
> copy drivers/usb/{host/xhci-omap.c => phy/omap_usb_phy.c} (58%)
> rename {arch/arm/include/asm/arch-omap5 => include/linux/usb}/xhci-omap.h
> (86%)
Applied all and pushed to -next.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 9+ messages in thread