[U-Boot] [PATCH v2 05/18] pcnet: enable the NOUFLO feature

[Marek Vasut <marex@denx.de>]

Dear Paul Burton,

> On relatively slow boards (such as the MIPS Malta with an FPGA core
> card) it can be extremely common for transmits to underflow - to the
> point where it appears they simply do not work at all. Setting the
> NOUFLO bit causes the ethernet controller to not begin transmission on
> the wire until a transmit start point is reached. Setting that transmit
> start point to the full packet will cause the controller to only
> transmit the packet once it has buffered it entirely thus preventing any
> transmit underflows from occuring and allowing the controller to
> function on slower boards.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
> Changes in v2:
>   - rebase atop master
> ---
>  drivers/net/pcnet.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
> index 7b87660..5b248be 100644
> --- a/drivers/net/pcnet.c
> +++ b/drivers/net/pcnet.c
> @@ -312,6 +312,21 @@ static int pcnet_init(struct eth_device *dev, bd_t
> *bis) pcnet_write_bcr(dev, 32, val);
> 
>  	/*
> +	 * Enable NOUFLO on supported controllers, with the transmit
> +	 * start point set to the full packet. This will cause entire
> +	 * packets to be buffered by the ethernet controller before
> +	 * transmission, eliminating underflows which are common on
> +	 * slower devices. Controllers which do not support NOUFLO will
> +	 * simply be left with a larger transmit FIFO threshold.
> +	 */
> +	val = pcnet_read_bcr(dev, 18);
> +	val |= 1 << 11;
> +	pcnet_write_bcr(dev, 18, val);
> +	val = pcnet_read_csr(dev, 80);
> +	val |= 0x3 << 10;
> +	pcnet_write_csr(dev, 80, val);

Would be nice to fix this so we don't have so many magic numbers there.

Best regards,
Marek Vasut