[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[Masahiro Yamada]

The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.

This commit moves ".algin 5" directive to the correct place.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Przywara <andre.przywara@linaro.org>
---

BTW, I noticed the legacy license block is used in this file.

Because arch/arm/cpu/armv7/nonsec_virt.S is a newly added file,
SPDX License Identifier should have been used...


 arch/arm/cpu/armv7/nonsec_virt.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 358348f..ee36760 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -30,6 +30,7 @@
 .arch_extension sec
 .arch_extension virt
 
+	.align	5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
 	.word 0	/* reset */
@@ -48,7 +49,6 @@ _monitor_vectors:
  * to non-secure state.
  * We use only r0 and r1 here, due to constraints in the caller.
  */
-	.align	5
 _secure_monitor:
 	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
 	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
-- 
1.8.1.2

[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[Andre Przywara]

On 10/07/2013 04:46 AM, Masahiro Yamada wrote:
> The lower 5 bit of MVBAR is UNK/SBZP.
> So, Monitor Vector Base Address must be 32-byte aligned.
> On the other hand, the secure monitor handler does not need
> 32-byte alignment.
>
> This commit moves ".algin 5" directive to the correct place.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Andre Przywara <andre.przywara@linaro.org>

Acked-by: Andre Przywara <andre.przywara@linaro.org>

Masahiro,

good catch, thanks for spotting!

I am wondering whether we need the alignment statements in the various 
start.S files also, because the lower 5 bits are reserved for VBAR too.

>
> BTW, I noticed the legacy license block is used in this file.
>
> Because arch/arm/cpu/armv7/nonsec_virt.S is a newly added file,
> SPDX License Identifier should have been used...

Right, will send a patch to address this.

Thanks,
Andre.

>
>   arch/arm/cpu/armv7/nonsec_virt.S | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
> index 358348f..ee36760 100644
> --- a/arch/arm/cpu/armv7/nonsec_virt.S
> +++ b/arch/arm/cpu/armv7/nonsec_virt.S
> @@ -30,6 +30,7 @@
>   .arch_extension sec
>   .arch_extension virt
>
> +	.align	5
>   /* the vector table for secure state and HYP mode */
>   _monitor_vectors:
>   	.word 0	/* reset */
> @@ -48,7 +49,6 @@ _monitor_vectors:
>    * to non-secure state.
>    * We use only r0 and r1 here, due to constraints in the caller.
>    */
> -	.align	5
>   _secure_monitor:
>   	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
>   	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
>

[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[Masahiro Yamada]

Hello Andre,


> Masahiro,
> 
> good catch, thanks for spotting!
> 
> I am wondering whether we need the alignment statements in the various 
> start.S files also, because the lower 5 bits are reserved for VBAR too.

I think start.o is always located at the begnning of .text section.
So, we do not need explicitely align.


Best Regards
Masahiro Yamada

[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[Masahiro Yamada]

Hello Albert.

> The lower 5 bit of MVBAR is UNK/SBZP.
> So, Monitor Vector Base Address must be 32-byte aligned.
> On the other hand, the secure monitor handler does not need
> 32-byte alignment.
> 
> This commit moves ".algin 5" directive to the correct place.
> 
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Andre Przywara <andre.przywara@linaro.org>


Could you apply this patch, please?

Best Regards
Masahiro Yamada

[U-Boot] [PATCH] ARM: align MVBAR on 32 byte boundary

[Albert ARIBAUD]

Hi Masahiro,

On Mon,  7 Oct 2013 11:46:56 +0900, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:

> The lower 5 bit of MVBAR is UNK/SBZP.
> So, Monitor Vector Base Address must be 32-byte aligned.
> On the other hand, the secure monitor handler does not need
> 32-byte alignment.
> 
> This commit moves ".algin 5" directive to the correct place.
> 
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Andre Przywara <andre.przywara@linaro.org>
> ---
> 
> BTW, I noticed the legacy license block is used in this file.
> 
> Because arch/arm/cpu/armv7/nonsec_virt.S is a newly added file,
> SPDX License Identifier should have been used...
> 
> 
>  arch/arm/cpu/armv7/nonsec_virt.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
> index 358348f..ee36760 100644
> --- a/arch/arm/cpu/armv7/nonsec_virt.S
> +++ b/arch/arm/cpu/armv7/nonsec_virt.S
> @@ -30,6 +30,7 @@
>  .arch_extension sec
>  .arch_extension virt
>  
> +	.align	5
>  /* the vector table for secure state and HYP mode */
>  _monitor_vectors:
>  	.word 0	/* reset */
> @@ -48,7 +49,6 @@ _monitor_vectors:
>   * to non-secure state.
>   * We use only r0 and r1 here, due to constraints in the caller.
>   */
> -	.align	5
>  _secure_monitor:
>  	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
>  	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.