From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Tue, 10 Dec 2013 13:06:37 +0100
Subject: [U-Boot] [PATCH] serial: zynq: Remove unused #defines
In-Reply-To: <8f583fe620e6a1606568f05a5d31486bb50e4caf.1383144568.git.michal.simek@xilinx.com>
References: <8f583fe620e6a1606568f05a5d31486bb50e4caf.1383144568.git.michal.simek@xilinx.com>
Message-ID: <20131210130637.00779cd1@lilith>
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To: u-boot@lists.denx.de

Hi Michal,

On Wed, 30 Oct 2013 15:49:32 +0100, Michal Simek
<michal.simek@xilinx.com> wrote:

> From: Soren Brinkmann <soren.brinkmann@xilinx.com>
> 
> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>  drivers/serial/serial_zynq.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> index 050b9c0..ff28f3c 100644
> --- a/drivers/serial/serial_zynq.c
> +++ b/drivers/serial/serial_zynq.c
> @@ -21,10 +21,6 @@
> 
>  #define ZYNQ_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
> 
> -/* Some clock/baud constants */
> -#define ZYNQ_UART_BDIV	15 /* Default/reset BDIV value */
> -#define ZYNQ_UART_BASECLK	3125000L /* master / (bdiv + 1) */
> -
>  struct uart_zynq {
>  	u32 control; /* Control Register [8:0] */
>  	u32 mode; /* Mode Register [10:0] */
> --
> 1.8.2.3
> 

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.