From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sat, 14 Dec 2013 13:29:25 +0100 Subject: [U-Boot] [PATCH 1/4] ARM: pxa: prevent PXA270 occasional reboot freezes In-Reply-To: <1386999720-23460-2-git-send-email-ynvich@gmail.com> References: <1386999720-23460-1-git-send-email-ynvich@gmail.com> <1386999720-23460-2-git-send-email-ynvich@gmail.com> Message-ID: <201312141329.25973.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Saturday, December 14, 2013 at 06:41:57 AM, Sergei Ianovich wrote: > Erratum 71 of PXA270M Processor Family Specification Update > (April 19, 2010) explains that watchdog reset time is just > 8us insead of 10ms in EMTS. > > If SDRAM is not reset, it causes memory bus congestion and > the device hangs. > > We put SDRAM in selfresh mode before watchdog reset, removing > potential freezes. > > Signed-off-by: Sergei Ianovich > --- > arch/arm/cpu/pxa/pxa2xx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c > index c9a7d45..93ca2f0 100644 > --- a/arch/arm/cpu/pxa/pxa2xx.c > +++ b/arch/arm/cpu/pxa/pxa2xx.c > @@ -281,5 +281,5 @@ void reset_cpu(ulong ignored) > writel(tmp, OSMR3); > > for (;;) > - ; > + writel(MDREFR_SLFRSH, MDREFR); Do you need to write this register in an endless loop ? > } Best regards, Marek Vasut