* [U-Boot] [PATCH v16 00/10] arm64 patch
@ 2013-12-14 3:47 fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support fenghua at phytium.com.cn
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Changes for v16:
- make the patches work with latest recently u-boot.
add rela relocation type to OBJCFLAGS definition
at arm/config.mk.
Changes for v15:
- modify boot process, u-boot will run at the highest
exception level until it prepare jump to OS.
- Fix a few bugs in cache.S.These bug is reported by
York Sun <yorksun@freescale.com> and Scott Wood
<scottwood@freescale.com>.
- when booting, slaves will wait on WFI, master wakeup
slaves by SGI interrupt.
- add generic_timer.c to utilize the newest timer architecture.
- add gic.S to support gic initialization and interrupt
operations, currently only support GICv2.
Changes for v14:
- Merge rela relocation patches from Scott Wood
<scottwood@freescale.com>.
- Remove all CONFIG_NEED_MANUAL_RELOC and other fixups
due to manual relocation. With rela relocation patches
them are not needed.
- Fix the bug of MEMORY_ATTRIBUTES definition due to
assembler. That need put brackets around (MT_NORMAL*8).
Otherwise the result is wrong.This bug is reported by
York Sun <yorksun@freescale.com>.
- -msoft-float is not supported by aarch64-gcc,
make a test though $(call cc-option,-msoft-float).
- Adjust the virtual address space to 42 bits.
- Filter armv8 boards from LIST_arm in MAKEALL.
- remove gpio.h in asm/arch-armv8/ and move mmu.h to
asm/armv8/ directory.
- remove vexpress64.dts from this patch, it could be
accessed from linux kernel.
Changes for v13:
- fix the bug of board_r.c and arm/lib/board.c due to
CONFIG_NEED_MANUAL_RELOC. adjust initr_serial() in board_r.c
to the first entry of init_sequence_r[] and relocate
serial_initialize() in arm/lib/board.c, routines of serial_device
should be relocated firstly by serial_initialize(), so that printf
access the correct puts function, otherwise uninitialized
serial_current will be selected as the output device.
- fix the bug of dcache_enable(). after mmu_setup the sctrl
register value should be fetched again because it has been
modifed by mmu_seup() function. This bug is reported by York Sun
<yorksun@freescale.com>.
- add macro branch_if_slave to macro.h, it choose processor
with all zero affinity value as the master and is used in start.S.
Changes for v12:
- custom the patches to new format boards.cfg.
Changes for v11:
- Replace CONFIG_ARMV8 with CONFIG_ARM64. Currently,
it's hard to distinguish what is armv8 specific and
what is aarch64 specific, so we use CONFIG_ARM64
only, no CONFIG_ARMV8 used.
- rename README.armv8 with README.arm64 and make some modification.
Changes for v10:
- add weak definition to include/linux/linkage.h and make
setup_el2/setup_el3/lowlevel_init weak routines,
so them can be easily overridden by processor specific code.
- modify s-o-f of 0002-board-support-of-vexpress_aemv8a which
use wrong mail address of Bhupesh Sharma.
Changes for v9:
- add Signed-off-by information to patch "board support of
vexpress_aemv8a" which SMC91111 support is integrated
from Sharma Bhupesh's patch.
- adjust pt_regs struct and add exception state
preservation in exception.S.
Changes for v8:
- Integrate SMC91111 patch of sharma bhupesh.
- remove v8_outer_cache* which is not need currently.
- Change license tag.
- Mov crt0.S/relocate.S/interrupts.c to arm/lib and
rename them with _64 suffix.
- Make el3/el2 initializing process of start.S as
two separate routines. It could be easier to be
replaced with processor specific codes.
- Remove exception stack save and restore routine,
it is unnecessary now.
- simplify __weak function declaration.
Changes for v7:
- Check the patches with checkpatch.pl and get rid of
almost all warnings. There are a few warnings still,
but I think it should be that.
- change printf format in cmd_pxe.c, use %zd indtead
of %ld to format size_t type variable.
- add macro PGTABLE_SIZE to identify tlb table size.
Changes for v6:
- Make modification to inappropriate licensed file
and bugs according to ScottWood's advice.
Thanks Scott for his checking to these patches.
- Enable u-boot's running at EL1.
- Get rid of compiling warnings originated from cmd_pxe.c.
Changes for v5:
- fix the generic board_f.c, remove zero_global_data
from init_sequence_f array and move it to board_init_f()
function with CONFIG_X86 switch. The previous fixup is
inaccurate.
- Replace __ARMEB__ with __AARCH64EB__ in byteorder.h
and unaligned.h, gcc for aarch64 use __AARCH64EB__ and
__AARCH64EL__ to identify endian.
- Some modification to README.armv8
Changes for v4:
- merge arm64 to arm architecture.
David Feng (10):
fdt_support: 64bit initrd start address support
cmd_pxe: remove compiling warnings
add weak entry definition
arm64: Add tool to statically apply RELA relocations
arm64: Turn u-boot.bin back into an ELF file after relocate-rela
arm64: Make checkarmreloc accept arm64 relocations
arm64: core support
arm64: generic board support
arm64: board support of vexpress_aemv8a
arm64: MAKEALL, filter armv8 boards from LIST_arm
MAKEALL | 12 +-
Makefile | 39 +++++-
arch/arm/config.mk | 7 +-
arch/arm/cpu/armv8/Makefile | 17 +++
arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++
arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++
arch/arm/cpu/armv8/config.mk | 15 +++
arch/arm/cpu/armv8/cpu.c | 43 ++++++
arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++
arch/arm/cpu/armv8/generic_timer.c | 31 +++++
arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++
arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++
arch/arm/cpu/armv8/tlb.S | 34 +++++
arch/arm/cpu/armv8/transition.S | 83 ++++++++++++
arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++
arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++
arch/arm/include/asm/byteorder.h | 12 ++
arch/arm/include/asm/cache.h | 5 +
arch/arm/include/asm/config.h | 6 +
arch/arm/include/asm/gic.h | 49 ++++++-
arch/arm/include/asm/global_data.h | 6 +-
arch/arm/include/asm/io.h | 15 ++-
arch/arm/include/asm/macro.h | 53 ++++++++
arch/arm/include/asm/posix_types.h | 10 ++
arch/arm/include/asm/proc-armv/ptrace.h | 21 +++
arch/arm/include/asm/proc-armv/system.h | 59 ++++++++-
arch/arm/include/asm/system.h | 84 ++++++++++++
arch/arm/include/asm/types.h | 4 +
arch/arm/include/asm/u-boot.h | 4 +
arch/arm/include/asm/unaligned.h | 2 +-
arch/arm/lib/Makefile | 20 ++-
arch/arm/lib/board.c | 7 +-
arch/arm/lib/bootm.c | 24 ++++
arch/arm/lib/crt0_64.S | 113 ++++++++++++++++
arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++
arch/arm/lib/relocate_64.S | 58 ++++++++
board/armltd/vexpress64/Makefile | 8 ++
board/armltd/vexpress64/vexpress64.c | 56 ++++++++
boards.cfg | 1 +
common/board_f.c | 20 ++-
common/cmd_pxe.c | 4 +-
common/fdt_support.c | 66 +++++-----
common/image.c | 1 +
doc/README.arm64 | 46 +++++++
examples/standalone/stubs.c | 15 +++
include/configs/vexpress_aemv8a.h | 189 ++++++++++++++++++++++++++
include/image.h | 1 +
include/linux/linkage.h | 4 +
tools/Makefile | 6 +
tools/relocate-rela.c | 189 ++++++++++++++++++++++++++
50 files changed, 2429 insertions(+), 68 deletions(-)
create mode 100644 arch/arm/cpu/armv8/Makefile
create mode 100644 arch/arm/cpu/armv8/cache.S
create mode 100644 arch/arm/cpu/armv8/cache_v8.c
create mode 100644 arch/arm/cpu/armv8/config.mk
create mode 100644 arch/arm/cpu/armv8/cpu.c
create mode 100644 arch/arm/cpu/armv8/exceptions.S
create mode 100644 arch/arm/cpu/armv8/generic_timer.c
create mode 100644 arch/arm/cpu/armv8/gic.S
create mode 100644 arch/arm/cpu/armv8/start.S
create mode 100644 arch/arm/cpu/armv8/tlb.S
create mode 100644 arch/arm/cpu/armv8/transition.S
create mode 100644 arch/arm/cpu/armv8/u-boot.lds
create mode 100644 arch/arm/include/asm/armv8/mmu.h
create mode 100644 arch/arm/lib/crt0_64.S
create mode 100644 arch/arm/lib/interrupts_64.c
create mode 100644 arch/arm/lib/relocate_64.S
create mode 100644 board/armltd/vexpress64/Makefile
create mode 100644 board/armltd/vexpress64/vexpress64.c
create mode 100644 doc/README.arm64
create mode 100644 include/configs/vexpress_aemv8a.h
create mode 100644 tools/relocate-rela.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support
2013-12-14 3:47 [U-Boot] [PATCH v16 00/10] arm64 patch fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings fenghua at phytium.com.cn
2014-01-09 16:01 ` [U-Boot] [PATCH v16 00/10] arm64 patch Albert ARIBAUD
2014-01-10 9:17 ` Albert ARIBAUD
2 siblings, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
common/fdt_support.c | 66 ++++++++++++++++++++++++++------------------------
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 1f0d8f5..a3f7442 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -21,6 +21,34 @@
*/
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get cells len in bytes
+ * if #NNNN-cells property is 2 then len is 8
+ * otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+ const fdt32_t *cell;
+
+ cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ if (cell && fdt32_to_cpu(*cell) == 2)
+ return 8;
+
+ return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+ int shift = (size - 1) * 8;
+ while (size-- > 0) {
+ *addr++ = (val >> shift) & 0xff;
+ shift -= 8;
+ }
+}
+
/**
* fdt_getprop_u32_default - Find a node and return it's property or a default
*
@@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
- int nodeoffset;
+ int nodeoffset, addr_cell_len;
int err, j, total;
- fdt32_t tmp;
+ fdt64_t tmp;
const char *path;
uint64_t addr, size;
@@ -170,9 +198,11 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
return err;
}
+ addr_cell_len = get_cells_len(fdt, "#address-cells");
+
path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
if ((path == NULL) || force) {
- tmp = cpu_to_fdt32(initrd_start);
+ write_cell((u8 *)&tmp, initrd_start, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0) {
@@ -181,7 +211,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
fdt_strerror(err));
return err;
}
- tmp = cpu_to_fdt32(initrd_end);
+ write_cell((u8 *)&tmp, initrd_end, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0) {
@@ -343,34 +373,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
-/*
- * Get cells len in bytes
- * if #NNNN-cells property is 2 then len is 8
- * otherwise len is 4
- */
-static int get_cells_len(void *blob, char *nr_cells_name)
-{
- const fdt32_t *cell;
-
- cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
- if (cell && fdt32_to_cpu(*cell) == 2)
- return 8;
-
- return 4;
-}
-
-/*
- * Write a 4 or 8 byte big endian cell
- */
-static void write_cell(u8 *addr, u64 val, int size)
-{
- int shift = (size - 1) * 8;
- while (size-- > 0) {
- *addr++ = (val >> shift) & 0xff;
- shift -= 8;
- }
-}
-
#ifdef CONFIG_NR_DRAM_BANKS
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings
2013-12-14 3:47 ` [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 03/10] add weak entry definition fenghua at phytium.com.cn
2013-12-14 5:05 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings Jagan Teki
0 siblings, 2 replies; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
common/cmd_pxe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
index db6b156..c27ec35 100644
--- a/common/cmd_pxe.c
+++ b/common/cmd_pxe.c
@@ -59,7 +59,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len)
uchar ethaddr[6];
if (outbuf_len < 21) {
- printf("outbuf is too small (%d < 21)\n", outbuf_len);
+ printf("outbuf is too small (%zd < 21)\n", outbuf_len);
return -EINVAL;
}
@@ -103,7 +103,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
path_len = (last_slash - bootfile) + 1;
if (bootfile_path_size < path_len) {
- printf("bootfile_path too small. (%d < %d)\n",
+ printf("bootfile_path too small. (%zd < %zd)\n",
bootfile_path_size, path_len);
return -1;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 03/10] add weak entry definition
2013-12-14 3:47 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations fenghua at phytium.com.cn
2013-12-14 5:05 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings Jagan Teki
1 sibling, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
include/linux/linkage.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 39c712e..7435fcd 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -48,6 +48,10 @@
.globl SYMBOL_NAME(name); \
LENTRY(name)
+#define WEAK(name) \
+ .weak SYMBOL_NAME(name); \
+ LENTRY(name)
+
#ifndef END
#define END(name) \
.size name, .-name
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations
2013-12-14 3:47 ` [U-Boot] [PATCH v16 03/10] add weak entry definition fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 05/10] arm64: Turn u-boot.bin back into an ELF file after relocate-rela fenghua at phytium.com.cn
2013-12-14 5:09 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations Jagan Teki
0 siblings, 2 replies; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: Scott Wood <scottwood@freescale.com>
ARM64 uses the newer RELA-style relocations rather than the older REL.
RELA relocations have an addend in the relocation struct, rather than
expecting the loader to read a value from the location to be updated.
While this is beneficial for ordinary program loading, it's problematic
for U-Boot because the location to be updated starts out with zero,
rather than a pre-relocation value. Since we need to be able to run C
code before relocation, we need a tool to apply the relocations at
build time.
In theory this tool is applicable to other newer architectures (mainly
64-bit), but currently the only relocations it supports are for arm64,
and it assumes a 64-bit little-endian target. If the latter limitation
is ever to be changed, we'll need a way to tell the tool what format
the image is in. Eventually this may be replaced by a tool that uses
libelf or similar and operates directly on the ELF file. I've written
some code for such an approach but libelf does not make it easy to poke
addresses by memory address (rather than by section), and I was
hesitant to write code to manually parse the program headers and do the
update outside of libelf (or to iterate over sections) -- especially
since it wouldn't get test coverage on things like binaries with
multiple PT_LOAD segments. This should be good enough for now to let
the manual relocation stuff be removed from the arm64 patches.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
Makefile | 12 ++++
tools/Makefile | 6 ++
tools/relocate-rela.c | 189 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 tools/relocate-rela.c
diff --git a/Makefile b/Makefile
index 7310c4e..4a8e8c5 100644
--- a/Makefile
+++ b/Makefile
@@ -334,6 +334,17 @@ else
BOARD_SIZE_CHECK =
endif
+# Statically apply RELA-style relocations (currently arm64 only)
+ifneq ($(CONFIG_STATIC_RELA),)
+# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
+DO_STATIC_RELA = \
+ start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \
+ end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \
+ $(obj)tools/relocate-rela $(2) $(3) $$start $$end
+else
+DO_STATIC_RELA =
+endif
+
# Always append ALL so that arch config.mk's can add custom ones
ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
@@ -376,6 +387,7 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
$(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr: $(obj)u-boot
diff --git a/tools/Makefile b/tools/Makefile
index 14d94e3..6d40398 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -59,6 +59,7 @@ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
BIN_FILES-y += proftool(SFX)
+BIN_FILES-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
# Source files which exist outside the tools directory
EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
@@ -84,6 +85,7 @@ NOPED_OBJ_FILES-y += os_support.o
NOPED_OBJ_FILES-y += pblimage.o
NOPED_OBJ_FILES-y += proftool.o
NOPED_OBJ_FILES-y += ublimage.o
+NOPED_OBJ_FILES-y += relocate-rela.o
OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
@@ -250,6 +252,10 @@ $(obj)kwboot$(SFX): $(obj)kwboot.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
$(HOSTSTRIP) $@
+$(obj)relocate-rela$(SFX): $(obj)relocate-rela.o
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
+
# Some of the tool objects need to be accessed from outside the tools directory
$(obj)%.o: $(SRCTREE)/common/%.c
$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
new file mode 100644
index 0000000..93b4c39
--- /dev/null
+++ b/tools/relocate-rela.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
+ *
+ * 64-bit and little-endian target only until we need to support a different
+ * arch that needs this.
+ */
+
+#include <elf.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifndef R_AARCH64_RELATIVE
+#define R_AARCH64_RELATIVE 1027
+#endif
+
+static const bool debug_en;
+
+static void debug(const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ if (debug_en)
+ vprintf(fmt, args);
+}
+
+static bool supported_rela(Elf64_Rela *rela)
+{
+ uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */
+ uint32_t type = rela->r_info & mask;
+
+ switch (type) {
+#ifdef R_AARCH64_RELATIVE
+ case R_AARCH64_RELATIVE:
+ return true;
+#endif
+ default:
+ fprintf(stderr, "warning: unsupported relocation type %"
+ PRIu32 " at %" PRIx64 "\n",
+ type, rela->r_offset);
+
+ return false;
+ }
+}
+
+static inline uint64_t swap64(uint64_t val)
+{
+ return ((val >> 56) & 0x00000000000000ffULL) |
+ ((val >> 40) & 0x000000000000ff00ULL) |
+ ((val >> 24) & 0x0000000000ff0000ULL) |
+ ((val >> 8) & 0x00000000ff000000ULL) |
+ ((val << 8) & 0x000000ff00000000ULL) |
+ ((val << 24) & 0x0000ff0000000000ULL) |
+ ((val << 40) & 0x00ff000000000000ULL) |
+ ((val << 56) & 0xff00000000000000ULL);
+}
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+static inline uint64_t be64(uint64_t val)
+{
+ return swap64(val);
+}
+
+static inline uint64_t le64(uint64_t val)
+{
+ return val;
+}
+#else
+static inline uint64_t le64(uint64_t val)
+{
+ return swap64(val);
+}
+
+static inline uint64_t be64(uint64_t val)
+{
+ return val;
+}
+#endif
+
+static bool read_num(const char *str, uint64_t *num)
+{
+ char *endptr;
+ *num = strtoull(str, &endptr, 16);
+ return str[0] && !endptr[0];
+}
+
+int main(int argc, char **argv)
+{
+ FILE *f;
+ int i, num;
+ uint64_t rela_start, rela_end, text_base;
+
+ if (argc != 5) {
+ fprintf(stderr, "Statically apply ELF rela relocations\n");
+ fprintf(stderr, "Usage: %s <bin file> <text base> " \
+ "<rela start> <rela end>\n", argv[0]);
+ fprintf(stderr, "All numbers in hex.\n");
+ return 1;
+ }
+
+ f = fopen(argv[1], "r+b");
+ if (!f) {
+ fprintf(stderr, "%s: Cannot open %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+ return 2;
+ }
+
+ if (!read_num(argv[2], &text_base) ||
+ !read_num(argv[3], &rela_start) ||
+ !read_num(argv[4], &rela_end)) {
+ fprintf(stderr, "%s: bad number\n", argv[0]);
+ return 3;
+ }
+
+ if (rela_start > rela_end || rela_start < text_base ||
+ (rela_end - rela_start) % 24) {
+ fprintf(stderr, "%s: bad rela bounds\n", argv[0]);
+ return 3;
+ }
+
+ rela_start -= text_base;
+ rela_end -= text_base;
+
+ num = (rela_end - rela_start) / sizeof(Elf64_Rela);
+
+ for (i = 0; i < num; i++) {
+ Elf64_Rela rela, swrela;
+ uint64_t pos = rela_start + sizeof(Elf64_Rela) * i;
+ uint64_t addr;
+
+ if (fseek(f, pos, SEEK_SET) < 0) {
+ fprintf(stderr, "%s: %s: seek to %" PRIx64
+ " failed: %s\n",
+ argv[0], argv[1], pos, strerror(errno));
+ }
+
+ if (fread(&rela, sizeof(rela), 1, f) != 1) {
+ fprintf(stderr, "%s: %s: read rela failed at %"
+ PRIx64 "\n",
+ argv[0], argv[1], pos);
+ return 4;
+ }
+
+ swrela.r_offset = le64(rela.r_offset);
+ swrela.r_info = le64(rela.r_info);
+ swrela.r_addend = le64(rela.r_addend);
+
+ if (!supported_rela(&swrela))
+ continue;
+
+ debug("Rela %" PRIx64 " %" PRIu64 " %" PRIx64 "\n",
+ swrela.r_offset, swrela.r_info, swrela.r_addend);
+
+ if (swrela.r_offset < text_base) {
+ fprintf(stderr, "%s: %s: bad rela at %" PRIx64 "\n",
+ argv[0], argv[1], pos);
+ return 4;
+ }
+
+ addr = swrela.r_offset - text_base;
+
+ if (fseek(f, addr, SEEK_SET) < 0) {
+ fprintf(stderr, "%s: %s: seek to %"
+ PRIx64 " failed: %s\n",
+ argv[0], argv[1], addr, strerror(errno));
+ }
+
+ if (fwrite(&rela.r_addend, sizeof(rela.r_addend), 1, f) != 1) {
+ fprintf(stderr, "%s: %s: write failed@%" PRIx64 "\n",
+ argv[0], argv[1], addr);
+ return 4;
+ }
+ }
+
+ if (fclose(f) < 0) {
+ fprintf(stderr, "%s: %s: close failed: %s\n",
+ argv[0], argv[1], strerror(errno));
+ return 4;
+ }
+
+ return 0;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 05/10] arm64: Turn u-boot.bin back into an ELF file after relocate-rela
2013-12-14 3:47 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 06/10] arm64: Make checkarmreloc accept arm64 relocations fenghua at phytium.com.cn
2013-12-14 5:09 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations Jagan Teki
1 sibling, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: Scott Wood <scottwood@freescale.com>
While performing relocations on u-boot.bin should be good enough for
booting on real hardware, some simulators insist on booting an ELF file
(and yet don't perform ELF relocations), so convert the relocated
binary back into an ELF file. This can go away in the future if we
change relocate-rela to operate directly on the ELF file, or if and
when we stop caring about a simulator with this restriction.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
Makefile | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Makefile b/Makefile
index 4a8e8c5..861f31e 100644
--- a/Makefile
+++ b/Makefile
@@ -358,6 +358,7 @@ ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
endif
+ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
@@ -526,6 +527,18 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
conv=notrunc 2>/dev/null
cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
+# Create a new ELF from a raw binary file. This is useful for arm64
+# where static relocation needs to be performed on the raw binary,
+# but certain simulators only accept an ELF file (but don't do the
+# relocation).
+# FIXME refactor dts/Makefile to share target/arch detection
+$(obj)u-boot.elf: $(obj)u-boot.bin
+ @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \
+ $< $(obj)u-boot-elf.o
+ @$(LD) $(obj)u-boot-elf.o -o $@ \
+ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
+ -Ttext=$(CONFIG_SYS_TEXT_BASE)
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 06/10] arm64: Make checkarmreloc accept arm64 relocations
2013-12-14 3:47 ` [U-Boot] [PATCH v16 05/10] arm64: Turn u-boot.bin back into an ELF file after relocate-rela fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 07/10] arm64: core support fenghua at phytium.com.cn
0 siblings, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
Makefile | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index 861f31e..e331d35 100644
--- a/Makefile
+++ b/Makefile
@@ -742,12 +742,16 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
$(MAKE) -C $@ all
endif # config.mk
-# ARM relocations should all be R_ARM_RELATIVE.
+# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
+# R_AARCH64_RELATIVE (64-bit).
checkarmreloc: $(obj)u-boot
- @if test "R_ARM_RELATIVE" != \
- "`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
- then echo "$< contains relocations other than \
- R_ARM_RELATIVE"; false; fi
+ @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
+ grep R_A | sort -u`"; \
+ if test "$$RELOC" != "R_ARM_RELATIVE" -a \
+ "$$RELOC" != "R_AARCH64_RELATIVE"; then \
+ echo "$< contains unexpected relocations: $$RELOC"; \
+ false; \
+ fi
$(VERSION_FILE):
@mkdir -p $(dir $(VERSION_FILE))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 07/10] arm64: core support
2013-12-14 3:47 ` [U-Boot] [PATCH v16 06/10] arm64: Make checkarmreloc accept arm64 relocations fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 08/10] arm64: generic board support fenghua at phytium.com.cn
0 siblings, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
arch/arm/config.mk | 7 +-
arch/arm/cpu/armv8/Makefile | 17 +++
arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++
arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++
arch/arm/cpu/armv8/config.mk | 15 +++
arch/arm/cpu/armv8/cpu.c | 43 ++++++
arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++
arch/arm/cpu/armv8/generic_timer.c | 31 +++++
arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++
arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++
arch/arm/cpu/armv8/tlb.S | 34 +++++
arch/arm/cpu/armv8/transition.S | 83 ++++++++++++
arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++
arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++
arch/arm/include/asm/byteorder.h | 12 ++
arch/arm/include/asm/cache.h | 5 +
arch/arm/include/asm/config.h | 6 +
arch/arm/include/asm/gic.h | 49 ++++++-
arch/arm/include/asm/global_data.h | 6 +-
arch/arm/include/asm/io.h | 15 ++-
arch/arm/include/asm/macro.h | 53 ++++++++
arch/arm/include/asm/posix_types.h | 10 ++
arch/arm/include/asm/proc-armv/ptrace.h | 21 +++
arch/arm/include/asm/proc-armv/system.h | 59 ++++++++-
arch/arm/include/asm/system.h | 84 ++++++++++++
arch/arm/include/asm/types.h | 4 +
arch/arm/include/asm/u-boot.h | 4 +
arch/arm/include/asm/unaligned.h | 2 +-
arch/arm/lib/Makefile | 20 ++-
arch/arm/lib/board.c | 7 +-
arch/arm/lib/bootm.c | 24 ++++
arch/arm/lib/crt0_64.S | 113 ++++++++++++++++
arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++
arch/arm/lib/relocate_64.S | 58 ++++++++
common/image.c | 1 +
doc/README.arm64 | 46 +++++++
examples/standalone/stubs.c | 15 +++
include/image.h | 1 +
38 files changed, 1882 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/cpu/armv8/Makefile
create mode 100644 arch/arm/cpu/armv8/cache.S
create mode 100644 arch/arm/cpu/armv8/cache_v8.c
create mode 100644 arch/arm/cpu/armv8/config.mk
create mode 100644 arch/arm/cpu/armv8/cpu.c
create mode 100644 arch/arm/cpu/armv8/exceptions.S
create mode 100644 arch/arm/cpu/armv8/generic_timer.c
create mode 100644 arch/arm/cpu/armv8/gic.S
create mode 100644 arch/arm/cpu/armv8/start.S
create mode 100644 arch/arm/cpu/armv8/tlb.S
create mode 100644 arch/arm/cpu/armv8/transition.S
create mode 100644 arch/arm/cpu/armv8/u-boot.lds
create mode 100644 arch/arm/include/asm/armv8/mmu.h
create mode 100644 arch/arm/lib/crt0_64.S
create mode 100644 arch/arm/lib/interrupts_64.c
create mode 100644 arch/arm/lib/relocate_64.S
create mode 100644 doc/README.arm64
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index fd3e5fb..329c7a7 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -17,7 +17,8 @@ endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
- -fno-common -ffixed-r9 -msoft-float
+ -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float)
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
@@ -105,4 +106,8 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
endif
# limit ourselves to the sections we want in the .bin.
+ifdef CONFIG_ARM64
+OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+else
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
+endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
new file mode 100644
index 0000000..b6eb6de
--- /dev/null
+++ b/arch/arm/cpu/armv8/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y := start.o
+
+obj-y += cpu.o
+obj-y += generic_timer.o
+obj-y += cache_v8.o
+obj-y += exceptions.o
+obj-y += cache.o
+obj-y += tlb.o
+obj-y += gic.o
+obj-y += transition.o
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
new file mode 100644
index 0000000..546a83e
--- /dev/null
+++ b/arch/arm/cpu/armv8/cache.S
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * This file is based on sample code from ARMv8 ARM.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * void __asm_flush_dcache_level(level)
+ *
+ * clean and invalidate one level cache.
+ *
+ * x0: cache level
+ * x1~x9: clobbered
+ */
+ENTRY(__asm_flush_dcache_level)
+ lsl x1, x0, #1
+ msr csselr_el1, x1 /* select cache level */
+ isb /* sync change of cssidr_el1 */
+ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
+ and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
+ add x2, x2, #4 /* x2 <- log2(cache line size) */
+ mov x3, #0x3ff
+ and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
+ add w4, w3, w3
+ sub w4, w4, 1 /* round up log2(#ways + 1) */
+ clz w5, w4 /* bit position of #ways */
+ mov x4, #0x7fff
+ and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
+ /* x1 <- cache level << 1 */
+ /* x2 <- line length offset */
+ /* x3 <- number of cache ways - 1 */
+ /* x4 <- number of cache sets - 1 */
+ /* x5 <- bit position of #ways */
+
+loop_set:
+ mov x6, x3 /* x6 <- working copy of #ways */
+loop_way:
+ lsl x7, x6, x5
+ orr x9, x1, x7 /* map way and level to cisw value */
+ lsl x7, x4, x2
+ orr x9, x9, x7 /* map set number to cisw value */
+ dc cisw, x9 /* clean & invalidate by set/way */
+ subs x6, x6, #1 /* decrement the way */
+ b.ge loop_way
+ subs x4, x4, #1 /* decrement the set */
+ b.ge loop_set
+
+ ret
+ENDPROC(__asm_flush_dcache_level)
+
+/*
+ * void __asm_flush_dcache_all(void)
+ *
+ * clean and invalidate all data cache by SET/WAY.
+ */
+ENTRY(__asm_flush_dcache_all)
+ dsb sy
+ mrs x10, clidr_el1 /* read clidr_el1 */
+ lsr x11, x10, #24
+ and x11, x11, #0x7 /* x11 <- loc */
+ cbz x11, finished /* if loc is 0, exit */
+ mov x15, lr
+ mov x0, #0 /* start flush at cache level 0 */
+ /* x0 <- cache level */
+ /* x10 <- clidr_el1 */
+ /* x11 <- loc */
+ /* x15 <- return address */
+
+loop_level:
+ lsl x1, x0, #1
+ add x1, x1, x0 /* x0 <- tripled cache level */
+ lsr x1, x10, x1
+ and x1, x1, #7 /* x1 <- cache type */
+ cmp x1, #2
+ b.lt skip /* skip if no cache or icache */
+ bl __asm_flush_dcache_level
+skip:
+ add x0, x0, #1 /* increment cache level */
+ cmp x11, x0
+ b.gt loop_level
+
+ mov x0, #0
+ msr csselr_el1, x0 /* resotre csselr_el1 */
+ dsb sy
+ isb
+ mov lr, x15
+
+finished:
+ ret
+ENDPROC(__asm_flush_dcache_all)
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+ENTRY(__asm_flush_dcache_range)
+ mrs x3, ctr_el0
+ lsr x3, x3, #16
+ and x3, x3, #0xf
+ mov x2, #4
+ lsl x2, x2, x3 /* cache line size */
+
+ /* x2 <- minimal cache line size in cache system */
+ sub x3, x2, #1
+ bic x0, x0, x3
+1: dc civac, x0 /* clean & invalidate data or unified cache */
+ add x0, x0, x2
+ cmp x0, x1
+ b.lo 1b
+ dsb sy
+ ret
+ENDPROC(__asm_flush_dcache_range)
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_icache_all)
+ ic ialluis
+ isb sy
+ ret
+ENDPROC(__asm_invalidate_icache_all)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
new file mode 100644
index 0000000..131fdab
--- /dev/null
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+static void set_pgtable_section(u64 section, u64 memory_type)
+{
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ u64 value;
+
+ value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ page_table[section] = value;
+}
+
+/* to activate the MMU we need to set up virtual memory */
+static void mmu_setup(void)
+{
+ int i, j, el;
+ bd_t *bd = gd->bd;
+
+ /* Setup an identity-mapping for all spaces */
+ for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
+ set_pgtable_section(i, MT_DEVICE_NGNRNE);
+
+ /* Setup an identity-mapping for all RAM space */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ulong start = bd->bi_dram[i].start;
+ ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
+ for (j = start >> SECTION_SHIFT;
+ j < end >> SECTION_SHIFT; j++) {
+ set_pgtable_section(j, MT_NORMAL);
+ }
+ }
+
+ /* load TTBR0 */
+ el = current_el();
+ if (el == 1)
+ asm volatile("msr ttbr0_el1, %0"
+ : : "r" (gd->arch.tlb_addr) : "memory");
+ else if (el == 2)
+ asm volatile("msr ttbr0_el2, %0"
+ : : "r" (gd->arch.tlb_addr) : "memory");
+ else
+ asm volatile("msr ttbr0_el3, %0"
+ : : "r" (gd->arch.tlb_addr) : "memory");
+
+ /* enable the mmu */
+ set_sctlr(get_sctlr() | CR_M);
+}
+
+/*
+ * Performs a invalidation of the entire data cache at all levels
+ */
+void invalidate_dcache_all(void)
+{
+ __asm_flush_dcache_all();
+}
+
+/*
+ * Performs a clean & invalidation of the entire data cache at all levels
+ */
+void flush_dcache_all(void)
+{
+ __asm_flush_dcache_all();
+}
+
+/*
+ * Invalidates range in all levels of D-cache/unified cache
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ __asm_flush_dcache_range(start, stop);
+}
+
+/*
+ * Flush range(clean & invalidate) from all levels of D-cache/unified cache
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ __asm_flush_dcache_range(start, stop);
+}
+
+void dcache_enable(void)
+{
+ /* The data cache is not active unless the mmu is enabled */
+ if (!(get_sctlr() & CR_M)) {
+ invalidate_dcache_all();
+ __asm_invalidate_tlb_all();
+ mmu_setup();
+ }
+
+ set_sctlr(get_sctlr() | CR_C);
+}
+
+void dcache_disable(void)
+{
+ uint32_t sctlr;
+
+ sctlr = get_sctlr();
+
+ /* if cache isn't enabled no need to disable */
+ if (!(sctlr & CR_C))
+ return;
+
+ set_sctlr(sctlr & ~(CR_C|CR_M));
+
+ flush_dcache_all();
+ __asm_invalidate_tlb_all();
+}
+
+int dcache_status(void)
+{
+ return (get_sctlr() & CR_C) != 0;
+}
+
+#else /* CONFIG_SYS_DCACHE_OFF */
+
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
+
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+
+void icache_enable(void)
+{
+ set_sctlr(get_sctlr() | CR_I);
+}
+
+void icache_disable(void)
+{
+ set_sctlr(get_sctlr() & ~CR_I);
+}
+
+int icache_status(void)
+{
+ return (get_sctlr() & CR_I) != 0;
+}
+
+void invalidate_icache_all(void)
+{
+ __asm_invalidate_icache_all();
+}
+
+#else /* CONFIG_SYS_ICACHE_OFF */
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void invalidate_icache_all(void)
+{
+}
+
+#endif /* CONFIG_SYS_ICACHE_OFF */
+
+/*
+ * Enable dCache & iCache, whether cache is actually enabled
+ * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
+ */
+void enable_caches(void)
+{
+ icache_enable();
+ dcache_enable();
+}
+
+/*
+ * Flush range from all levels of d-cache/unified-cache
+ */
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
new file mode 100644
index 0000000..027a68c
--- /dev/null
+++ b/arch/arm/cpu/armv8/config.mk
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-x18
+
+# SEE README.arm-unaligned-accesses
+PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
+PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
+
+PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
new file mode 100644
index 0000000..e06c3cc
--- /dev/null
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <linux/compiler.h>
+
+int cleanup_before_linux(void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * disable interrupt and turn off caches etc ...
+ */
+ disable_interrupts();
+
+ /*
+ * Turn off I-cache and invalidate it
+ */
+ icache_disable();
+ invalidate_icache_all();
+
+ /*
+ * turn off D-cache
+ * dcache_disable() in turn flushes the d-cache and disables MMU
+ */
+ dcache_disable();
+ invalidate_dcache_all();
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
new file mode 100644
index 0000000..b91a1b6
--- /dev/null
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/ptrace.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * Enter Exception.
+ * This will save the processor state that is ELR/X0~X30
+ * to the stack frame.
+ */
+.macro exception_entry
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ stp x17, x18, [sp, #-16]!
+ stp x15, x16, [sp, #-16]!
+ stp x13, x14, [sp, #-16]!
+ stp x11, x12, [sp, #-16]!
+ stp x9, x10, [sp, #-16]!
+ stp x7, x8, [sp, #-16]!
+ stp x5, x6, [sp, #-16]!
+ stp x3, x4, [sp, #-16]!
+ stp x1, x2, [sp, #-16]!
+
+ /* Could be running at EL3/EL2/EL1 */
+ switch_el x11, 3f, 2f, 1f
+3: mrs x1, esr_el3
+ mrs x2, elr_el3
+ b 0f
+2: mrs x1, esr_el2
+ mrs x2, elr_el2
+ b 0f
+1: mrs x1, esr_el1
+ mrs x2, elr_el1
+0:
+ stp x2, x0, [sp, #-16]!
+ mov x0, sp
+.endm
+
+/*
+ * Exception vectors.
+ */
+ .align 11
+ .globl vectors
+vectors:
+ .align 7
+ b _do_bad_sync /* Current EL Synchronous Thread */
+
+ .align 7
+ b _do_bad_irq /* Current EL IRQ Thread */
+
+ .align 7
+ b _do_bad_fiq /* Current EL FIQ Thread */
+
+ .align 7
+ b _do_bad_error /* Current EL Error Thread */
+
+ .align 7
+ b _do_sync /* Current EL Synchronous Handler */
+
+ .align 7
+ b _do_irq /* Current EL IRQ Handler */
+
+ .align 7
+ b _do_fiq /* Current EL FIQ Handler */
+
+ .align 7
+ b _do_error /* Current EL Error Handler */
+
+
+_do_bad_sync:
+ exception_entry
+ bl do_bad_sync
+
+_do_bad_irq:
+ exception_entry
+ bl do_bad_irq
+
+_do_bad_fiq:
+ exception_entry
+ bl do_bad_fiq
+
+_do_bad_error:
+ exception_entry
+ bl do_bad_error
+
+_do_sync:
+ exception_entry
+ bl do_sync
+
+_do_irq:
+ exception_entry
+ bl do_irq
+
+_do_fiq:
+ exception_entry
+ bl do_fiq
+
+_do_error:
+ exception_entry
+ bl do_error
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
new file mode 100644
index 0000000..223b95e
--- /dev/null
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+/*
+ * Generic timer implementation of get_tbclk()
+ */
+unsigned long get_tbclk(void)
+{
+ unsigned long cntfrq;
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+ return cntfrq;
+}
+
+/*
+ * Generic timer implementation of timer_read_counter()
+ */
+unsigned long timer_read_counter(void)
+{
+ unsigned long cntpct;
+ isb();
+ asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+ return cntpct;
+}
diff --git a/arch/arm/cpu/armv8/gic.S b/arch/arm/cpu/armv8/gic.S
new file mode 100644
index 0000000..599aa8f
--- /dev/null
+++ b/arch/arm/cpu/armv8/gic.S
@@ -0,0 +1,106 @@
+/*
+ * GIC Initialization Routines.
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/gic.h>
+
+
+/*************************************************************************
+ *
+ * void gic_init(void) __attribute__((weak));
+ *
+ * Currently, this routine only initialize secure copy of GIC
+ * with Security Extensions at EL3.
+ *
+ *************************************************************************/
+WEAK(gic_init)
+ branch_if_slave x0, 2f
+
+ /* Initialize Distributor and SPIs */
+ ldr x1, =GICD_BASE
+ mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */
+ str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */
+ ldr w0, [x1, GICD_TYPER]
+ and w2, w0, #0x1f /* ITLinesNumber */
+ cbz w2, 2f /* No SPIs */
+ add x1, x1, (GICD_IGROUPRn + 4)
+ mov w0, #~0 /* Config SPIs as Grp1 */
+1: str w0, [x1], #0x4
+ sub w2, w2, #0x1
+ cbnz w2, 1b
+
+ /* Initialize SGIs and PPIs */
+2: ldr x1, =GICD_BASE
+ mov w0, #~0 /* Config SGIs and PPIs as Grp1 */
+ str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */
+ mov w0, #0x1 /* Enable SGI 0 */
+ str w0, [x1, GICD_ISENABLERn]
+
+ /* Initialize Cpu Interface */
+ ldr x1, =GICC_BASE
+ mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */
+ /* Enable Ack Group1 Interrupt & */
+ /* EnableGrp0 & EnableGrp1 */
+ str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */
+
+ mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */
+ str w0, [x1, GICC_PMR]
+
+ ret
+ENDPROC(gic_init)
+
+
+/*************************************************************************
+ *
+ * void gic_send_sgi(u64 sgi) __attribute__((weak));
+ *
+ *************************************************************************/
+WEAK(gic_send_sgi)
+ ldr x1, =GICD_BASE
+ mov w2, #0x8000
+ movk w2, #0x100, lsl #16
+ orr w2, w2, w0
+ str w2, [x1, GICD_SGIR]
+ ret
+ENDPROC(gic_send_sgi)
+
+
+/*************************************************************************
+ *
+ * void wait_for_wakeup(void) __attribute__((weak));
+ *
+ * Wait for SGI 0 from master.
+ *
+ *************************************************************************/
+WEAK(wait_for_wakeup)
+ ldr x1, =GICC_BASE
+0: wfi
+ ldr w0, [x1, GICC_AIAR]
+ str w0, [x1, GICC_AEOIR]
+ cbnz w0, 0b
+ ret
+ENDPROC(wait_for_wakeup)
+
+
+/*************************************************************************
+ *
+ * void smp_kick_all_cpus(void) __attribute__((weak));
+ *
+ *************************************************************************/
+WEAK(smp_kick_all_cpus)
+ /* Kick secondary cpus up by SGI 0 interrupt */
+ mov x0, xzr /* SGI 0 */
+ mov x29, lr /* Save LR */
+ bl gic_send_sgi
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(smp_kick_all_cpus)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
new file mode 100644
index 0000000..bcc2603
--- /dev/null
+++ b/arch/arm/cpu/armv8/start.S
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ *************************************************************************/
+
+.globl _start
+_start:
+ b reset
+
+ .align 3
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+ .quad CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the linker script.
+ */
+.globl _end_ofs
+_end_ofs:
+ .quad _end - _start
+
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .quad __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .quad __bss_end - _start
+
+reset:
+ /*
+ * Could be EL3/EL2/EL1, Initial State:
+ * Little Endian, MMU Disabled, i/dCache Disabled
+ */
+ adr x0, vectors
+ switch_el x1, 3f, 2f, 1f
+3: msr vbar_el3, x0
+ msr cptr_el3, xzr /* Enable FP/SIMD */
+ ldr x0, =COUNTER_FREQUENCY
+ msr cntfrq_el0, x0 /* Initialize CNTFRQ */
+ b 0f
+2: msr vbar_el2, x0
+ mov x0, #0x33ff
+ msr cptr_el2, x0 /* Enable FP/SIMD */
+ b 0f
+1: msr vbar_el1, x0
+ mov x0, #3 << 20
+ msr cpacr_el1, x0 /* Enable FP/SIMD */
+0:
+
+ /* Cache/BPB/TLB Invalidate */
+ bl __asm_flush_dcache_all /* dCache clean&invalidate */
+ bl __asm_invalidate_icache_all /* iCache invalidate */
+ bl __asm_invalidate_tlb_all /* invalidate TLBs */
+
+ /* Processor specific initialization */
+ bl lowlevel_init
+
+ branch_if_master x0, x1, master_cpu
+
+ /*
+ * Slave CPUs
+ */
+slave_cpu:
+ wfe
+ ldr x1, =CPU_RELEASE_ADDR
+ ldr x0, [x1]
+ cbz x0, slave_cpu
+ br x0 /* branch to the given address */
+
+ /*
+ * Master CPU
+ */
+master_cpu:
+ bl _main
+
+/*-----------------------------------------------------------------------*/
+
+WEAK(lowlevel_init)
+ /* Initialize GIC Secure Bank Status */
+ mov x29, lr /* Save LR */
+ bl gic_init
+
+ branch_if_master x0, x1, 1f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent salves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+ bl wait_for_wakeup
+
+ /*
+ * All processors will enter EL2 and optionally EL1.
+ */
+ bl armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ bl armv8_switch_to_el1
+#endif
+
+1:
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
+
+/*-----------------------------------------------------------------------*/
+
+ENTRY(c_runtime_cpu_setup)
+ /* If I-cache is enabled invalidate it */
+#ifndef CONFIG_SYS_ICACHE_OFF
+ ic iallu /* I+BTB cache invalidate */
+ isb sy
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /*
+ * Setup MAIR and TCR.
+ */
+ ldr x0, =MEMORY_ATTRIBUTES
+ ldr x1, =TCR_FLAGS
+
+ switch_el x2, 3f, 2f, 1f
+3: orr x1, x1, TCR_EL3_IPS_BITS
+ msr mair_el3, x0
+ msr tcr_el3, x1
+ b 0f
+2: orr x1, x1, TCR_EL2_IPS_BITS
+ msr mair_el2, x0
+ msr tcr_el2, x1
+ b 0f
+1: orr x1, x1, TCR_EL1_IPS_BITS
+ msr mair_el1, x0
+ msr tcr_el1, x1
+0:
+#endif
+
+ /* Relocate vBAR */
+ adr x0, vectors
+ switch_el x1, 3f, 2f, 1f
+3: msr vbar_el3, x0
+ b 0f
+2: msr vbar_el2, x0
+ b 0f
+1: msr vbar_el1, x0
+0:
+
+ ret
+ENDPROC(c_runtime_cpu_setup)
diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S
new file mode 100644
index 0000000..f840b04
--- /dev/null
+++ b/arch/arm/cpu/armv8/tlb.S
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void __asm_invalidate_tlb_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_tlb_all)
+ switch_el x9, 3f, 2f, 1f
+3: tlbi alle3
+ dsb sy
+ isb
+ b 0f
+2: tlbi alle2
+ dsb sy
+ isb
+ b 0f
+1: tlbi vmalle1
+ dsb sy
+ isb
+0:
+ ret
+ENDPROC(__asm_invalidate_tlb_all)
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
new file mode 100644
index 0000000..e0a5946
--- /dev/null
+++ b/arch/arm/cpu/armv8/transition.S
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(armv8_switch_to_el2)
+ switch_el x0, 1f, 0f, 0f
+0: ret
+1:
+ mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
+ msr scr_el3, x0
+ msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
+ mov x0, #0x33ff
+ msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
+
+ /* Initialize SCTLR_EL2 */
+ msr sctlr_el2, xzr
+
+ /* Return to the EL2_SP2 mode from EL3 */
+ mov x0, sp
+ msr sp_el2, x0 /* Migrate SP */
+ mrs x0, vbar_el3
+ msr vbar_el2, x0 /* Migrate VBAR */
+ mov x0, #0x3c9
+ msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
+ msr elr_el3, lr
+ eret
+ENDPROC(armv8_switch_to_el2)
+
+ENTRY(armv8_switch_to_el1)
+ switch_el x0, 0f, 1f, 0f
+0: ret
+1:
+ /* Initialize Generic Timers */
+ mrs x0, cnthctl_el2
+ orr x0, x0, #0x3 /* Enable EL1 access to timers */
+ msr cnthctl_el2, x0
+ msr cntvoff_el2, x0
+ mrs x0, cntkctl_el1
+ orr x0, x0, #0x3 /* Enable EL0 access to timers */
+ msr cntkctl_el1, x0
+
+ /* Initilize MPID/MPIDR registers */
+ mrs x0, midr_el1
+ mrs x1, mpidr_el1
+ msr vpidr_el2, x0
+ msr vmpidr_el2, x1
+
+ /* Disable coprocessor traps */
+ mov x0, #0x33ff
+ msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
+ msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
+ mov x0, #3 << 20
+ msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
+
+ /* Initialize HCR_EL2 */
+ mov x0, #(1 << 31) /* 64bit EL1 */
+ orr x0, x0, #(1 << 29) /* Disable HVC */
+ msr hcr_el2, x0
+
+ /* SCTLR_EL1 initialization */
+ mov x0, #0x0800
+ movk x0, #0x30d0, lsl #16
+ msr sctlr_el1, x0
+
+ /* Return to the EL1_SP1 mode from EL2 */
+ mov x0, sp
+ msr sp_el1, x0 /* Migrate SP */
+ mrs x0, vbar_el2
+ msr vbar_el1, x0 /* Migrate VBAR */
+ mov x0, #0x3c5
+ msr spsr_el2, x0 /* EL1_SP1 | D | A | I | F */
+ msr elr_el2, lr
+ eret
+ENDPROC(armv8_switch_to_el1)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
new file mode 100644
index 0000000..4c12222
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(8);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(8);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(8);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(8);
+
+ . = .;
+
+ . = ALIGN(8);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(8);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ . = ALIGN(8);
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rela.dyn : {
+ *(.rela*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ . = ALIGN(8);
+
+ .bss_start : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss : {
+ *(.bss*)
+ . = ALIGN(8);
+ }
+
+ .bss_end : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
new file mode 100644
index 0000000..1193e76
--- /dev/null
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_MMU_H_
+#define _ASM_ARMV8_MMU_H_
+
+#ifdef __ASSEMBLY__
+#define _AC(X, Y) X
+#else
+#define _AC(X, Y) (X##Y)
+#endif
+
+#define UL(x) _AC(x, UL)
+
+/***************************************************************/
+/*
+ * The following definitions are related each other, shoud be
+ * calculated specifically.
+ */
+#define VA_BITS (42) /* 42 bits virtual address */
+
+/* PAGE_SHIFT determines the page size */
+#undef PAGE_SIZE
+#define PAGE_SHIFT 16
+#define PAGE_SIZE (1 << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT 29
+#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
+#define SECTION_MASK (~(SECTION_SIZE-1))
+/***************************************************************/
+
+/*
+ * Memory types
+ */
+#define MT_DEVICE_NGNRNE 0
+#define MT_DEVICE_NGNRE 1
+#define MT_DEVICE_GRE 2
+#define MT_NORMAL_NC 3
+#define MT_NORMAL 4
+
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
+ (0x04 << (MT_DEVICE_NGNRE*8)) | \
+ (0x0c << (MT_DEVICE_GRE*8)) | \
+ (0x44 << (MT_NORMAL_NC*8)) | \
+ (UL(0xff) << (MT_NORMAL*8)))
+
+/*
+ * Hardware page table definitions.
+ *
+ * Level 2 descriptor (PMD).
+ */
+#define PMD_TYPE_MASK (3 << 0)
+#define PMD_TYPE_FAULT (0 << 0)
+#define PMD_TYPE_TABLE (3 << 0)
+#define PMD_TYPE_SECT (1 << 0)
+
+/*
+ * Section
+ */
+#define PMD_SECT_S (3 << 8)
+#define PMD_SECT_AF (1 << 10)
+#define PMD_SECT_NG (1 << 11)
+#define PMD_SECT_PXN (UL(1) << 53)
+#define PMD_SECT_UXN (UL(1) << 54)
+
+/*
+ * AttrIndx[2:0]
+ */
+#define PMD_ATTRINDX(t) ((t) << 2)
+#define PMD_ATTRINDX_MASK (7 << 2)
+
+/*
+ * TCR flags.
+ */
+#define TCR_T0SZ(x) ((64 - (x)) << 0)
+#define TCR_IRGN_NC (0 << 8)
+#define TCR_IRGN_WBWA (1 << 8)
+#define TCR_IRGN_WT (2 << 8)
+#define TCR_IRGN_WBNWA (3 << 8)
+#define TCR_IRGN_MASK (3 << 8)
+#define TCR_ORGN_NC (0 << 10)
+#define TCR_ORGN_WBWA (1 << 10)
+#define TCR_ORGN_WT (2 << 10)
+#define TCR_ORGN_WBNWA (3 << 10)
+#define TCR_ORGN_MASK (3 << 10)
+#define TCR_SHARED_NON (0 << 12)
+#define TCR_SHARED_OUTER (1 << 12)
+#define TCR_SHARED_INNER (2 << 12)
+#define TCR_TG0_4K (0 << 14)
+#define TCR_TG0_64K (1 << 14)
+#define TCR_TG0_16K (2 << 14)
+#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
+#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
+#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
+
+/* PTWs cacheable, inner/outer WBWA and non-shareable */
+#define TCR_FLAGS (TCR_TG0_64K | \
+ TCR_SHARED_NON | \
+ TCR_ORGN_WBWA | \
+ TCR_IRGN_WBWA | \
+ TCR_T0SZ(VA_BITS))
+
+#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
index c3489f1..71a9966 100644
--- a/arch/arm/include/asm/byteorder.h
+++ b/arch/arm/include/asm/byteorder.h
@@ -23,10 +23,22 @@
# define __SWAB_64_THRU_32__
#endif
+#ifdef CONFIG_ARM64
+
+#ifdef __AARCH64EB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#else /* CONFIG_ARM64 */
+
#ifdef __ARMEB__
#include <linux/byteorder/big_endian.h>
#else
#include <linux/byteorder/little_endian.h>
#endif
+#endif /* CONFIG_ARM64 */
+
#endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 6d60a4a..ddebbc8 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -11,6 +11,8 @@
#include <asm/system.h>
+#ifndef CONFIG_ARM64
+
/*
* Invalidate L2 Cache using co-proc instruction
*/
@@ -28,6 +30,9 @@ void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
void dram_bank_mmu_setup(int bank);
+
+#endif
+
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 99b703e..abf79e5 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -9,4 +9,10 @@
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifdef CONFIG_ARM64
+#define CONFIG_PHYS_64BIT
+#define CONFIG_STATIC_RELA
+#endif
+
#endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index a0891cc..ac2b2bf 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -1,19 +1,54 @@
-#ifndef __GIC_V2_H__
-#define __GIC_V2_H__
+#ifndef __GIC_H__
+#define __GIC_H__
-/* register offsets for the ARM generic interrupt controller (GIC) */
+/* Register offsets for the ARM generic interrupt controller (GIC) */
#define GIC_DIST_OFFSET 0x1000
+#define GIC_CPU_OFFSET_A9 0x0100
+#define GIC_CPU_OFFSET_A15 0x2000
+
+/* Distributor Registers */
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
+#define GICD_IIDR 0x0008
+#define GICD_STATUSR 0x0010
+#define GICD_SETSPI_NSR 0x0040
+#define GICD_CLRSPI_NSR 0x0048
+#define GICD_SETSPI_SR 0x0050
+#define GICD_CLRSPI_SR 0x0058
+#define GICD_SEIR 0x0068
#define GICD_IGROUPRn 0x0080
-#define GICD_SGIR 0x0F00
+#define GICD_ISENABLERn 0x0100
+#define GICD_ICENABLERn 0x0180
+#define GICD_ISPENDRn 0x0200
+#define GICD_ICPENDRn 0x0280
+#define GICD_ISACTIVERn 0x0300
+#define GICD_ICACTIVERn 0x0380
+#define GICD_IPRIORITYRn 0x0400
+#define GICD_ITARGETSRn 0x0800
+#define GICD_ICFGR 0x0c00
+#define GICD_IGROUPMODRn 0x0d00
+#define GICD_NSACRn 0x0e00
+#define GICD_SGIR 0x0f00
+#define GICD_CPENDSGIRn 0x0f10
+#define GICD_SPENDSGIRn 0x0f20
+#define GICD_IROUTERn 0x6000
-#define GIC_CPU_OFFSET_A9 0x0100
-#define GIC_CPU_OFFSET_A15 0x2000
+/* Cpu Interface Memory Mapped Registers */
#define GICC_CTLR 0x0000
#define GICC_PMR 0x0004
+#define GICC_BPR 0x0008
#define GICC_IAR 0x000C
#define GICC_EOIR 0x0010
+#define GICC_RPR 0x0014
+#define GICC_HPPIR 0x0018
+#define GICC_ABPR 0x001c
+#define GICC_AIAR 0x0020
+#define GICC_AEOIR 0x0024
+#define GICC_AHPPIR 0x0028
+#define GICC_APRn 0x00d0
+#define GICC_NSAPRn 0x00e0
+#define GICC_IIDR 0x00fc
+#define GICC_DIR 0x1000
-#endif
+#endif /* __GIC_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index e126436..60e8726 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,10 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
+#ifdef CONFIG_ARM64
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
+#else
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
+#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531..6a1f05a 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+extern inline void __raw_writesb(unsigned long addr, const void *data,
+ int bytelen)
{
uint8_t *buf = (uint8_t *)data;
while(bytelen--)
__arch_putb(*buf++, addr);
}
-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+extern inline void __raw_writesw(unsigned long addr, const void *data,
+ int wordlen)
{
uint16_t *buf = (uint16_t *)data;
while(wordlen--)
__arch_putw(*buf++, addr);
}
-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+extern inline void __raw_writesl(unsigned long addr, const void *data,
+ int longlen)
{
uint32_t *buf = (uint32_t *)data;
while(longlen--)
__arch_putl(*buf++, addr);
}
-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
{
uint8_t *buf = (uint8_t *)data;
while(bytelen--)
*buf++ = __arch_getb(addr);
}
-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
{
uint16_t *buf = (uint16_t *)data;
while(wordlen--)
*buf++ = __arch_getw(addr);
}
-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
{
uint32_t *buf = (uint32_t *)data;
while(longlen--)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index ff13f36..f77e4b8 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -54,5 +54,58 @@
bcs 1b
.endm
+#ifdef CONFIG_ARM64
+/*
+ * Register aliases.
+ */
+lr .req x30
+
+/*
+ * Branch according to exception level
+ */
+.macro switch_el, xreg, el3_label, el2_label, el1_label
+ mrs \xreg, CurrentEL
+ cmp \xreg, 0xc
+ b.eq \el3_label
+ cmp \xreg, 0x8
+ b.eq \el2_label
+ cmp \xreg, 0x4
+ b.eq \el1_label
+.endm
+
+/*
+ * Branch if current processor is a slave,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro branch_if_slave, xreg, slave_label
+ mrs \xreg, mpidr_el1
+ tst \xreg, #0xff /* Test Affinity 0 */
+ b.ne \slave_label
+ lsr \xreg, \xreg, #8
+ tst \xreg, #0xff /* Test Affinity 1 */
+ b.ne \slave_label
+ lsr \xreg, \xreg, #8
+ tst \xreg, #0xff /* Test Affinity 2 */
+ b.ne \slave_label
+ lsr \xreg, \xreg, #16
+ tst \xreg, #0xff /* Test Affinity 3 */
+ b.ne \slave_label
+.endm
+
+/*
+ * Branch if current processor is a master,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro branch_if_master, xreg1, xreg2, master_label
+ mrs \xreg1, mpidr_el1
+ lsr \xreg2, \xreg1, #32
+ lsl \xreg1, \xreg1, #40
+ lsr \xreg1, \xreg1, #40
+ orr \xreg1, \xreg1, \xreg2
+ cbz \xreg1, \master_label
+.endm
+
+#endif /* CONFIG_ARM64 */
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_MACRO_H__ */
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
index c412486..9ba9add 100644
--- a/arch/arm/include/asm/posix_types.h
+++ b/arch/arm/include/asm/posix_types.h
@@ -13,6 +13,8 @@
#ifndef __ARCH_ARM_POSIX_TYPES_H
#define __ARCH_ARM_POSIX_TYPES_H
+#include <config.h>
+
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
@@ -28,9 +30,17 @@ typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
+
+#ifdef CONFIG_ARM64
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#else /* CONFIG_ARM64 */
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
+#endif /* CONFIG_ARM64 */
+
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
index a060ee6..21aef58 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -10,6 +10,25 @@
#ifndef __ASM_PROC_PTRACE_H
#define __ASM_PROC_PTRACE_H
+#ifdef CONFIG_ARM64
+
+#define PCMASK 0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+ unsigned long elr;
+ unsigned long regs[31];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
#define USR26_MODE 0x00
#define FIQ26_MODE 0x01
#define IRQ26_MODE 0x02
@@ -104,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_ARM64 */
+
#endif
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
index cda8976..693d1f4 100644
--- a/arch/arm/include/asm/proc-armv/system.h
+++ b/arch/arm/include/asm/proc-armv/system.h
@@ -13,6 +13,60 @@
/*
* Save the current interrupt enable state & disable IRQs
*/
+#ifdef CONFIG_ARM64
+
+/*
+ * Save the current interrupt enable state
+ * and disable IRQs/FIQs
+ */
+#define local_irq_save(flags) \
+ ({ \
+ asm volatile( \
+ "mrs %0, daif" \
+ "msr daifset, #3" \
+ : "=r" (flags) \
+ : \
+ : "memory"); \
+ })
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(flags) \
+ ({ \
+ asm volatile( \
+ "msr daif, %0" \
+ : \
+ : "r" (flags) \
+ : "memory"); \
+ })
+
+/*
+ * Enable IRQs/FIQs
+ */
+#define local_irq_enable() \
+ ({ \
+ asm volatile( \
+ "msr daifclr, #3" \
+ : \
+ : \
+ : "memory"); \
+ })
+
+/*
+ * Disable IRQs/FIQs
+ */
+#define local_irq_disable() \
+ ({ \
+ asm volatile( \
+ "msr daifset, #3" \
+ : \
+ : \
+ : "memory"); \
+ })
+
+#else /* CONFIG_ARM64 */
+
#define local_irq_save(x) \
({ \
unsigned long temp; \
@@ -107,7 +161,10 @@
: "r" (x) \
: "memory")
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+#endif /* CONFIG_ARM64 */
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
+ defined(CONFIG_ARM64)
/*
* On the StrongARM, "swp" is terminally broken since it bypasses the
* cache totally. This means that the cache becomes inconsistent, and,
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 760345f..4178f8c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,86 @@
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
+#ifdef CONFIG_ARM64
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M (1 << 0) /* MMU enable */
+#define CR_A (1 << 1) /* Alignment abort enable */
+#define CR_C (1 << 2) /* Dcache enable */
+#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
+#define CR_I (1 << 12) /* Icache enable */
+#define CR_WXN (1 << 19) /* Write Permision Imply XN */
+#define CR_EE (1 << 25) /* Exception (Big) Endian */
+
+#define PGTABLE_SIZE (0x10000)
+
+#ifndef __ASSEMBLY__
+
+#define isb() \
+ ({asm volatile( \
+ "isb" : : : "memory"); \
+ })
+
+#define wfi() \
+ ({asm volatile( \
+ "wfi" : : : "memory"); \
+ })
+
+static inline unsigned int current_el(void)
+{
+ unsigned int el;
+ asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
+ return el >> 2;
+}
+
+static inline unsigned int get_sctlr(void)
+{
+ unsigned int el, val;
+
+ el = current_el();
+ if (el == 1)
+ asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+ else if (el == 2)
+ asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
+ else
+ asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
+
+ return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+ unsigned int el;
+
+ el = current_el();
+ if (el == 1)
+ asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+ else if (el == 2)
+ asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
+ else
+ asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
+
+ asm volatile("isb");
+}
+
+void __asm_flush_dcache_all(void);
+void __asm_flush_dcache_range(u64 start, u64 end);
+void __asm_invalidate_tlb_all(void);
+void __asm_invalidate_icache_all(void);
+
+void armv8_switch_to_el2(void);
+void armv8_switch_to_el1(void);
+void gic_init(void);
+void gic_send_sgi(unsigned long sgino);
+void wait_for_wakeup(void);
+void smp_kick_all_cpus(void);
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
#ifdef __KERNEL__
#define CPU_ARCH_UNKNOWN 0
@@ -45,6 +125,8 @@
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
+#define PGTABLE_SIZE (4096 * 4)
+
/*
* This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust
@@ -132,4 +214,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
#endif /* __KERNEL__ */
+#endif /* CONFIG_ARM64 */
+
#endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 71dc049..2326420 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -39,7 +39,11 @@ typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
+#ifdef CONFIG_ARM64
+#define BITS_PER_LONG 64
+#else /* CONFIG_ARM64 */
#define BITS_PER_LONG 32
+#endif /* CONFIG_ARM64 */
/* Dma addresses are 32-bits wide. */
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index 2b5fce8..cb81232 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -44,6 +44,10 @@ typedef struct bd_info {
#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
+#ifndef CONFIG_ARM64
#define IH_ARCH_DEFAULT IH_ARCH_ARM
+#else
+#define IH_ARCH_DEFAULT IH_ARCH_ARM64
+#endif
#endif /* _U_BOOT_H_ */
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
index 44593a8..0a228fb 100644
--- a/arch/arm/include/asm/unaligned.h
+++ b/arch/arm/include/asm/unaligned.h
@@ -8,7 +8,7 @@
/*
* Select endianness
*/
-#ifndef __ARMEB__
+#if __BYTE_ORDER == __LITTLE_ENDIAN
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
#else
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 679f19a..321997c 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -17,14 +17,22 @@ lib-y += _umodsi3.o
lib-y += div0.o
endif
-obj-y += crt0.o
+ifdef CONFIG_ARM64
+obj-y += crt0_64.o
+else
+obj-y += crt0.o
+endif
ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
+ifdef CONFIG_ARM64
+obj-y += relocate_64.o
+else
+obj-y += relocate.o
+endif
ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
endif
-obj-y += sections.o
+obj-y += sections.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
@@ -35,11 +43,17 @@ else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
endif
+ifdef CONFIG_ARM64
+obj-y += interrupts_64.o
+else
obj-y += interrupts.o
+endif
obj-y += reset.o
obj-y += cache.o
+ifndef CONFIG_ARM64
obj-y += cache-cp15.o
+endif
# For EABI conformant tool chains, provide eabi_compat()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 9c72a53..b770e25 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -344,7 +344,7 @@ void board_init_f(ulong bootflag)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
- gd->arch.tlb_size = 4096 * 4;
+ gd->arch.tlb_size = PGTABLE_SIZE;
addr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
@@ -419,6 +419,7 @@ void board_init_f(ulong bootflag)
}
#endif
+#ifndef CONFIG_ARM64
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
@@ -431,6 +432,10 @@ void board_init_f(ulong bootflag)
/* 8-byte alignment for ABI compliance */
addr_sp &= ~0x07;
+#else /* CONFIG_ARM64 */
+ /* 16-byte alignment for ABI compliance */
+ addr_sp &= ~0x0f;
+#endif /* CONFIG_ARM64 */
#else
addr_sp += 128; /* leave 32 words for abort-stack */
gd->irq_sp = addr_sp;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index f476a89..77f1a5c 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -196,6 +196,14 @@ static void do_nonsec_virt_switch(void)
debug("entered non-secure state\n");
#endif
#endif
+
+#ifdef CONFIG_ARM64
+ smp_kick_all_cpus();
+ armv8_switch_to_el2();
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ armv8_switch_to_el1();
+#endif
+#endif
}
/* Subcommand: PREP */
@@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images)
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
+#ifdef CONFIG_ARM64
+ void (*kernel_entry)(void *fdt_addr);
+ int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+ kernel_entry = (void (*)(void *fdt_addr))images->ep;
+
+ debug("## Transferring control to Linux (at address %lx)...\n",
+ (ulong) kernel_entry);
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ announce_and_cleanup(fake);
+
+ if (!fake)
+ kernel_entry(images->ft_addr);
+#else
unsigned long machid = gd->bd->bi_arch_number;
char *s;
void (*kernel_entry)(int zero, int arch, uint params);
@@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (!fake)
kernel_entry(0, machid, r2);
+#endif
}
/* Main Entry point for arm bootm implementation
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
new file mode 100644
index 0000000..7756396
--- /dev/null
+++ b/arch/arm/lib/crt0_64.S
@@ -0,0 +1,113 @@
+/*
+ * crt0 - C-runtime startup Code for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2012
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ * This environment only provides a stack and a place to store
+ * the GD ('global data') structure, both located in some readily
+ * available RAM (SRAM, locked cache...). In this context, VARIABLE
+ * global data, initialized or not (BSS), are UNAVAILABLE; only
+ * CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ * execution from system RAM (DRAM, DDR...) As system RAM may not
+ * be available yet, , board_init_f() must use the current GD to
+ * store any data which must be passed on to later stages. These
+ * data include the relocation destination, the future stack, and
+ * the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ * ones allocated by board_init_f() in system RAM, but BSS and
+ * initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ * current location into the relocation destination computed by
+ * board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ * environment has BSS (initialized to 0), initialized non-const
+ * data (initialized to their intended value), and stack in system
+ * RAM. GD has retained values set by board_init_f(). Some CPUs
+ * have some work left to do at this point regarding memory, so
+ * call c_runtime_cpu_setup.
+ *
+ * 6. Branch to board_init_r().
+ */
+
+ENTRY(_main)
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
+ sub x0, x0, #GD_SIZE /* allocate one GD above SP */
+ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
+ mov x18, sp /* GD is above SP */
+ mov x0, #0
+ bl board_init_f
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
+ */
+ ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
+ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
+ ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */
+ sub x18, x18, #GD_SIZE /* new GD is below bd */
+
+ adr lr, relocation_return
+ ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
+ add lr, lr, x9 /* new return address after relocation */
+ ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */
+ b relocate_code
+
+relocation_return:
+
+/*
+ * Set up final (full) environment
+ */
+ bl c_runtime_cpu_setup /* still call old routine */
+
+/*
+ * Clear BSS section
+ */
+ ldr x0, =__bss_start /* this is auto-relocated! */
+ ldr x1, =__bss_end /* this is auto-relocated! */
+ mov x2, #0
+clear_loop:
+ str x2, [x0]
+ add x0, x0, #8
+ cmp x0, x1
+ b.lo clear_loop
+
+ /* call board_init_r(gd_t *id, ulong dest_addr) */
+ mov x0, x18 /* gd_t */
+ ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */
+ b board_init_r /* PC relative jump */
+
+ /* NOTREACHED - board_init_r() does not return */
+
+ENDPROC(_main)
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
new file mode 100644
index 0000000..b476722
--- /dev/null
+++ b/arch/arm/lib/interrupts_64.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+void enable_interrupts(void)
+{
+ return;
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ int i;
+
+ printf("ELR: %lx\n", regs->elr);
+ printf("LR: %lx\n", regs->regs[30]);
+ for (i = 0; i < 29; i += 2)
+ printf("x%-2d: %016lx x%-2d: %016lx\n",
+ i, regs->regs[i], i+1, regs->regs[i+1]);
+ printf("\n");
+}
+
+/*
+ * do_bad_sync handles the impossible case in the Synchronous Abort vector.
+ */
+void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_irq handles the impossible case in the Irq vector.
+ */
+void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_fiq handles the impossible case in the Fiq vector.
+ */
+void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_error handles the impossible case in the Error vector.
+ */
+void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_sync handles the Synchronous Abort exception.
+ */
+void do_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_irq handles the Irq exception.
+ */
+void do_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("\"Irq\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_fiq handles the Fiq exception.
+ */
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("\"Fiq\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_error handles the Error exception.
+ * Errors are more likely to be processor specific,
+ * it is defined with weak attribute and can be redefined
+ * in processor specific code.
+ */
+void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+ printf("\"Error\" handler, esr 0x%08x\n", esr);
+ show_regs(pt_regs);
+ panic("Resetting CPU ...\n");
+}
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
new file mode 100644
index 0000000..7fba9e2
--- /dev/null
+++ b/arch/arm/lib/relocate_64.S
@@ -0,0 +1,58 @@
+/*
+ * relocate - common relocation function for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * void relocate_code (addr_moni)
+ *
+ * This function relocates the monitor code.
+ * x0 holds the destination address.
+ */
+ENTRY(relocate_code)
+ /*
+ * Copy u-boot from flash to RAM
+ */
+ ldr x1, =__image_copy_start /* x1 <- SRC &__image_copy_start */
+ subs x9, x0, x1 /* x9 <- relocation offset */
+ b.eq relocate_done /* skip relocation */
+ ldr x2, =__image_copy_end /* x2 <- SRC &__image_copy_end */
+
+copy_loop:
+ ldp x10, x11, [x1], #16 /* copy from source address [x1] */
+ stp x10, x11, [x0], #16 /* copy to target address [x0] */
+ cmp x1, x2 /* until source end address [x2] */
+ b.lo copy_loop
+
+ /*
+ * Fix .rela.dyn relocations
+ */
+ ldr x2, =__rel_dyn_start /* x2 <- SRC &__rel_dyn_start */
+ ldr x3, =__rel_dyn_end /* x3 <- SRC &__rel_dyn_end */
+fixloop:
+ ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
+ ldr x4, [x2], #8 /* x4 <- addend */
+ and x1, x1, #0xffffffff
+ cmp x1, #1027 /* relative fixup? */
+ bne fixnext
+
+ /* relative fix: store addend plus offset at dest location */
+ add x0, x0, x9
+ add x4, x4, x9
+ str x4, [x0]
+fixnext:
+ cmp x2, x3
+ b.lo fixloop
+
+relocate_done:
+ ret
+ENDPROC(relocate_code)
diff --git a/common/image.c b/common/image.c
index b0ae58f..4145354 100644
--- a/common/image.c
+++ b/common/image.c
@@ -81,6 +81,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_NDS32, "nds32", "NDS32", },
{ IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",},
{ IH_ARCH_SANDBOX, "sandbox", "Sandbox", },
+ { IH_ARCH_ARM64, "arm64", "AArch64", },
{ -1, "", "", },
};
diff --git a/doc/README.arm64 b/doc/README.arm64
new file mode 100644
index 0000000..75586db
--- /dev/null
+++ b/doc/README.arm64
@@ -0,0 +1,46 @@
+U-boot for arm64
+
+Summary
+=======
+No hardware platform of arm64 is available now. The u-boot is
+simulated on Foundation Model and Fast Model for ARMv8.
+
+Notes
+=====
+
+1. Currenly, u-boot run at the highest exception level processor
+ supported and jump to EL2 or optionally EL1 before enter OS.
+
+2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
+ use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
+ is used to encode the initial addend of rela to u-boot.bin. After running,
+ the u-boot will be relocated to destination again.
+
+3. Fdt should be placed at a 2-megabyte boundary and within the first 512
+ megabytes from the start of the kernel image. So, fdt_high should be
+ defined specially.
+ Please reference linux/Documentation/arm64/booting.txt for detail.
+
+4. Spin-table is used to wake up secondary processors. One location
+ (or per processor location) is defined to hold the kernel entry point
+ for secondary processors. It must be ensured that the location is
+ accessible and zero immediately after secondary processor
+ enter slave_cpu branch execution in start.S. The location address
+ is encoded in cpu node of DTS. Linux kernel store the entry point
+ of secondary processors to it and send event to wakeup secondary
+ processors.
+ Please reference linux/Documentation/arm64/booting.txt for detail.
+
+5. Generic board is supported.
+
+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
+ aarch32 specific codes.
+
+Contributor
+===========
+ Tom Rini <trini@ti.com>
+ Scott Wood <scottwood@freescale.com>
+ York Sun <yorksun@freescale.com>
+ Simon Glass <sjg@chromium.org>
+ Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ Rob Herring <robherring2@gmail.com>
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 5d2ab56..32a19ce 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -39,6 +39,20 @@ gd_t *global_data;
" bctr\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11");
#elif defined(CONFIG_ARM)
+#ifdef CONFIG_ARM64
+/*
+ * x18 holds the pointer to the global_data, x9 is a call-clobbered
+ * register
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" ldr x9, [x18, %0]\n" \
+" ldr x9, [x9, %1]\n" \
+" br x9\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "x9");
+#else
/*
* r9 holds the pointer to the global_data, ip is a call-clobbered
* register
@@ -50,6 +64,7 @@ gd_t *global_data;
" ldr ip, [r9, %0]\n" \
" ldr pc, [ip, %1]\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip");
+#endif
#elif defined(CONFIG_MIPS)
/*
* k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
diff --git a/include/image.h b/include/image.h
index ee6eb8d..7de2bb2 100644
--- a/include/image.h
+++ b/include/image.h
@@ -156,6 +156,7 @@ struct lmb;
#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */
#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
+#define IH_ARCH_ARM64 22 /* ARM64 */
/*
* Image Types
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 08/10] arm64: generic board support
2013-12-14 3:47 ` [U-Boot] [PATCH v16 07/10] arm64: core support fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 09/10] arm64: board support of vexpress_aemv8a fenghua at phytium.com.cn
0 siblings, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
common/board_f.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index f0664bc..d918e4b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -462,7 +462,7 @@ static int reserve_round_4k(void)
static int reserve_mmu(void)
{
/* reserve TLB table */
- gd->arch.tlb_size = 4096 * 4;
+ gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
@@ -614,7 +614,7 @@ static int reserve_stacks(void)
* TODO(sjg at chromium.org): Perhaps create arch_reserve_stack()
* to handle this and put in arch/xxx/lib/stack.c
*/
-# ifdef CONFIG_ARM
+# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
# ifdef CONFIG_USE_IRQ
gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
@@ -811,11 +811,6 @@ static int mark_bootstage(void)
}
static init_fnc_t init_sequence_f[] = {
-#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
- !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
- !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
- zero_global_data,
-#endif
#ifdef CONFIG_SANDBOX
setup_ram_buf,
#endif
@@ -1009,6 +1004,17 @@ void board_init_f(ulong boot_flags)
gd = &data;
#endif
+ /*
+ * Clear global data before it is accessed at debug print
+ * in initcall_run_list. Otherwise the debug print probably
+ * get the wrong vaule of gd->have_console.
+ */
+#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
+ !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
+ !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
+ zero_global_data();
+#endif
+
gd->flags = boot_flags;
if (initcall_run_list(init_sequence_f))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 09/10] arm64: board support of vexpress_aemv8a
2013-12-14 3:47 ` [U-Boot] [PATCH v16 08/10] arm64: generic board support fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 10/10] arm64: MAKEALL, filter armv8 boards from LIST_arm fenghua at phytium.com.cn
0 siblings, 1 reply; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
board/armltd/vexpress64/Makefile | 8 ++
board/armltd/vexpress64/vexpress64.c | 56 ++++++++++
boards.cfg | 1 +
include/configs/vexpress_aemv8a.h | 189 ++++++++++++++++++++++++++++++++++
4 files changed, 254 insertions(+)
create mode 100644 board/armltd/vexpress64/Makefile
create mode 100644 board/armltd/vexpress64/vexpress64.c
create mode 100644 include/configs/vexpress_aemv8a.h
diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
new file mode 100644
index 0000000..e009141
--- /dev/null
+++ b/board/armltd/vexpress64/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vexpress64.o
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 0000000..2ec3bc9
--- /dev/null
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Clear spin table so that secondary processors
+ * observe the correct value after waken up from wfe.
+ */
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
diff --git a/boards.cfg b/boards.cfg
index b662149..7572f88 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -395,6 +395,7 @@ Active arm pxa - - vpac270
Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
+Active arm armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bie?mann <andreas.devel@googlemail.com>
Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
new file mode 100644
index 0000000..ce5f384
--- /dev/null
+++ b/include/configs/vexpress_aemv8a.h
@@ -0,0 +1,189 @@
+/*
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ * configurations.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_AEMV8A_H
+#define __VEXPRESS_AEMV8A_H
+
+#define DEBUG
+
+#define CONFIG_REMAKE_ELF
+
+/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
+
+/*#define CONFIG_SYS_GENERIC_BOARD*/
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_IDENT_STRING " vexpress_aemv8a"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_DEFAULT_DEVICE_TREE vexpress64
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0 0x00000000
+#define V2M_PA_CS1 0x14000000
+#define V2M_PA_CS2 0x18000000
+#define V2M_PA_CS3 0x1c000000
+#define V2M_PA_CS4 0x0c000000
+#define V2M_PA_CS5 0x10000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 16)
+#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE 0x80000000
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0 (V2M_PA_CS0)
+#define V2M_NOR1 (V2M_PA_CS4)
+#define V2M_SRAM (V2M_PA_CS1)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE (0x2C001000)
+#define GICC_BASE (0x2C002000)
+
+#define CONFIG_SYS_MEMTEST_START V2M_BASE
+#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/* SMSC9115 Ethernet from SMSC9118 family */
+#define CONFIG_SMC9111 1
+#define CONFIG_SMC9111_BASE (0x1a000000)
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX 0
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0 V2M_UART0
+#define CONFIG_SYS_SERIAL1 V2M_UART1
+
+/* Command line configuration */
+#define CONFIG_MENU
+/*#define CONFIG_MENU_SHOW*/
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PXE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=0x200000\0" \
+ "initrd_addr=0xa00000\0" \
+ "initrd_size=0x2000000\0" \
+ "fdt_addr=0x100000\0" \
+ "fdt_high=0xa0000000\0"
+
+#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTCOMMAND "bootm $kernel_addr " \
+ "$initrd_addr:$initrd_size $fdt_addr"
+#define CONFIG_BOOTDELAY -1
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT "VExpress64# "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#endif /* __VEXPRESS_AEMV8A_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 10/10] arm64: MAKEALL, filter armv8 boards from LIST_arm
2013-12-14 3:47 ` [U-Boot] [PATCH v16 09/10] arm64: board support of vexpress_aemv8a fenghua at phytium.com.cn
@ 2013-12-14 3:47 ` fenghua at phytium.com.cn
0 siblings, 0 replies; 19+ messages in thread
From: fenghua at phytium.com.cn @ 2013-12-14 3:47 UTC (permalink / raw)
To: u-boot
From: David Feng <fenghua@phytium.com.cn>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
---
MAKEALL | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/MAKEALL b/MAKEALL
index a74f0fc..562071a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -381,6 +381,12 @@ LIST_ARM11="$(targets_by_cpu arm1136) \
LIST_ARMV7="$(targets_by_cpu armv7)"
#########################################################################
+## ARMV8 Systems
+#########################################################################
+
+LIST_ARMV8="$(targets_by_cpu armv8)"
+
+#########################################################################
## AT91 Systems
#########################################################################
@@ -404,7 +410,11 @@ LIST_spear="$(targets_by_soc spear)"
## ARM groups
#########################################################################
-LIST_arm="$(targets_by_arch arm)"
+LIST_arm="$(targets_by_arch arm | \
+ for ARMV8_TARGET in $LIST_ARMV8; \
+ do sed "/$ARMV8_TARGET/d"; \
+ done) \
+"
#########################################################################
## MIPS Systems (default = big endian)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings
2013-12-14 3:47 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 03/10] add weak entry definition fenghua at phytium.com.cn
@ 2013-12-14 5:05 ` Jagan Teki
2013-12-19 14:27 ` FengHua
1 sibling, 1 reply; 19+ messages in thread
From: Jagan Teki @ 2013-12-14 5:05 UTC (permalink / raw)
To: u-boot
On Sat, Dec 14, 2013 at 9:17 AM, <fenghua@phytium.com.cn> wrote:
> From: David Feng <fenghua@phytium.com.cn>
>
> Signed-off-by: David Feng <fenghua@phytium.com.cn>
> ---
> common/cmd_pxe.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
> index db6b156..c27ec35 100644
> --- a/common/cmd_pxe.c
> +++ b/common/cmd_pxe.c
> @@ -59,7 +59,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len)
> uchar ethaddr[6];
>
> if (outbuf_len < 21) {
> - printf("outbuf is too small (%d < 21)\n", outbuf_len);
> + printf("outbuf is too small (%zd < 21)\n", outbuf_len);
>
> return -EINVAL;
> }
> @@ -103,7 +103,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
> path_len = (last_slash - bootfile) + 1;
>
> if (bootfile_path_size < path_len) {
> - printf("bootfile_path too small. (%d < %d)\n",
> + printf("bootfile_path too small. (%zd < %zd)\n",
> bootfile_path_size, path_len);
CHECK: Alignment should match open parenthesis
#40: FILE: common/cmd_pxe.c:107:
+ printf("bootfile_path too small. (%zd < %zd)\n",
bootfile_path_size, path_len);
--
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations
2013-12-14 3:47 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 05/10] arm64: Turn u-boot.bin back into an ELF file after relocate-rela fenghua at phytium.com.cn
@ 2013-12-14 5:09 ` Jagan Teki
2013-12-16 18:12 ` Scott Wood
1 sibling, 1 reply; 19+ messages in thread
From: Jagan Teki @ 2013-12-14 5:09 UTC (permalink / raw)
To: u-boot
On Sat, Dec 14, 2013 at 9:17 AM, <fenghua@phytium.com.cn> wrote:
> From: Scott Wood <scottwood@freescale.com>
>
> ARM64 uses the newer RELA-style relocations rather than the older REL.
> RELA relocations have an addend in the relocation struct, rather than
> expecting the loader to read a value from the location to be updated.
>
> While this is beneficial for ordinary program loading, it's problematic
> for U-Boot because the location to be updated starts out with zero,
> rather than a pre-relocation value. Since we need to be able to run C
> code before relocation, we need a tool to apply the relocations at
> build time.
>
> In theory this tool is applicable to other newer architectures (mainly
> 64-bit), but currently the only relocations it supports are for arm64,
> and it assumes a 64-bit little-endian target. If the latter limitation
> is ever to be changed, we'll need a way to tell the tool what format
> the image is in. Eventually this may be replaced by a tool that uses
> libelf or similar and operates directly on the ELF file. I've written
> some code for such an approach but libelf does not make it easy to poke
> addresses by memory address (rather than by section), and I was
> hesitant to write code to manually parse the program headers and do the
> update outside of libelf (or to iterate over sections) -- especially
> since it wouldn't get test coverage on things like binaries with
> multiple PT_LOAD segments. This should be good enough for now to let
> the manual relocation stuff be removed from the arm64 patches.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Signed-off-by: David Feng <fenghua@phytium.com.cn>
> ---
> Makefile | 12 ++++
> tools/Makefile | 6 ++
> tools/relocate-rela.c | 189 +++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 207 insertions(+)
> create mode 100644 tools/relocate-rela.c
>
> diff --git a/Makefile b/Makefile
> index 7310c4e..4a8e8c5 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -334,6 +334,17 @@ else
> BOARD_SIZE_CHECK =
> endif
>
> +# Statically apply RELA-style relocations (currently arm64 only)
> +ifneq ($(CONFIG_STATIC_RELA),)
> +# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
> +DO_STATIC_RELA = \
> + start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \
> + end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \
> + $(obj)tools/relocate-rela $(2) $(3) $$start $$end
> +else
> +DO_STATIC_RELA =
> +endif
> +
> # Always append ALL so that arch config.mk's can add custom ones
> ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
>
> @@ -376,6 +387,7 @@ $(obj)u-boot.srec: $(obj)u-boot
>
> $(obj)u-boot.bin: $(obj)u-boot
> $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
> + $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
> $(BOARD_SIZE_CHECK)
>
> $(obj)u-boot.ldr: $(obj)u-boot
> diff --git a/tools/Makefile b/tools/Makefile
> index 14d94e3..6d40398 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -59,6 +59,7 @@ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
> BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
> BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
> BIN_FILES-y += proftool(SFX)
> +BIN_FILES-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
>
> # Source files which exist outside the tools directory
> EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
> @@ -84,6 +85,7 @@ NOPED_OBJ_FILES-y += os_support.o
> NOPED_OBJ_FILES-y += pblimage.o
> NOPED_OBJ_FILES-y += proftool.o
> NOPED_OBJ_FILES-y += ublimage.o
> +NOPED_OBJ_FILES-y += relocate-rela.o
> OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
> OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
> OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
> @@ -250,6 +252,10 @@ $(obj)kwboot$(SFX): $(obj)kwboot.o
> $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
> $(HOSTSTRIP) $@
>
> +$(obj)relocate-rela$(SFX): $(obj)relocate-rela.o
> + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
> + $(HOSTSTRIP) $@
> +
> # Some of the tool objects need to be accessed from outside the tools directory
> $(obj)%.o: $(SRCTREE)/common/%.c
> $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
> diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
> new file mode 100644
> index 0000000..93b4c39
> --- /dev/null
> +++ b/tools/relocate-rela.c
> @@ -0,0 +1,189 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause
> + *
> + * 64-bit and little-endian target only until we need to support a different
> + * arch that needs this.
> + */
> +
> +#include <elf.h>
> +#include <errno.h>
> +#include <inttypes.h>
> +#include <stdarg.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +
> +#ifndef R_AARCH64_RELATIVE
> +#define R_AARCH64_RELATIVE 1027
> +#endif
> +
> +static const bool debug_en;
> +
> +static void debug(const char *fmt, ...)
> +{
> + va_list args;
> +
> + va_start(args, fmt);
> + if (debug_en)
> + vprintf(fmt, args);
> +}
> +
> +static bool supported_rela(Elf64_Rela *rela)
> +{
> + uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */
> + uint32_t type = rela->r_info & mask;
> +
> + switch (type) {
> +#ifdef R_AARCH64_RELATIVE
> + case R_AARCH64_RELATIVE:
> + return true;
> +#endif
> + default:
> + fprintf(stderr, "warning: unsupported relocation type %"
> + PRIu32 " at %" PRIx64 "\n",
> + type, rela->r_offset);
> +
> + return false;
> + }
> +}
> +
> +static inline uint64_t swap64(uint64_t val)
> +{
> + return ((val >> 56) & 0x00000000000000ffULL) |
> + ((val >> 40) & 0x000000000000ff00ULL) |
> + ((val >> 24) & 0x0000000000ff0000ULL) |
> + ((val >> 8) & 0x00000000ff000000ULL) |
> + ((val << 8) & 0x000000ff00000000ULL) |
> + ((val << 24) & 0x0000ff0000000000ULL) |
> + ((val << 40) & 0x00ff000000000000ULL) |
> + ((val << 56) & 0xff00000000000000ULL);
> +}
> +
> +#if __BYTE_ORDER == __LITTLE_ENDIAN
> +static inline uint64_t be64(uint64_t val)
> +{
> + return swap64(val);
> +}
> +
> +static inline uint64_t le64(uint64_t val)
> +{
> + return val;
> +}
> +#else
> +static inline uint64_t le64(uint64_t val)
> +{
> + return swap64(val);
> +}
> +
> +static inline uint64_t be64(uint64_t val)
> +{
> + return val;
> +}
> +#endif
> +
> +static bool read_num(const char *str, uint64_t *num)
> +{
> + char *endptr;
> + *num = strtoull(str, &endptr, 16);
> + return str[0] && !endptr[0];
> +}
> +
> +int main(int argc, char **argv)
> +{
> + FILE *f;
> + int i, num;
> + uint64_t rela_start, rela_end, text_base;
> +
> + if (argc != 5) {
> + fprintf(stderr, "Statically apply ELF rela relocations\n");
> + fprintf(stderr, "Usage: %s <bin file> <text base> " \
> + "<rela start> <rela end>\n", argv[0]);
Try to avoid unnecessary line continuations at fprintf
--
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations
2013-12-14 5:09 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations Jagan Teki
@ 2013-12-16 18:12 ` Scott Wood
0 siblings, 0 replies; 19+ messages in thread
From: Scott Wood @ 2013-12-16 18:12 UTC (permalink / raw)
To: u-boot
On Sat, 2013-12-14 at 10:39 +0530, Jagan Teki wrote:
> On Sat, Dec 14, 2013 at 9:17 AM, <fenghua@phytium.com.cn> wrote:
> > From: Scott Wood <scottwood@freescale.com>
> >
[snip]
> > + if (argc != 5) {
> > + fprintf(stderr, "Statically apply ELF rela relocations\n");
> > + fprintf(stderr, "Usage: %s <bin file> <text base> " \
> > + "<rela start> <rela end>\n", argv[0]);
>
> Try to avoid unnecessary line continuations at fprintf
FWIW, it wasn't like that it in my original patch. I'm guessing he
changed it due to checkpatch output; checkpatch recognizes printf() but
not fprintf(). It should probably be changed to recognize *printf(),
just as it recognizes *printk().
-Scott
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings
2013-12-14 5:05 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings Jagan Teki
@ 2013-12-19 14:27 ` FengHua
0 siblings, 0 replies; 19+ messages in thread
From: FengHua @ 2013-12-19 14:27 UTC (permalink / raw)
To: u-boot
> On Sat, Dec 14, 2013 at 9:17 AM, <fenghua@phytium.com.cn> wrote:
> > From: David Feng <fenghua@phytium.com.cn>
> >
> > Signed-off-by: David Feng <fenghua@phytium.com.cn>
> > ---
> > common/cmd_pxe.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
> > index db6b156..c27ec35 100644
> > --- a/common/cmd_pxe.c
> > +++ b/common/cmd_pxe.c
> > @@ -59,7 +59,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len)
> > uchar ethaddr[6];
> >
> > if (outbuf_len < 21) {
> > - printf("outbuf is too small (%d < 21)\n", outbuf_len);
> > + printf("outbuf is too small (%zd < 21)\n", outbuf_len);
> >
> > return -EINVAL;
> > }
> > @@ -103,7 +103,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
> > path_len = (last_slash - bootfile) + 1;
> >
> > if (bootfile_path_size < path_len) {
> > - printf("bootfile_path too small. (%d < %d)\n",
> > + printf("bootfile_path too small. (%zd < %zd)\n",
> > bootfile_path_size, path_len);
>
> CHECK: Alignment should match open parenthesis
> #40: FILE: common/cmd_pxe.c:107:
> + printf("bootfile_path too small. (%zd < %zd)\n",
> bootfile_path_size, path_len);
Yes, this should be fixed. I only replace %d with %z and did not notice the alignment.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 00/10] arm64 patch
2013-12-14 3:47 [U-Boot] [PATCH v16 00/10] arm64 patch fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support fenghua at phytium.com.cn
@ 2014-01-09 16:01 ` Albert ARIBAUD
2014-01-10 1:58 ` TigerLiu at viatech.com.cn
2014-01-10 9:17 ` Albert ARIBAUD
2 siblings, 1 reply; 19+ messages in thread
From: Albert ARIBAUD @ 2014-01-09 16:01 UTC (permalink / raw)
To: u-boot
Hi fenghua at phytium.com.cn,
On Sat, 14 Dec 2013 11:47:28 +0800, fenghua at phytium.com.cn wrote:
> From: David Feng <fenghua@phytium.com.cn>
>
> Changes for v16:
> - make the patches work with latest recently u-boot.
> add rela relocation type to OBJCFLAGS definition
> at arm/config.mk.
The series applies well and builds armv8 targets well if I set the
CROSS_COMPILE prefix to a 64-bit toolchain. However, if I use a 32-bit
toolchain prefix,
1) it still tries to build armv8 target, and fails understandably;
2) it causes the following boards to fail building:
trats2 snow smdk5250 vexpress_aemv8a smdkv310 origen s5pc210_universal
trats s5p_goni smdkc100 smdk5420 arndale
All with the same error, starting with:
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h:45:1:
error: unknown type name '__le64'
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h: In
function '__cpu_to_le64p':
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h:47:18:
error: '__le64' undeclared (first use in this function)
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h:47:18:
note: each undeclared identifier is reported only once for each function it appears in
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h: At
top level:
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h:49:1:
error: unknown type name '__le64'
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h:53:1:
error: unknown type name '__le32'
/home/albert/src/u-boot-arm/include/linux/byteorder/little_endian.h: In
function '__cpu_to_le32p':
Etc.
Can you look into it on your side and determine what causes this? I
don't necessarily need a v16 series; a bugfix patch is ok.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 00/10] arm64 patch
2014-01-09 16:01 ` [U-Boot] [PATCH v16 00/10] arm64 patch Albert ARIBAUD
@ 2014-01-10 1:58 ` TigerLiu at viatech.com.cn
2014-01-10 9:14 ` Albert ARIBAUD
0 siblings, 1 reply; 19+ messages in thread
From: TigerLiu at viatech.com.cn @ 2014-01-10 1:58 UTC (permalink / raw)
To: u-boot
Hi, Albtert:
How to download u-boot source code with arm64 patch code.
Such as :
Include arch/arm/cpu/armv8 directory.
I used "git clone git://www.denx.de/git/u-boot.git" to download source
code.
But not find arm64 patch code in the downloaded source code.
Best wishes,
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 00/10] arm64 patch
2014-01-10 1:58 ` TigerLiu at viatech.com.cn
@ 2014-01-10 9:14 ` Albert ARIBAUD
0 siblings, 0 replies; 19+ messages in thread
From: Albert ARIBAUD @ 2014-01-10 9:14 UTC (permalink / raw)
To: u-boot
Hi TigerLiu at viatech.com.cn,
On Fri, 10 Jan 2014 09:58:11 +0800, <TigerLiu@viatech.com.cn> wrote:
> Hi, Albtert:
> How to download u-boot source code with arm64 patch code.
> Such as :
> Include arch/arm/cpu/armv8 directory.
>
> I used "git clone git://www.denx.de/git/u-boot.git" to download source
> code.
> But not find arm64 patch code in the downloaded source code.
This is normal as the series is not yet applied to the ARM repo, let
alone the main repo.
I have just finished testing the series with the corrective patch from
Tom re: the 32-bit boards failing to build, and another patch from me
which prevents building 32-bit and 64-bit targets in a single 'MAKEALL
-a' command, as no toolchain currently exists that can build both types
of targets.
> Best wishes,
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v16 00/10] arm64 patch
2013-12-14 3:47 [U-Boot] [PATCH v16 00/10] arm64 patch fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support fenghua at phytium.com.cn
2014-01-09 16:01 ` [U-Boot] [PATCH v16 00/10] arm64 patch Albert ARIBAUD
@ 2014-01-10 9:17 ` Albert ARIBAUD
2 siblings, 0 replies; 19+ messages in thread
From: Albert ARIBAUD @ 2014-01-10 9:17 UTC (permalink / raw)
To: u-boot
Hi fenghua at phytium.com.cn,
On Sat, 14 Dec 2013 11:47:28 +0800, fenghua at phytium.com.cn wrote:
> From: David Feng <fenghua@phytium.com.cn>
>
> Changes for v16:
> - make the patches work with latest recently u-boot.
> add rela relocation type to OBJCFLAGS definition
> at arm/config.mk.
Applied to u-boot-arm, with Tom's (amended) patch
http://patchwork.ozlabs.org/patch/308941/ right above it.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2014-01-10 9:17 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-12-14 3:47 [U-Boot] [PATCH v16 00/10] arm64 patch fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 01/10] fdt_support: 64bit initrd start address support fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 03/10] add weak entry definition fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 05/10] arm64: Turn u-boot.bin back into an ELF file after relocate-rela fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 06/10] arm64: Make checkarmreloc accept arm64 relocations fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 07/10] arm64: core support fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 08/10] arm64: generic board support fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 09/10] arm64: board support of vexpress_aemv8a fenghua at phytium.com.cn
2013-12-14 3:47 ` [U-Boot] [PATCH v16 10/10] arm64: MAKEALL, filter armv8 boards from LIST_arm fenghua at phytium.com.cn
2013-12-14 5:09 ` [U-Boot] [PATCH v16 04/10] arm64: Add tool to statically apply RELA relocations Jagan Teki
2013-12-16 18:12 ` Scott Wood
2013-12-14 5:05 ` [U-Boot] [PATCH v16 02/10] cmd_pxe: remove compiling warnings Jagan Teki
2013-12-19 14:27 ` FengHua
2014-01-09 16:01 ` [U-Boot] [PATCH v16 00/10] arm64 patch Albert ARIBAUD
2014-01-10 1:58 ` TigerLiu at viatech.com.cn
2014-01-10 9:14 ` Albert ARIBAUD
2014-01-10 9:17 ` Albert ARIBAUD
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