From: Albert ARIBAUD <albert.u.boot@aribaud.net>
To: u-boot@lists.denx.de
Subject: [U-Boot] [Patch v2 1/3] armv8/cache: Consolidate setting for MAIR and TCR
Date: Wed, 26 Feb 2014 22:53:18 +0100 [thread overview]
Message-ID: <20140226225318.5c8f4c8a@lilith> (raw)
In-Reply-To: <1393449965-11420-1-git-send-email-yorksun@freescale.com>
Hi York,
On Wed, 26 Feb 2014 13:26:02 -0800, York Sun <yorksun@freescale.com>
wrote:
> Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
> sub-architecture.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> CC: David Feng <fenghua@phytium.com.cn>
> ---
> Changed since v1
> v1: Acked-by: David Feng <fenghua@phytium.com.cn>
> v2: No change.
Didn't a v3 already hit the list, and shouldn't this series be v4?
Amicalement,
--
Albert.
next prev parent reply other threads:[~2014-02-26 21:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-26 21:26 [U-Boot] [Patch v2 1/3] armv8/cache: Consolidate setting for MAIR and TCR York Sun
2014-02-26 21:26 ` [U-Boot] [Patch v2 2/3] armv8/cache: Flush D-cache, invalidate I-cache for relocation York Sun
2014-02-26 21:26 ` [U-Boot] [Patch v2 3/3] armv8/cache: Change cache invalidate and flush function York Sun
2014-02-26 21:53 ` Albert ARIBAUD [this message]
2014-02-26 21:58 ` [U-Boot] [Patch v2 1/3] armv8/cache: Consolidate setting for MAIR and TCR York Sun
2014-02-27 6:11 ` Albert ARIBAUD
2014-04-07 16:12 ` Albert ARIBAUD
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