From mboxrd@z Thu Jan  1 00:00:00 1970
From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Thu, 27 Feb 2014 07:11:48 +0100
Subject: [U-Boot] [Patch v2 1/3] armv8/cache: Consolidate setting for
 MAIR and TCR
In-Reply-To: <530E637C.2080500@freescale.com>
References: <1393449965-11420-1-git-send-email-yorksun@freescale.com>
	<20140226225318.5c8f4c8a@lilith> <530E637C.2080500@freescale.com>
Message-ID: <20140227071148.7aadbcb5@lilith>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi York,

On Wed, 26 Feb 2014 13:58:20 -0800, York Sun <yorksun@freescale.com>
wrote:

> On 02/26/2014 01:53 PM, Albert ARIBAUD wrote:
> > Hi York,
> > 
> > On Wed, 26 Feb 2014 13:26:02 -0800, York Sun <yorksun@freescale.com>
> > wrote:
> > 
> >> Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
> >> sub-architecture.
> >>
> >> Signed-off-by: York Sun <yorksun@freescale.com>
> >> CC: David Feng <fenghua@phytium.com.cn>
> >> ---
> >> Changed since v1
> >>  v1: Acked-by: David Feng <fenghua@phytium.com.cn>
> >>  v2: No change.
> > 
> > Didn't a v3 already hit the list, and shouldn't this series be v4?
> > 
> 
> Really? I don't recall. Did I leak an internal review patch to the list?
> Previous version is http://patchwork.ozlabs.org/patch/319067/

My mistake (and second one yesterday evening). V2 is fine.

> York

Amicalement,
-- 
Albert.