From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 26 Mar 2014 09:59:27 +0100
Subject: [U-Boot] [PATCH v2 2/9] sunxi: initial sun7i pinmux and gpio
	support
In-Reply-To: <1395822638.29683.9.camel@dagon.hellion.org.uk>
References: <1395438845.2234.95.camel@hastur.hellion.org.uk>
	<201403242154.12633.marex@denx.de>
	<1395822638.29683.9.camel@dagon.hellion.org.uk>
Message-ID: <201403260959.27436.marex@denx.de>
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On Wednesday, March 26, 2014 at 09:30:38 AM, Ian Campbell wrote:
> On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
> > > +     cfg = readl(&pio->cfg[0] + index);
> > > +     cfg &= ~(0xf << offset);
> > > +     cfg |= val << offset;
> > > +
> > > +     writel(cfg, &pio->cfg[0] + index);
> > 
> > clrsetbits_le32() here.
> 
> I looked at this transform in a few different contexts and one concern I
> had was that readl and writel have barriers in them (after the read and
> before the write respectively) while clrsetbits and friends do not. I
> don't think this will matter for the read/modify/write bit twiddling
> itself (since there are register dependencies) but I was slightly
> concerned that the barriers were hiding the lack of explicit barriers
> which would be required between the various reads/writes.
> 
> But I think I am probably being overly cautious here and the obvious
> transformation can be made. Anyone got any thoughts?

+CC Tom, Albert .

Best regards,
Marek Vasut