From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Fri, 18 Apr 2014 17:01:53 -0400 Subject: [U-Boot] [U-Boot, 1/3] pcnet: access descriptor rings & init block uncached In-Reply-To: <1396885308-61884-2-git-send-email-paul.burton@imgtec.com> References: <1396885308-61884-2-git-send-email-paul.burton@imgtec.com> Message-ID: <20140418210153.GY5698@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Apr 07, 2014 at 04:41:46PM +0100, Paul Burton wrote: > The prior accesses to the descriptor rings & init block via cached > memory had a few issues: > > - The memory needs cache flushes or invalidation at the appropriate > times, but was not necessarily aligned on cache line boundaries. > This could lead to data being incorrectly lost or written back to > RAM at the wrong time. > > - There are points where ordering of writes to the memory is > important, but because it's cached memory the pcnet controller > would see cache lines written back ordered by address. This could > occasionally lead to hardware seeing descriptors in an incorrect > state. > > - Flushing the cache constantly is inefficient. > > So, to avoid all of those issues simply access the descriptors & init > block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is > used to do this (retrieving an address in kseg1) as I could see no > existing generic solution. Since the MIPS Malta board is the only user > of the pcnet driver, hopefully this doesn't matter. > > Signed-off-by: Paul Burton Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: