From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 21 Aug 2014 07:02:28 +0200 Subject: [U-Boot] [PATCH v2 2/2] net: fec_mxc: Do not error out when FEC_TBD_READY In-Reply-To: References: <1408569876-28539-1-git-send-email-festevam@gmail.com> <201408210553.27015.marex@denx.de> Message-ID: <201408210702.29047.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote: > The TDAR bit is set when the descriptors are all out from TX ring, but the > descriptor properly is in transmitting not READY. I don't quite understand this, can you please rephrase ? > These are two signals, > and in Ic simulation, we found the TDAR always clear prior than the READY > bit of last BD. In mx6solox, we use a latest version of FEC IP. It looks > the intrinsic behave of TDAR bit is changed in this FEC version, not any > bug in mx6sx. OK, so this behavior is isolated to MX6SX and newer. Then any adjustment should focus solely on MX6SX and newer. > There are some solutions for this problem. Which would be acceptable? > 1. Change the TDAR polling to checking the READY bit in BD. This would return the cache-grinding, so this is not nice. > 2. Add polling the READY bit of BD after the TDAR polling. If this would be isolated to MX6SX only, then that is doable. > 3. Add a delay after the TDAR polling. This is just work. > > Best regards, > Ye Li Thanks for clarifying. Also, can you please stop top-posting when sending to mailing lists ? Best regards, Marek Vasut