[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut <marex@denx.de>]

On Thursday, August 21, 2014 at 06:12:08 PM, Fabio Estevam wrote:
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> Other SoCs work with the standard 32 bytes alignment.
> 
> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> which addresses the needs from mx6solox and also works for the other SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Use 64 bit alignment which covers mx6solox and the other SoCs as
> suggested by Stefan Roese
> 
>  drivers/net/fec_mxc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4cefda4..56178d4 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  #define FEC_XFER_TIMEOUT	5000
> 
> +/*
> + * The standard 32 DMA alignment does not work on mx6solox, which requires
> + * 64 alignment in the DMA RX FEC buffer.

Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there 
something completely else broken on MX6SX ?

[...]
Best regards,
Marek Vasut