[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, 
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Use 64 bit alignment which covers mx6solox and the other SoCs as suggested
by Stefan Roese
 
 drivers/net/fec_mxc.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cefda4..56178d4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define FEC_XFER_TIMEOUT	5000
 
+/*
+ * The standard 32 DMA alignment does not work on mx6solox, which requires
+ * 64 alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32)
+ */
+#define FEC_DMA_RX_MINALIGN	64
+
 #ifndef CONFIG_MII
 #error "CONFIG_MII has to be defined!"
 #endif
@@ -286,7 +294,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 	 * Reload the RX descriptors with default values and wipe
 	 * the RX buffers.
 	 */
-	size = roundup(dsize, ARCH_DMA_MINALIGN);
+	size = roundup(dsize, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < count; i++) {
 		data = (uint8_t *)fec->rbd_base[i].data_pointer;
 		memset(data, 0, dsize);
@@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec)
 	/* Allocate RX buffers. */
 
 	/* Maximum RX buffer size. */
-	size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+	size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < FEC_RBD_NUM; i++) {
-		data = memalign(ARCH_DMA_MINALIGN, size);
+		data = memalign(FEC_DMA_RX_MINALIGN, size);
 		if (!data) {
 			printf("%s: error allocating rxbuf %d\n", __func__, i);
 			goto err_ring;
-- 
1.9.1

[U-Boot] [PATCH v3 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

[Fabio Estevam]

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to fail.

As explained by Ye Li:

"The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly is in transmitting not READY. These are two signals, and in
Ic simulation, we found the TDAR always clear prior than the READY bit of last
BD. In mx6solox, we use a latest version of FEC IP. It looks the intrinsic 
behave of TDAR bit is changed in this FEC version, not any bug in mx6sx."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Poll FEC_TBD_READY after polling TDAR

 drivers/net/fec_mxc.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 56178d4..3050e58 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -719,12 +719,22 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
+	if (!timeout) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY))
+			break;
+	}
+
 	if (!timeout)
 		ret = -EINVAL;
 
+out:
 	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
-		ret = -EINVAL;
 
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
-- 
1.9.1

[U-Boot] [PATCH v3 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

[Marek Vasut]

On Thursday, August 21, 2014 at 06:12:09 PM, Fabio Estevam wrote:
> When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
> always cleared prior then the READY bit is set in the last BD, which causes
> FEC transmission to fail.
> 
> As explained by Ye Li:
> 
> "The TDAR bit is set when the descriptors are all out from TX ring, but the
> descriptor properly is in transmitting not READY. These are two signals,
> and in Ic simulation, we found the TDAR always clear prior than the READY
> bit of last BD. In mx6solox, we use a latest version of FEC IP. It looks
> the intrinsic behave of TDAR bit is changed in this FEC version, not any
> bug in mx6sx."
> 
> Fix this by polling the READY bit of BD after the TDAR polling, which
> covers the mx6solox case and does not harm for the other SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Poll FEC_TBD_READY after polling TDAR
> 
>  drivers/net/fec_mxc.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 56178d4..3050e58 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -719,12 +719,22 @@ static int fec_send(struct eth_device *dev, void
> *packet, int length) break;
>  	}
> 
> +	if (!timeout) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	timeout = FEC_XFER_TIMEOUT;
> +	while (--timeout) {
> +		if (!(readw(&fec->tbd_base[fec->tbd_index].status) & 
FEC_TBD_READY))

This will never work, because you never invalidate the memory over the DMA 
descriptor here.

> +			break;
> +	}
> +
>  	if (!timeout)
>  		ret = -EINVAL;
> 
> +out:
>  	invalidate_dcache_range(addr, addr + size);

And here you invalidate it for no reason ;-)

> -	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
> -		ret = -EINVAL;
> 
>  	debug("fec_send: status 0x%x index %d ret %i\n",
>  			readw(&fec->tbd_base[fec->tbd_index].status),

Best regards,
Marek Vasut

[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut]

On Thursday, August 21, 2014 at 06:12:08 PM, Fabio Estevam wrote:
> mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
> Other SoCs work with the standard 32 bytes alignment.
> 
> Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
> which addresses the needs from mx6solox and also works for the other SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v2:
> - Use 64 bit alignment which covers mx6solox and the other SoCs as
> suggested by Stefan Roese
> 
>  drivers/net/fec_mxc.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 4cefda4..56178d4 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
>   */
>  #define FEC_XFER_TIMEOUT	5000
> 
> +/*
> + * The standard 32 DMA alignment does not work on mx6solox, which requires
> + * 64 alignment in the DMA RX FEC buffer.

Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there 
something completely else broken on MX6SX ?

[...]
Best regards,
Marek Vasut

[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Fabio Estevam]

On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:

> Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there
> something completely else broken on MX6SX ?

Thanks for the review, Marek.

Inspecting this further I think the correct fix would be:

 arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb..e9e6f63 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,7 @@

 #define ARCH_MXC

-#define CONFIG_SYS_CACHELINE_SIZE    32
+#define CONFIG_SYS_CACHELINE_SIZE    64

Do you agree?

[U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

[Marek Vasut]

On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
> On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
> > there something completely else broken on MX6SX ?
> 
> Thanks for the review, Marek.
> 
> Inspecting this further I think the correct fix would be:
> 
>  arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 2631beb..e9e6f63 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,7 @@
> 
>  #define ARCH_MXC
> 
> -#define CONFIG_SYS_CACHELINE_SIZE    32
> +#define CONFIG_SYS_CACHELINE_SIZE    64

Well yeah, it would ;-)

Best regards,
Marek Vasut